Sensor structure

Abstract

The utility model provides a sensor structure, which comprises an acceptor substrate, a dielectric layer on the acceptor substrate and a stacking layer on the dielectric layer, and is characterized in that the stacking layer comprises a first doping layer, an intrinsic absorption layer and an intrinsic lead-out layer which are sequentially stacked in a first direction perpendicular to the surface of the acceptor substrate, the lead-out region of the intrinsic lead-out layer is doped by a second doping type to serve as a doping structure, or the intrinsic lead-out layer is doped by the second doping type to serve as a second doping layer. A first lead-out layer is arranged on the side, facing the acceptor substrate, of the stacking layer, and / or a second lead-out layer is arranged on the side, deviating from the acceptor substrate, of the doping structure or the second doping layer, the first lead-out layer is used for being connected with a first electrode, the second lead-out layer is used for being connected with a second electrode, and the doping concentration of the first lead-out layer is larger than that of the first doping layer; and the doping concentration of the second lead-out layer is greater than that of the doping structure or the second doping layer, so that the detection performance of the sensor is improved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductors, and in particular to a sensor structure. Background Art

[0002] Short-wave infrared imaging technology is widely used in defense, aerospace, rail transportation, industrial detection and university research. Commercial InGaAs short-wave infrared (SWIR) sensors use InGaAs materials as the intrinsic region and InP as the N-type and P-type regions. The band gap of the InGaAs intrinsic region can be adjusted by changing the content of In and Ga, which is very suitable for imaging applications in the 0.9-3μm short-wave infrared band. In view of the lattice matching of InP and InGaAs (In and Ga contents are 53% and 47% respectively), most InGaAs / InP short-wave infrared sensors are directly epitaxially formed on InP substrates, and their spectral response range is 0.9-1.7μm. This type of sensor has extremely low dark current at room temperature (the entire layer structure is completely lattice matched).

[0003] However, commercial InGaAs / InP short-wave infrared sensors have problems such as expensive InP substrates, small InP wafer size, high manufacturing costs, small number of sensors formed on a single wafer, low sensor yield, and inability to mass produce. How to form high-quality short-wave infrared sensors on a large-sized substrate is one of the important issues in achieving large-scale mass production. Utility Model Content

[0004] In view of this, the purpose of the present application is to provide a sensor structure that can form a high-quality short-wave infrared sensor on a large-sized substrate, thereby facilitating large-scale commercial use of the sensor.

[0005] The present application provides a sensor structure, including:

[0006] acceptor substrate;

[0007] a dielectric layer on the acceptor substrate;

[0008] The stacked layers on the dielectric layer include a first doped layer, an intrinsic absorption layer and an intrinsic extraction layer sequentially stacked in a first direction perpendicular to the surface of the acceptor substrate, the first doped layer has a first doping type, the extraction region of the intrinsic extraction layer is doped with a second doping type as a doped structure, or the intrinsic extraction layer is doped with the second doping type as a second doped layer, and the first doped layer, the intrinsic absorption layer and the intrinsic extraction layer include Group III and V elements;

[0009] The stacked layer faces a first lead-out layer on one side of the acceptor substrate, and / or the doping structure or the second doping layer faces a second lead-out layer on one side of the acceptor substrate, the first lead-out layer is used to connect a first electrode, and the second lead-out layer is used to connect a second electrode; the first lead-out layer and the second lead-out layer include Group III and V elements;

[0010] The first lead-out layer has a first doping type, and the doping concentration of the first lead-out layer is greater than the doping concentration of the first doping layer; the second lead-out layer has a second doping type, and the doping concentration of the second lead-out layer is greater than the doping concentration of the doping structure or the second doping layer.

[0011] Optionally, the material of the first lead-out layer or the second lead-out layer includes indium gallium arsenide, the material of the first doping layer and the intrinsic lead-out layer includes indium phosphide, and the material of the intrinsic absorption layer includes indium gallium arsenide.

[0012] Optionally, the intrinsic absorption layer includes a quantum well structure composed of multiple sub-absorption layers, and the quantum well structure includes at least one of the following quantum wells: InGaAs / InP quantum well, InGaAs / InAlAs quantum well, InGaAs / AlGaAs quantum well, InGaAs / InAlGaAs quantum well, InGaAs / InGaAsP quantum well, GaAsP / InGaAs quantum well and GaAsSb / InGaAs quantum well.

[0013] Optionally, the first doping type is P type, the second doping type is N type, and the doping concentration of the intrinsic absorption layer is not higher than 2×10^16cm- 3 The doping concentration of the first lead-out layer or the second lead-out layer is not less than 5×10^18cm- 3 The doping concentration of the first doping layer is not less than 1×10^18cm- 3 The doping concentration of the doping structure or the second doping layer is not less than 2×10^18cm -3 .

[0014] Optionally, the dielectric layer includes a ferroelectric oxide layer.

[0015] Optionally, the dielectric layer includes an aluminum oxide layer and a ferroelectric oxide layer stacked in sequence.

[0016] Optionally, an insulating layer is further included between the acceptor substrate and the dielectric layer, and the insulating layer includes a stack of a silicon oxide layer and a TEOS layer, or a stack of polysilicon and silicon oxide, or a stack of silicon oxide / silicon nitride / silicon oxide.

[0017] Optionally, the sensor structure further includes:

[0018] A passivation layer covers the stacked layer, the first electrode penetrates the passivation layer on the first doped layer, and the second electrode penetrates the doped structure or the passivation layer on the second doped layer; the material of the passivation layer is ferroelectric oxide.

[0019] Optionally, the stacked layer is isolated into a plurality of parts by an isolation groove along the first direction, and each part serves as a picture element corresponding to a group of paired first electrodes and second electrodes.

[0020] Optionally, the sensor structure further includes:

[0021] the first electrode and the second electrode;

[0022] The readout circuit wafer on the first electrode and the second electrode has a readout circuit, and the readout circuit is connected to the first electrode and the second electrode respectively.

[0023] The present application provides a sensor structure, which includes an acceptor substrate, a dielectric layer on the acceptor substrate, and a stacked layer on the dielectric layer. The stacked layer includes a first doping layer, an intrinsic absorption layer, and an intrinsic extraction layer stacked in sequence along a first direction perpendicular to the surface of the acceptor substrate. The first doping layer has a first doping type, and the extraction region of the intrinsic extraction layer is doped with a second doping type as a doping structure, or the intrinsic extraction layer is doped with a second doping type as a second doping layer. The first doping layer, the intrinsic absorption layer, and the intrinsic extraction layer include Group III and V elements. The first extraction layer can be arranged on a side of the stacked layer facing the acceptor substrate, or the second extraction layer can be arranged on a side of the doping structure or the second doping layer facing away from the acceptor substrate. The first extraction layer is used to connect the first electrode, and the second extraction layer is used to connect the second electrode. The first extraction layer and the second extraction layer include Group III and V elements. The first extraction layer has a first doping type, and the doping concentration of the first extraction layer is greater than the doping concentration of the first doping layer. The second extraction layer has a second doping type, and the doping concentration of the second extraction layer is greater than the doping concentration of the doping structure or the second doping layer.

[0024] In this way, the stacked layer is not directly formed on the acceptor substrate, and the acceptor substrate can be a non-indium phosphide substrate, so its size is not limited, and a large-size structure can be realized at low cost. In addition, the first electrode is connected through a first lead-out layer with a higher doping concentration, and the second electrode is connected through a second lead-out layer with a higher doping concentration, that is, by setting an additional lead-out layer outside the stacked layer, good contact with the electrode is achieved, which improves the contact quality, reduces the contact resistance, and improves the detection performance of the sensor compared to directly connecting the electrode to the first doping layer or doping structure or second doping layer with a lower doping concentration. In summary, this solution can form a high-quality short-wave infrared sensor on a large-size substrate, which is conducive to the large-scale commercial use of the sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A schematic diagram of a sensor structure provided by an embodiment of the present application is shown;

[0027] Figure 2 A schematic diagram of another sensor structure provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of another sensor structure provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of another sensor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0032] This application is described in detail with reference to schematic diagrams. When describing the embodiments of this application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of this application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0033] In order to better understand the technical solution and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0034] The present application provides a sensor structure, which includes an acceptor substrate, a dielectric layer on the acceptor substrate, and a stacked layer on the dielectric layer. The stacked layer includes a first doping layer, an intrinsic absorption layer, and an intrinsic extraction layer stacked in sequence along a first direction perpendicular to the surface of the acceptor substrate. The first doping layer has a first doping type, and the extraction region of the intrinsic extraction layer is doped with a second doping type as a doping structure, or the intrinsic extraction layer is doped with a second doping type as a second doping layer. The first doping layer, the intrinsic absorption layer, and the intrinsic extraction layer include Group III and V elements. The first extraction layer can be arranged on a side of the stacked layer facing the acceptor substrate, or the second extraction layer can be arranged on a side of the doping structure or the second doping layer facing away from the acceptor substrate. The first extraction layer is used to connect the first electrode, and the second extraction layer is used to connect the second electrode. The first extraction layer and the second extraction layer include Group III and V elements. The first extraction layer has a first doping type, and the doping concentration of the first extraction layer is greater than the doping concentration of the first doping layer. The second extraction layer has a second doping type, and the doping concentration of the second extraction layer is greater than the doping concentration of the doping structure or the second doping layer.

[0035] In this way, the stacked layer is not directly formed on the acceptor substrate, and the acceptor substrate can be a non-indium phosphide substrate, so its size is not limited, and a large-size structure can be realized at low cost. In addition, the first electrode is connected through a first lead-out layer with a higher doping concentration, and the second electrode is connected through a second lead-out layer with a higher doping concentration, that is, by setting an additional lead-out layer outside the stacked layer, good contact with the electrode is achieved, which improves the contact quality, reduces the contact resistance, and improves the detection performance of the sensor compared to directly connecting the electrode to the first doping layer or doping structure or second doping layer with a lower doping concentration. In summary, this solution can form a high-quality short-wave infrared sensor on a large-size substrate, which is conducive to the large-scale commercial use of the sensor.

[0036] Since the above solution involves two stacking layers, the two stacking layers will be introduced separately below.

[0037] See also Figure 1 , which is a schematic diagram of a sensor structure provided in an embodiment of the present application, the sensor structure includes: a host substrate 100, a dielectric layer 250 / 280 on the host substrate 100, and a stacked layer 210 / 220 / 230 on the dielectric layer.

[0038] In the embodiment of the present application, the acceptor substrate 100 is used to provide support for the film layer thereon, and can be a conductor substrate or an insulating substrate, for example, a silicon substrate, a sapphire substrate or a glass substrate. The size of the acceptor substrate 100 is usually large, so a sensor on a large-size substrate can be formed, which is conducive to the large-scale commercial use of the sensor structure. The size (diameter or side length) of the acceptor substrate 100 can be, for example, ≥8 inches, which is conducive to reducing manufacturing costs.

[0039] The stacked layers include a first doping layer 230, an intrinsic absorption layer 220, and an intrinsic extraction layer 210 stacked in sequence along a first direction (i.e., longitudinal direction) perpendicular to the surface of the acceptor substrate. The first doping layer 230 has a first doping type, and the extraction region of the intrinsic extraction layer 210 is doped with a second doping type as a doping structure 211. The first doping layer 230, the intrinsic absorption layer 220, and the intrinsic extraction layer 210 include Group III and V elements. The first doping type and the second doping type are opposite, the first doping type can be one of P-type doping and N-type doping, and the second doping type can be the other of P-type doping and N-type doping, for example, the first doping type can be P-type doping, and the second doping type can be N-type doping. In this way, the stacked layers constitute a vertical PIN structure (Vertical PIN Structure), and the first doping layer 230 and the doping structure 211 in the intrinsic extraction layer 210 can respectively serve as an electron transport layer and a hole transport layer for charge response.

[0040] The material of the intrinsic absorption layer 220 may include indium gallium arsenide. The band gap of the intrinsic region of InGaAs can be adjusted by changing the content of In and Ga, which is very suitable for imaging applications in the 0.9-3μm short-wave infrared band. For example, the content of In and Ga is 53% and 47% respectively, and its spectral response range is 0.9-1.7μm. The doping concentration of the intrinsic absorption layer 220 is not higher than 2×10^16cm- 3 The thickness of the intrinsic absorption layer 220 is in the range of 500-3000 nm.

[0041] The intrinsic absorption layer 220 may include only InGaAs, or may include a quantum well structure composed of multiple sub-absorption layers, wherein the quantum well structure includes at least one of the following quantum wells: InGaAs / InP quantum well, InGaAs / InAlAs quantum well, InGaAs / AlGaAs quantum well, InGaAs / InAlGaAs quantum well, InGaAs / InGaAsP quantum well, GaAsP / InGaAs quantum well, and GaAsSb / InGaAs quantum well. In this way, the absorption efficiency of the intrinsic absorption layer 220 can be improved, and the photosensitivity of the sensor can be improved.

[0042] The material of the first doping layer 230 and the intrinsic extraction layer 210 can be indium phosphide. In the doping structure 211 in the first doping layer 230 and the intrinsic extraction layer 210, the doping element of P-type doping can include Zn, etc., and the doping element of N-type doping can include Si, etc. Generally speaking, the first doping layer 230 and the doping structure 211 can realize the extraction of charges, which can directly connect the first electrode and the second electrode. When the doping type of the first doping layer 230 or the doping structure 211 is P-type doping, the doping concentration is not less than 1×10^18cm- 3When the doping type of the first doping layer 230 or the doping structure 211 is N-type doping, the doping concentration is not less than 2×10^18cm- 3 , the doping concentration of the intrinsic extraction layer 210 is not higher than 2×10^16cm- 3 The thickness of the first doping layer 230 may be in the range of 100-500 nm, and the thickness of the intrinsic extraction layer 210 may be in the range of 100-500 nm.

[0043] However, the inventors have found through research that at least one of the first doping layer 230 and the doping structure 211 has a problem of low effective doping concentration, for example, the P-type effective doping concentration of InP is relatively low, and the P-type doping concentration of InP cannot be further increased. This results in a large contact resistance between the doping layer and the corresponding electrode, which is not conducive to improving the sensor performance.

[0044] Therefore, a first lead-out layer 240 may be provided on the side of the stacked layer facing the acceptor substrate 100, that is, the first lead-out layer 240 may be provided between the dielectric layer and the stacked layer, and the first lead-out layer 240 is used to connect the first electrode, and has a first doping type, including Group III and V elements, and the doping concentration of the first lead-out layer 240 is greater than the doping concentration of the first doping layer 230. Thus, by connecting the first electrode through the added first lead-out layer 240, a good ohmic contact is formed, with higher contact quality and lower contact resistance, compared with directly connecting the first electrode through the first doping layer 230.

[0045] Similarly, a second lead-out layer (not shown) may be provided on the side of the doping structure 211 away from the acceptor substrate 100, that is, a second lead-out layer may be provided on the stacked layer, the second lead-out layer is used to connect the second electrode, has a second doping type, includes Group III and V elements, and the doping concentration of the second lead-out layer is greater than the doping concentration of the doping structure 211. Thus, the second electrode is connected by the added second lead-out layer, and a good ohmic contact is formed, with higher contact quality and lower contact resistance, compared with connecting the second electrode through the doping structures 211.

[0046] In the embodiment of the present application, only one of the first lead-out layer 240 and the second lead-out layer may be provided, or both may be provided. In the following example, the first lead-out layer 240 is provided as an example for explanation. In actual operation, the first lead-out layer 240 may be provided when the doping concentration of the first doping layer 230 is low, and the second lead-out layer may be provided when the doping concentration of the doping structure 211 is low, thereby improving the contact quality at the corresponding position.

[0047] The materials of the first lead-out layer 240 and the second lead-out layer may include indium gallium arsenide. When the doping type of the first lead-out layer 240 or the second lead-out layer is P-type doping, the doping concentration is not less than 5×10^18cm- 3 .

[0048] The dielectric layer is used to isolate the acceptor substrate 100 and the stacked layer. The dielectric layer may include an insulating material, such as a ferroelectric oxide, or other insulating materials, such as silicon oxide, aluminum oxide, etc. As a possible implementation, the dielectric layer includes at least one of a ferroelectric oxide (Ferroelectric Oxide) layer 250 and an aluminum oxide (Al2O3) layer 280. The ferroelectric oxide layer 250 has a negative capacitance effect, and its capacitance is negative in the sensor structure working device, which effectively compensates for the larger positive capacitance in the sensor structure, thereby reducing the capacitance value in the entire germanium sensor, and can simultaneously achieve high responsiveness and high operating speed; the ferroelectric oxide layer 250 is also an effective insulating layer, which can effectively improve the defect state existing at the interface between germanium and other film layers (such as the acceptor substrate or buried oxide layer). In other words, the ferroelectric oxide has the functions of both electrical insulation and capacitance compensation.

[0049] The aluminum oxide layer 280 can be used as a bonding layer to bond the aluminum oxide layer 280 and the acceptor substrate together. The aluminum oxide layer 280 can be disposed on the side of the ferroelectric oxide away from the acceptor substrate 100. The thickness of the ferroelectric oxide layer 250 is in the range of 10-1000 nm, and the thickness of the aluminum oxide layer 280 is in the range of 10-1000 nm.

[0050] The material of the ferroelectric oxide layer 250 is ferroelectric oxide, and its types include but are not limited to Hf 0.5 Zr 0.5 Stacking structures such as O2, BaTiO3, PZT, LiNbO3, SrRuO3, SrTiO3, PbTiO3, (Pb, Sr)TiO3 / SrTiO3 (PST / STO) superlattice and (Ba, Sr)TiO3 / LaAlO3 superlattice.

[0051] refer to Figure 2 As shown, a schematic diagram of another sensor structure provided in an embodiment of the present application, an insulating layer may also be provided between the dielectric layer and the acceptor substrate 100, and the insulating layer may enhance the interaction between the light and the sensing layer, which is beneficial to the improvement of the light responsiveness. The insulating layer may also be used as a bonding layer, bonded to the aforementioned aluminum oxide layer 280. The insulating layer may be a single layer or a stacked layer. When the insulating layer is a single layer, it may be a silicon oxide layer. When the insulating layer is a stacked layer, it may be a stack of a silicon oxide layer 110 and a silicon oxide (denoted as a TEOS layer) 120 formed using tetraethyl orthosilicate (TEOS), or a stack of polycrystalline silicon and silicon oxide, or a stack of silicon oxide / silicon nitride / silicon oxide, etc. The insulating layer may constitute a distributed Bragg reflector (DBR). The thickness of the insulating layer may be 100-1000nm.

[0052] That is to say, from the acceptor substrate 100 upwards, the sensor structure may include vertically stacked insulator layers such as the silicon oxide layer 110, the TEOS layer 120, the aluminum oxide layer 280 and the ferroelectric oxide layer 250 in sequence. The illumination direction of the sensor structure is usually longitudinal, so that the interfaces of the aforementioned insulator layers and the stacked layers can reflect light, which is equivalent to increasing the vertical resonant cavity effect, improving the light absorption efficiency, and further improving the key performance indicators of the sensor such as dark current, quantum efficiency and responsiveness.

[0053] The sensor structure may further include a passivation layer 290 on the stacked layer, and the passivation layer 290 is used to protect the stacked layer. The material of the passivation layer 290 is an insulating material, for example, it may be a ferroelectric oxide, or it may be other insulating materials, such as silicon oxide. When the material of the passivation layer 290 is a ferroelectric oxide, it can also compensate for the larger positive capacitance in the sensor structure, and also serve as an insulating layer to achieve effective insulation.

[0054] The first electrode 260 may penetrate the passivation layer 290 on the first doping layer 230, and the second electrode 270 may penetrate the passivation layer 290 on the doping structure 211. When the sensor structure includes a first lead-out layer 240, the first electrode 260 penetrates the passivation layer 290 on the surface of the first lead-out layer 240 so as to be connected to the first lead-out layer 240. When the sensor structure includes a second lead-out layer, the second electrode 270 penetrates the passivation layer 290 on the surface of the second lead-out layer so as to be connected to the second lead-out layer.

[0055] When the sensor structure includes the first lead-out layer 240, the first lead-out layer 240 may have a lead-out region, the lead-out region is used to connect the first electrode 260, and the stacked layer may expose the lead-out region. Specifically, the stacked layer may be isolated into a plurality of parts by an isolation groove 20A along the first direction, each part being a pixel 20B (refer to Figure 2 The portion in the dashed box) corresponds to a group of paired first electrodes 260 and second electrodes 270. The spacing between adjacent picture elements 20B is called a picture element spacing, which can be the spacing between the center points of two adjacent isolation trenches 20A.

[0056] The isolation trench 20A may expose the lead-out region of the first lead-out layer 240, the passivation layer 290 may cover the bottom and sidewalls of the isolation trench 20A, and the first electrode 260 may penetrate the passivation layer 290 at the bottom of the isolation trench 20A to be connected to the first lead-out layer 240. The thickness of the first lead-out layer 240 at the bottom of the isolation trench 20A may be equal to the thickness of the first lead-out layer 240 under the stacked layer, or may be less than the thickness of the first lead-out layer 240 under the stacked layer. When the thickness is less than the thickness of the first lead-out layer 240 under the stacked layer, it is beneficial to improve the reliability of the device.

[0057] The sensor structure may further include a first electrode 260 and a second electrode 270. The sensor structure may further include a readout circuit (ROIC) wafer 300 on the first electrode 260 and the second electrode 270, wherein the readout circuit wafer 300 includes a readout circuit, and the readout circuit is connected to the first electrode 260 and the second electrode 270, respectively. In actual operation, the readout circuit may be connected to the first electrode 260 through a first connection structure 310, and connected to the second electrode 270 through a second connection structure 320. In this way, the photogenerated carriers generated in the sensing layer may be transmitted to the first electrode 260 and the second electrode 270 through the first doping layer 230 and the doping structure 211, respectively, so that the readout circuit obtains the current information of the first electrode 260 and the second electrode 270, thereby obtaining the light detection result.

[0058] The sensor structure of this structure is called a planar type vertical PIN structure. The doping structure 211 only exists in the lead-out region of the intrinsic lead-out layer 210. Compared with the mesa type vertical PIN structure in which the intrinsic lead-out layer 210 is doped (although the surface treatment and passivation process reduce the sidewall leakage current to a certain extent, it is still very challenging to suppress the sidewall leakage current of the small pixel pitch pixel in the mesa structure, resulting in prominent leakage current and electrical crosstalk between adjacent pixels when the pixel pitch is further miniaturized, resulting in increased dark current. Therefore, the mesa structure has a large pixel size, a large pixel pitch, a low fill factor, and it is difficult to further improve the resolution), the isolation groove 20A is not doped, that is, the doping structure 211 will not be exposed from the isolation trench 20A, the entire junction interface is buried, and there is little leakage current on the side wall of the isolation trench 20A, which eliminates the electrical crosstalk between adjacent pixels as much as possible, and completely avoids the problems of surface leakage current and sidewall leakage current, thereby reducing the pixel size, miniaturizing the pixel pitch, increasing the fill factor, improving the resolution, suppressing the dark current and avoiding the electrical crosstalk between pixels, which is beneficial to the improvement of the performance of the focal plane array, and is more suitable for manufacturing InGaAs / InP short-wave infrared sensors with small pixel pitch and low dark current, meeting the application scenario requirements of focal plane arrays with higher resolution, larger array specifications, smaller pixel pitch, smaller pixel size, higher fill factor and lower cost.

[0059] Compared with conventional silicon heteroepitaxial InGaAs / InP wafer materials, the average defect density in the planar vertical PIN-type InGaAs / InP short-wave infrared wafer structure on multiple oxides (including ferroelectric oxides) is greatly reduced, which is beneficial to suppress the dark current caused by defects (the reasons for the reduction in dark current: the combined effect of multi-layer stacked insulators, planar structure and reduced average defect density). It is an effective solution to suppress the dark current of InGaAs / InP short-wave infrared sensors with small pixel pitch and large size (≥8 inches) on multiple oxide layers and electrical crosstalk between adjacent pixels. It is beneficial to achieve higher resolution high-performance InGaAs / InP short-wave infrared sensors, lays the wafer material foundation for the large-scale mass production of high-performance InGaAs / InP short-wave infrared sensors, and is considered to be one of the important technical approaches to promote the large-scale mass production of InGaAs / InP short-wave infrared sensors.

[0060] The realization of this technology can greatly promote the popularization and application of InGaAs / InP short-wave infrared sensors in the civilian field, and has very important research significance and application value. The planar vertical PIN type InGaAs / InP short-wave infrared imaging technology on multiple oxides (including ferroelectric oxides) can not only replace the existing military market of InGaAs short-wave infrared imaging technology, but also create a new market for InGaAs short-wave infrared imaging technology in the civilian field, which has great research significance and economic benefits for promoting the development of the national economy.

[0061] The present application provides a sensor structure, which may include a sensor structure, including an acceptor substrate, a dielectric layer on the acceptor substrate, and a stacked layer on the dielectric layer, wherein the stacked layer includes a first doping layer, an intrinsic absorption layer, and an intrinsic extraction layer stacked in sequence along a first direction perpendicular to the surface of the acceptor substrate, wherein the first doping layer has a first doping type, and an extraction region of the intrinsic extraction layer is doped with a second doping type as a doping structure, and the first doping layer, the intrinsic absorption layer, and the intrinsic extraction layer include Group III and V elements. A first extraction layer may be provided on a side of the stacked layer facing the acceptor substrate, and a second extraction layer may be provided on a side of the stacked layer facing away from the acceptor substrate, wherein the first extraction layer is used to connect a first electrode, and the second extraction layer is used to connect a second electrode, wherein the first extraction layer and the second extraction layer include Group III and V elements, wherein the first extraction layer has a first doping type, and the doping concentration of the first extraction layer is greater than the doping concentration of the first doping layer, and the second extraction layer has a second doping type, and the doping concentration of the second extraction layer is greater than the doping concentration of the doping structure.

[0062] In this way, the stacked layer is not directly formed on the acceptor substrate, and the acceptor substrate can be a non-indium phosphide substrate, so its size is not limited, and a large-size structure can be realized at low cost. In addition, the first electrode is connected through a first lead-out layer with a higher doping concentration, and the second electrode is connected through a second lead-out layer with a higher doping concentration, that is, by setting an additional lead-out layer outside the stacked layer, a good contact with the electrode is achieved, which improves the contact quality, reduces the contact resistance, and improves the detection performance of the sensor compared to directly connecting the electrode to the first doping layer or doping structure with a lower doping concentration. In summary, this scheme can form a high-quality short-wave infrared sensor on a large-size substrate, which is conducive to the large-scale commercial use of the sensor.

[0063] See also Figure 3 , this figure is a schematic diagram of another sensor structure provided in an embodiment of the present application, the sensor structure includes: a host substrate 100, a dielectric layer 250 / 280 on the host substrate 100, and a stacked layer 210 / 220 / 230 on the dielectric layer.

[0064] In the embodiment of the present application, the acceptor substrate 100 is used to provide support for the film layer thereon, and can be a conductive substrate or an insulating substrate, for example, a silicon substrate, a sapphire substrate or a glass substrate. The size of the acceptor substrate 100 is usually large, so a sensor on a large-size substrate can be formed, which is conducive to the large-scale commercial use of the sensor structure. The size (diameter or side length) of the acceptor substrate 100 can be, for example, ≥8 inches.

[0065] The stacked layers include a first doping layer 230, an intrinsic absorption layer 220, and a second doping layer 210 stacked in sequence along a first direction (i.e., longitudinal direction) perpendicular to the surface of the acceptor substrate. The first doping layer 230 has a first doping type, the second doping layer 210 has a second doping type, the first doping layer 230, the intrinsic absorption layer 220, and the second doping layer 210 include Group III and V elements, and the second doping layer 210 is obtained by doping the intrinsic extraction layer. The first doping type and the second doping type are opposite, the first doping type can be one of P-type doping and N-type doping, and the second doping type can be the other of P-type doping and N-type doping, for example, the first doping type can be P-type doping, and the second doping type can be N-type doping. In this way, the stacked layers constitute a vertical PIN structure (Vertical PIN Structure), and the first doping layer 230 and the second doping layer 210 can be used as an electron transport layer or a hole transport layer for charge response.

[0066] The material of the intrinsic absorption layer 220 may include indium gallium arsenide. The band gap of the intrinsic region of InGaAs can be adjusted by changing the content of In and Ga, which is very suitable for imaging applications in the 0.9-3μm short-wave infrared band. For example, the content of In and Ga is 53% and 47% respectively, and its spectral response range is 0.9-1.7μm. The doping concentration of the intrinsic absorption layer 220 is not higher than 2×10^16cm- 3 The thickness of the intrinsic absorption layer 220 is in the range of 500-3000 nm.

[0067] The intrinsic absorption layer 220 may include only InGaAs, or may include a quantum well structure composed of multiple sub-absorption layers, wherein the quantum well structure includes at least one of the following quantum wells: InGaAs / InP quantum well, InGaAs / InAlAs quantum well, InGaAs / AlGaAs quantum well, InGaAs / InAlGaAs quantum well, InGaAs / InGaAsP quantum well, GaAsP / InGaAs quantum well, and GaAsSb / InGaAs quantum well. In this way, the absorption efficiency of the intrinsic absorption layer 220 can be improved, and the photosensitivity of the sensor can be improved.

[0068] The material of the first doping layer 230 and the second doping layer 210 may be indium phosphide. In the first doping layer 230 and the second doping layer 210, the doping element of the P-type doping may include Zn, etc., and the doping element of the N-type doping may include Si, etc. Generally speaking, the first doping layer 230 and the second doping layer 210 can realize the extraction of charges, which can directly connect the first electrode and the second electrode. When the doping type of the first doping layer 230 or the second doping layer 210 is P-type doping, the doping concentration is not less than 1×10^18cm- 3 When the doping type of the first doping layer 230 or the second doping layer 210 is N-type doping, the doping concentration is not less than 2×10^18cm- 3 The thickness of the first doping layer 230 may be in the range of 100-500 nm, and the thickness of the second doping layer 210 may be in the range of 100-500 nm.

[0069] However, the inventors have found through research that at least one of the first doping layer 230 and the second doping layer 210 has a problem of low effective doping concentration, for example, the effective P-type doping concentration of InP is relatively low, and the P-type doping concentration of InP cannot be further increased. This results in a large contact resistance between the doping layer and the corresponding electrode, which is not conducive to improving the sensor performance.

[0070] Therefore, a first lead-out layer 240 may be provided on the side of the stacked layer facing the acceptor substrate 100, that is, the first lead-out layer 240 may be provided between the dielectric layer and the stacked layer, and the first lead-out layer 240 is used to connect the first electrode, and has a first doping type, including Group III and V elements, and the doping concentration of the first lead-out layer 240 is greater than the doping concentration of the first doping layer 230. Thus, by connecting the first electrode through the added first lead-out layer 240, a good ohmic contact is formed, with higher contact quality and lower contact resistance, compared with directly connecting the first electrode through the first doping layer 230.

[0071] Similarly, a second lead-out layer (not shown) may be provided on the side of the stacked layer away from the acceptor substrate 100, that is, a second lead-out layer is provided on the stacked layer, and the second lead-out layer is used to connect the second electrode, has a second doping type, includes Group III and V elements, and the doping concentration of the second lead-out layer is greater than the doping concentration of the second doping layer 210. Thus, the second electrode is connected by the added second lead-out layer, and a good ohmic contact is formed, which has a higher contact quality and a lower contact resistance, compared with connecting the second electrode through the second doping layers 210.

[0072] In the embodiment of the present application, only one of the first lead-out layer 240 and the second lead-out layer may be provided, or both may be provided. In the following example, the first lead-out layer 240 is provided as an example for explanation. In actual operation, the first lead-out layer 240 may be provided when the doping concentration of the first doping layer 230 is low, and the second lead-out layer may be provided when the doping concentration of the second doping layer 210 is low, thereby improving the contact quality at the corresponding position.

[0073] The materials of the first lead-out layer 240 and the second lead-out layer may include indium gallium arsenide. When the doping type of the first lead-out layer 240 or the second lead-out layer is P-type doping, the doping concentration is not less than 5×10^18cm- 3 .

[0074] The dielectric layer is used to isolate the acceptor substrate 100 and the stacked layer. The dielectric layer may include an insulating material, such as a ferroelectric oxide, or other insulating materials, such as silicon oxide, aluminum oxide, etc. As a possible implementation, the dielectric layer includes at least one of a ferroelectric oxide (Ferroelectric Oxide) layer 250 and an aluminum oxide (Al2O3) layer 280. The ferroelectric oxide layer 250 has a negative capacitance effect, and its capacitance is negative in the sensor structure working device, which effectively compensates for the larger positive capacitance in the sensor structure, thereby reducing the capacitance value in the entire germanium sensor, and can simultaneously achieve high responsiveness and high operating speed; the ferroelectric oxide layer 250 is also an effective insulating layer, which can effectively improve the defect state existing at the interface between germanium and other film layers (such as the acceptor substrate or buried oxide layer). In other words, the ferroelectric oxide has the functions of both electrical insulation and capacitance compensation.

[0075] The aluminum oxide layer 280 can be used as a bonding layer to bond the aluminum oxide layer 280 and the acceptor substrate together. The aluminum oxide layer 280 can be disposed on the side of the ferroelectric oxide away from the acceptor substrate 100. The thickness of the ferroelectric oxide layer 250 is in the range of 10-1000 nm, and the thickness of the aluminum oxide layer 280 is in the range of 10-1000 nm.

[0076] The material of the ferroelectric oxide layer 250 is ferroelectric oxide, and its types include but are not limited to Hf 0.5 Zr 0.5 Stacking structures such as O2, BaTiO3, PZT, LiNbO3, SrRuO3, SrTiO3, PbTiO3, (Pb, Sr)TiO3 / SrTiO3 (PST / STO) superlattice and (Ba, Sr)TiO3 / LaAlO3 superlattice.

[0077] refer to Figure 4 As shown, it is a schematic diagram of another sensor structure provided by an embodiment of the present application. An insulating layer may also be provided between the dielectric layer and the acceptor substrate 100. The insulating layer may enhance the interaction between the light and the sensing layer, which is beneficial to the improvement of the light responsiveness. The insulating layer may also be used as a bonding layer, bonded to the aforementioned aluminum oxide layer 280. The insulating layer may be a single layer or a stacked layer. When the insulating layer is a single layer, it may be a silicon oxide layer. When the insulating layer is a stacked layer, it may be a stack of a silicon oxide layer 110 and a silicon oxide (denoted as a TEOS layer) 120 formed using tetraethyl orthosilicate (TEOS), or a stack of polycrystalline silicon and silicon oxide, or a stack of silicon oxide / silicon nitride / silicon oxide, etc. The insulating layer may constitute a distributed Bragg reflector (DBR). The thickness of the insulating layer may be 100-1000nm.

[0078] That is to say, from the acceptor substrate 100 upwards, the sensor structure may include vertically stacked insulator layers such as the silicon oxide layer 110, the TEOS layer 120, the aluminum oxide layer 280 and the ferroelectric oxide layer 250 in sequence. The illumination direction of the sensor structure is usually longitudinal, so that the interfaces of the aforementioned insulator layers and the stacked layers can reflect light, which is equivalent to increasing the vertical resonant cavity effect, improving the light absorption efficiency, and further improving the key performance indicators of the sensor such as dark current, quantum efficiency and responsiveness.

[0079] The sensor structure may further include a passivation layer 290 on the stacked layer, and the passivation layer 290 is used to protect the stacked layer. The material of the passivation layer 290 is an insulating material, for example, it may be a ferroelectric oxide, or it may be other insulating materials, such as silicon oxide. When the material of the passivation layer 290 is a ferroelectric oxide, it can also compensate for the larger positive capacitance in the sensor structure, and also serve as an insulating layer to achieve effective insulation.

[0080] The first electrode 260 may penetrate the passivation layer 290 on the first doping layer 230, and the second electrode 270 may penetrate the passivation layer 290 on the second doping layer 210. When the sensor structure includes a first lead-out layer 240, the first electrode 260 penetrates the passivation layer 290 on the surface of the first lead-out layer 240 so as to be connected to the first lead-out layer 240. When the sensor structure includes a second lead-out layer, the second electrode 270 penetrates the passivation layer 290 on the surface of the second lead-out layer so as to be connected to the second lead-out layer.

[0081] When the sensor structure includes the first lead-out layer 240, the first lead-out layer 240 may have a lead-out region, the lead-out region is used to connect the first electrode 260, and the stacked layer may expose the lead-out region. Specifically, the stacked layer may be isolated into a plurality of parts by an isolation groove 20A along the first direction, and each part is a pixel 20B (refer to Figure 4 The portion in the dashed box) corresponds to a group of paired first electrodes 260 and second electrodes 270. The spacing between adjacent picture elements 20B is called a picture element spacing, which can be the spacing between the center points of two adjacent isolation trenches 20A.

[0082] The isolation trench 20A may expose the lead-out region of the first lead-out layer 240, the passivation layer 290 may cover the bottom and sidewalls of the isolation trench 20A, and the first electrode 260 may penetrate the passivation layer 290 at the bottom of the isolation trench 20A to be connected to the first lead-out layer 240. The thickness of the first lead-out layer 240 at the bottom of the isolation trench 20A may be equal to the thickness of the first lead-out layer 240 under the stacked layer, or may be less than the thickness of the first lead-out layer 240 under the stacked layer. When the thickness is less than the thickness of the first lead-out layer 240 under the stacked layer, it is beneficial to improve the reliability of the device.

[0083] The sensor structure may further include a first electrode 260 and a second electrode 270. The sensor structure may further include a readout circuit (ROIC) wafer 300 on the first electrode 260 and the second electrode 270, wherein the readout circuit wafer 300 includes a readout circuit, and the readout circuit is connected to the first electrode 260 and the second electrode 270, respectively. In actual operation, the readout circuit may be connected to the first electrode 260 through a first connection structure 310, and connected to the second electrode 270 through a second connection structure 320. In this way, the photogenerated carriers generated in the sensing layer may be transmitted to the first electrode 260 and the second electrode 270 through the first doping layer 230 and the second doping layer 210, respectively, so that the readout circuit obtains the current information of the first electrode 260 and the second electrode 270, thereby obtaining the light detection result.

[0084] Compared with conventional silicon heteroepitaxial InGaAs / InP wafer materials, the average defect density in the vertical PIN-type InGaAs / InP short-wave infrared wafer structure on ferroelectric oxide is greatly reduced, which is conducive to suppressing the dark current caused by defects (the reason for the reduction of dark current: the combined effect of multi-layer stacked insulators and the reduction of average defect density), laying the foundation for the large-scale mass production of high-performance InGaAs / InP short-wave infrared sensors. The realization of this technology can greatly promote the promotion and application of InGaAs / InP short-wave infrared sensors in the civilian field, and has very important research significance and application value. The vertical PIN-type InGaAs / InP short-wave infrared imaging technology on ferroelectric oxide can not only replace the existing military market of InGaAs short-wave infrared imaging technology, but also create a new market for InGaAs short-wave infrared imaging technology in the civilian field, which has great research significance and economic benefits for promoting the development of the national economy.

[0085] The present application provides a sensor structure, which may include a sensor structure, including an acceptor substrate, a dielectric layer on the acceptor substrate, and a stacked layer on the dielectric layer, wherein the stacked layer includes a first doping layer, an intrinsic absorption layer, and a second doping layer stacked in sequence along a first direction perpendicular to the surface of the acceptor substrate, wherein the first doping layer has a first doping type, and the second doping layer has a second doping type, and the first doping layer, the intrinsic absorption layer, and the second doping layer include Group III and V elements. A first lead-out layer may be provided on a side of the stacked layer facing the acceptor substrate, and a second lead-out layer may be provided on a side of the stacked layer facing away from the acceptor substrate, wherein the first lead-out layer is used to connect the first electrode, and the second lead-out layer is used to connect the second electrode, wherein the first lead-out layer and the second lead-out layer include Group III and V elements, wherein the first lead-out layer has a first doping type, and the doping concentration of the first lead-out layer is greater than the doping concentration of the first doping layer, and the second lead-out layer has a second doping type, and the doping concentration of the second lead-out layer is greater than the doping concentration of the second doping layer.

[0086] In this way, the stacked layer is not directly formed on the acceptor substrate, and the acceptor substrate can be a non-indium phosphide substrate, so its size is not limited, and a large-size structure can be realized at low cost. In addition, the first electrode is connected through a first lead-out layer with a higher doping concentration, and the second electrode is connected through a second lead-out layer with a higher doping concentration, that is, by setting an additional lead-out layer outside the stacked layer, good contact with the electrode is achieved, which improves the contact quality, reduces the contact resistance, and improves the detection performance of the sensor compared to directly connecting the electrode to the doping layer with a lower doping concentration. In summary, this scheme can form a high-quality short-wave infrared sensor on a large-size substrate, which is conducive to the large-scale commercial use of the sensor.

[0087] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A sensor structure, characterized in that: include: acceptor substrate; a dielectric layer on the acceptor substrate; The stacked layers on the dielectric layer include a first doped layer, an intrinsic absorption layer and an intrinsic extraction layer sequentially stacked in a first direction perpendicular to the surface of the acceptor substrate, the first doped layer has a first doping type, the extraction region of the intrinsic extraction layer is doped with a second doping type as a doped structure, or the intrinsic extraction layer is doped with the second doping type as a second doped layer, and the first doped layer, the intrinsic absorption layer and the intrinsic extraction layer include Group III and V elements; The stacked layer faces a first lead-out layer on one side of the acceptor substrate, and / or the doping structure or the second doping layer faces a second lead-out layer on one side of the acceptor substrate, the first lead-out layer is used to connect a first electrode, and the second lead-out layer is used to connect a second electrode; the first lead-out layer and the second lead-out layer include Group III and V elements; The first lead-out layer has a first doping type, and the doping concentration of the first lead-out layer is greater than the doping concentration of the first doping layer; the second lead-out layer has a second doping type, and the doping concentration of the second lead-out layer is greater than the doping concentration of the doping structure or the second doping layer.

2. The sensor structure according to claim 1, characterized in that: The material of the first lead-out layer or the second lead-out layer includes indium gallium arsenide, the material of the first doping layer and the intrinsic lead-out layer includes indium phosphide, and the material of the intrinsic absorption layer includes indium gallium arsenide.

3. The sensor structure according to claim 2, characterized in that: The intrinsic absorption layer includes a quantum well structure composed of multiple sub-absorption layers, and the quantum well structure includes at least one of the following quantum wells: InGaAs / InP quantum well, InGaAs / InAlAs quantum well, InGaAs / AlGaAs quantum well, InGaAs / InAlGaAs quantum well, InGaAs / InGaAsP quantum well, GaAsP / InGaAs quantum well and GaAsSb / InGaAs quantum well.

4. The sensor structure according to claim 2, characterized in that: The first doping type is P type, and the second doping type is N type.

5. The sensor structure according to any one of claims 1 to 4, characterized in that: The dielectric layer includes a ferroelectric oxide layer.

6. The sensor structure according to claim 5, characterized in that: The dielectric layer includes an aluminum oxide layer and a ferroelectric oxide layer stacked in sequence.

7. The sensor structure according to any one of claims 1 to 4, characterized in that: An insulating layer is also provided between the acceptor substrate and the dielectric layer. The insulating layer includes a stack of a silicon oxide layer and a TEOS layer, or a stack of polysilicon and silicon oxide, or a stack of silicon oxide / silicon nitride / silicon oxide.

8. The sensor structure according to any one of claims 1 to 4, characterized in that: Also includes: a passivation layer covering the stacked layer, the first electrode penetrating the passivation layer on the first doped layer, and the second electrode penetrating the doped structure or the passivation layer on the second doped layer; The material of the passivation layer is ferroelectric oxide.

9. The sensor structure according to any one of claims 1 to 4, characterized in that: The stacked layer is isolated into a plurality of parts by isolation grooves along the first direction, and each part serves as a picture element corresponding to a group of paired first electrodes and second electrodes.

10. The sensor structure according to any one of claims 1 to 4, characterized in that: Also includes: the first electrode and the second electrode; The readout circuit wafer on the first electrode and the second electrode has a readout circuit, and the readout circuit is connected to the first electrode and the second electrode respectively.

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