Operational amplifier, modulator and temperature sensor

Abstract

The utility model relates to the technical field of integrated circuits, and particularly discloses an operational amplifier which is used for solving the mismatch problem. According to the specific implementation scheme, the operational amplifier comprises a first amplification circuit, a second amplification circuit, a first load circuit, a second load circuit and an offset voltage calibration circuit, wherein the offset voltage calibration circuit is configured to alternately connect the first load circuit to the first amplification circuit and the second amplification circuit, and alternately connect the second load circuit to the first amplification circuit and the second amplification circuit; the first load circuit is used for adjusting the differential signal output by the first amplification circuit or the second amplification circuit, and the second load circuit is used for adjusting the differential signal output by the first amplification circuit or the second amplification circuit, so that the error of the output signal caused by the offset voltage of the operational amplifier can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an operational amplifier, a modulator, and a temperature sensor. Background Art

[0002] An operational amplifier usually has two amplification circuits, namely a first amplification circuit and a second amplification circuit. In an ideal operational amplifier, the two amplification circuits are completely symmetrical, and the parameters of the circuit components in the two amplification circuits are completely consistent. However, in the manufacturing process of chips, especially in the manufacturing process of operational amplifiers, due to the limitations of the manufacturing process, two circuit components of the same type inevitably have differences, resulting in mismatch, and then the operational amplifier will generate an offset voltage, which will cause errors in the output signal of the operational amplifier. Utility Model Content

[0003] The present disclosure provides an operational amplifier, a modulator and a temperature sensor, which can reduce the error of the output signal of the operational amplifier caused by the offset voltage.

[0004] According to a first aspect of the present disclosure, an operational amplifier is provided, comprising: a first amplification circuit, a second amplification circuit, a first load circuit, a second load circuit and an offset voltage calibration circuit; wherein,

[0005] The offset voltage calibration circuit is configured to connect the first load circuit to the first amplification circuit and the second amplification circuit alternately, and to connect the second load circuit to the first amplification circuit and the second amplification circuit alternately.

[0006] In some examples, the offset voltage calibration circuit is configured to connect the first load circuit to the first amplification circuit and the second amplification circuit alternately, and connect the second load circuit to the first amplification circuit and the second amplification circuit alternately, including:

[0007] When the first load circuit is connected to the first amplifier circuit, the second load circuit is connected to the second amplifier circuit;

[0008] When the first load circuit is connected to the second amplifying circuit, the second load circuit is connected to the first amplifying circuit.

[0009] In some examples, the offset voltage calibration circuit is configured to connect the first load circuit to the first amplification circuit and the second amplification circuit alternately, and connect the second load circuit to the first amplification circuit and the second amplification circuit alternately, including:

[0010] When receiving a first control signal, the offset voltage calibration circuit connects the first load circuit to the first amplifier circuit and connects the second load circuit to the second amplifier circuit; when receiving a second control signal, the offset voltage calibration circuit connects the first load circuit to the second amplifier circuit and connects the second load circuit to the first amplifier circuit.

[0011] In some examples, the offset voltage calibration circuit includes a first switch subcircuit and a second switch subcircuit; wherein,

[0012] The first switch subcircuit includes a first switch and a second switch, wherein a first end of the first switch is electrically connected to the first load circuit, and a second end of the first switch is electrically connected to the first amplifier circuit; a first end of the second switch is electrically connected to the first load circuit, and a second end of the second switch is electrically connected to the second amplifier circuit;

[0013] The second switch subcircuit comprises a third switch and a fourth switch, wherein a first end of the third switch is electrically connected to the second load circuit, and a second end thereof is electrically connected to the first amplifier circuit; a first end of the fourth switch is electrically connected to the second load circuit, and a second end thereof is electrically connected to the second amplifier circuit;

[0014] When a first control signal is received, the first switch is connected to the fourth switch; when a second control signal is received, the second switch is connected to the third switch.

[0015] In some examples, the first switch includes a first switch transistor and a second switch transistor; a first electrode of the first switch transistor is electrically connected to a first electrode of the second switch transistor, and is electrically connected to the first load circuit; a second electrode of the first switch transistor is electrically connected to a second electrode of the second switch transistor, and is electrically connected to the first amplifier circuit; a control electrode of the first switch transistor is connected to a first clock signal terminal, and a control electrode of the second switch transistor is connected to a second clock signal terminal;

[0016] The second switch includes a third switch transistor and a fourth switch transistor; a first electrode of the third switch transistor is electrically connected to a first electrode of the fourth switch transistor, and is electrically connected to the first load circuit; a second electrode of the third switch transistor is electrically connected to a second electrode of the fourth switch transistor, and is electrically connected to the second amplifier circuit; a control electrode of the third switch transistor is connected to a second clock signal terminal, and a control electrode of the fourth switch transistor is connected to a first clock signal terminal;

[0017] The third switch includes a fifth switch transistor and a sixth switch transistor; the first electrode of the fifth switch transistor is electrically connected to the first electrode of the sixth switch transistor, and is electrically connected to the second load circuit; the second electrode of the fifth switch transistor is electrically connected to the second electrode of the sixth switch transistor, and is electrically connected to the first amplifier circuit; the control electrode of the fifth switch transistor is connected to the second clock signal terminal, and the control electrode of the sixth switch transistor is connected to the first clock signal terminal;

[0018] The fourth switch includes a seventh switch transistor and an eighth switch transistor; the first electrode of the seventh switch transistor is electrically connected to the first electrode of the eighth switch transistor, and is electrically connected to the second load circuit; the second electrode of the seventh switch transistor is electrically connected to the second electrode of the eighth switch transistor, and is electrically connected to the second amplifier circuit; the control electrode of the seventh switch transistor is connected to the first clock signal terminal, and the control electrode of the eighth switch transistor is connected to the second clock signal terminal;

[0019] Among them, the first clock signal terminal is used to provide a first clock signal, and the second clock signal terminal is used to provide a second clock signal; the first control signal is represented by the first clock signal being a first level and the second clock signal being a second level; the second control signal is represented by the first clock signal being a second level and the second clock signal being a first level.

[0020] In some examples, the first switch transistor, the third switch transistor, the fifth switch transistor, and the seventh switch transistor are P-type field effect transistors;

[0021] The second switch transistor, the fourth switch transistor, the sixth switch transistor and the eighth switch transistor are N-type field effect transistors.

[0022] In some examples, the first load circuit includes a first load transistor and a second load transistor; a first electrode of the first load transistor is electrically connected to a second electrode of the second load transistor, and the second electrode is electrically connected to a first input terminal of the offset voltage calibration circuit;

[0023] The second load circuit includes a third load transistor and a fourth load transistor; the first electrode of the third load transistor is electrically connected to the second electrode of the fourth load transistor, and the second electrode is electrically connected to the second input terminal of the offset voltage calibration circuit;

[0024] The first electrode of the second load transistor and the first electrode of the fourth load transistor are connected to a first power supply voltage terminal; the control electrode of the first load transistor is electrically connected to the control electrode of the third load transistor, and they are jointly electrically connected to a first bias voltage terminal; the control electrode of the second load transistor is electrically connected to the control electrode of the fourth load transistor, and they are jointly electrically connected to a common-mode voltage output terminal.

[0025] In some examples, the first amplifier circuit includes a first amplifier transistor and a first bias transistor; a first electrode of the first amplifier transistor is electrically connected to a first output terminal of the offset voltage calibration circuit, and a second electrode is electrically connected to a first electrode of the first bias transistor;

[0026] The second amplifier circuit includes a second amplifier transistor and a second bias transistor; a first electrode of the second amplifier transistor is electrically connected to the second output terminal of the offset voltage calibration circuit, and a second electrode is electrically connected to the first electrode of the second bias transistor;

[0027] The control electrode of the first bias transistor and the control electrode of the second bias transistor are electrically connected to a second bias voltage terminal; the second electrode of the first bias transistor and the second electrode of the second bias transistor are connected to a second power supply voltage terminal.

[0028] In some examples, the first bias transistor is multiplexed as the second bias transistor.

[0029] In some examples, the first amplifier circuit further includes a third amplifier transistor and a third bias transistor; the control electrode of the third amplifier transistor is electrically connected to the first electrode of the first amplifier transistor, the first electrode is connected to the first power supply voltage terminal, and the second electrode is electrically connected to the first electrode of the third bias transistor; the control electrode of the third bias transistor is electrically connected to the second bias voltage terminal, and the second electrode is connected to the second power supply voltage terminal;

[0030] The second amplifier circuit also includes a fourth amplifier transistor and a fourth bias transistor; the control electrode of the fourth amplifier transistor is electrically connected to the first electrode of the second amplifier transistor, the first electrode is connected to the first power supply voltage terminal, and the second electrode is electrically connected to the first electrode of the fourth bias transistor; the control electrode of the fourth bias transistor is electrically connected to the second bias voltage terminal, and the second electrode is connected to the second power supply voltage terminal.

[0031] In some examples, the further comprising: a first capacitor, a second capacitor, a first resistor, and a second resistor;

[0032] The first end of the first capacitor is electrically connected to the output end of the first amplifier circuit, the second end of the first capacitor is connected to the first end of the first resistor, and the second end of the first resistor is electrically connected to the input end of the first amplifier circuit;

[0033] The first end of the second capacitor is electrically connected to the output end of the second amplifier circuit, the second end is connected to the first end of the second resistor, and the second end of the second resistor is electrically connected to the input end of the second amplifier circuit.

[0034] In some examples, it also includes: a common-mode feedback circuit; a first input terminal of the common-mode feedback circuit is electrically connected to the output terminal of the first amplifier circuit, a second input terminal is electrically connected to the output terminal of the second amplifier circuit, and a common-mode voltage output terminal is electrically connected to the first load circuit and the second load circuit.

[0035] In some examples, the first load circuit includes a first load transistor and a second load transistor, a first electrode of the first load transistor being electrically connected to a second electrode of the second load transistor;

[0036] The second load circuit comprises a third load transistor and a fourth load transistor, wherein a first electrode of the third load transistor is electrically connected to a second electrode of the fourth load transistor;

[0037] The first electrode of the second load transistor and the first electrode of the fourth load transistor are connected to the first power supply voltage terminal; the control electrode of the second load transistor is electrically connected to the control electrode of the fourth load transistor, and are electrically connected to the common mode voltage output terminal.

[0038] According to a second aspect of the present disclosure, a modulator is provided, comprising the above operational amplifier.

[0039] In some examples, further comprising: a first switched capacitor circuit and a second switched capacitor circuit;

[0040] The first switched capacitor circuit comprises a first level switch, a first end of the first level switch is electrically connected to the input end of the first amplifier circuit, and a control end is electrically connected to the first clock signal end;

[0041] The second switched capacitor circuit comprises a second level switch, a first end of the second level switch is electrically connected to the input end of the second amplifier circuit, and a control end is electrically connected to the second clock signal end;

[0042] The offset voltage calibration circuit is electrically connected to the first clock signal terminal and the second clock signal terminal; wherein,

[0043] The first clock signal terminal is used to provide a first clock signal, and the second clock signal terminal is used to provide a second clock signal; the first control signal is represented by the first clock signal being a first level and the second clock signal being a second level; the second control signal is represented by the first clock signal being a second level and the second clock signal being a first level, and the first level is different from the second level.

[0044] According to a third aspect of the present disclosure, a temperature sensor is provided, which includes the above-mentioned operational amplifier and / or the above-mentioned modulator.

[0045] According to the technology disclosed in the present invention, by setting an offset voltage calibration circuit, under the control of a first control signal and a second control signal, the first and second load circuits are alternately connected to the first and second amplifier circuits, thereby being able to eliminate or reduce the offset voltage generated by the mismatch difference between the first amplifier circuit and the second amplifier circuit, and further being able to eliminate or reduce the error of the differential signal output by the first amplifier circuit and the second amplifier circuit.

[0046] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0048] Figure 1 A circuit diagram of an operational amplifier and a current-mode offset voltage digital-to-analog converter in the related art;

[0049] Figure 2A A circuit connection diagram of an operational amplifier provided for one embodiment of the present disclosure;

[0050] Figure 2B A schematic diagram of a circuit structure of an operational amplifier provided in one embodiment of the present disclosure;

[0051] Figure 3 A circuit diagram of an offset voltage calibration circuit provided for one embodiment of the present disclosure;

[0052] Figure 4 A circuit diagram of an operational amplifier provided for another embodiment of the present disclosure;

[0053] Figure 5 A circuit diagram of a modulator provided for one embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0055] It should be understood that the terms "first", "second", "third", "fourth", etc. in the claims, specifications and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specifications and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections.

[0056] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0057] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0058] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0059] It should be noted that the transistor used in the present disclosure may be a field effect transistor or a thin film transistor or other switching devices with the same characteristics. The thin film transistor may include an oxide semiconductor thin film transistor, an amorphous silicon thin film transistor or a polycrystalline silicon thin film transistor, etc. The field effect transistor may include a junction field effect transistor (JFET) or a metal-oxide semiconductor field effect transistor (MOSFET), etc. The following is an example of a transistor being a MOSFET (MOS tube for short). For each transistor, it includes a first electrode, a second electrode and a control electrode, wherein the control electrode serves as the gate of the transistor, one of the first electrode and the second electrode serves as the source of the transistor, and the other serves as the drain of the transistor; and the source and drain of the transistor may be symmetrical in structure, so the source and drain thereof may be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate serving as the control electrode, the first electrode is directly described as the source (or drain) and the second electrode is the drain (or source). However, the source and drain of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed and are not limited to this.

[0060] In the related art, see Figure 1 , operational amplifier 001 is a fully differential operational amplifier, the first input terminal Vi1 of operational amplifier 001 receives a first differential signal, the second input terminal Vi2 receives a second differential signal, the first output terminal Vo1 outputs the amplified first differential signal, and the second output terminal Vo2 outputs the amplified second differential signal. Operational amplifier 001 is connected to a first power supply voltage terminal to receive a first power supply voltage VDDA, and is connected to a second power supply voltage terminal to receive a second power supply voltage Vss. In the manufacturing process of the operational amplifier, due to the limitations of the manufacturing process, there are inevitably differences between two circuit devices of the same type (such as MOS tubes) in the two-way amplification circuit of the operational amplifier 001, resulting in mismatch, and then the operational amplifier 001 will generate an offset voltage. Usually a calibration circuit ( Figure 1The calibration circuit includes a current-mode offset voltage digital-to-analog converter (Current Offset DAC) 002 connected to the operational amplifier 001. During the calibration process, it is necessary to first run the calibration program to obtain the corresponding calibration code, and write the calibration code into the register. Then, during the operation of the operational amplifier 001, the calibration code is input into the current-mode offset voltage digital-to-analog converter 002. The current-mode offset voltage digital-to-analog converter 002 outputs a compensation current to the operational amplifier 001 according to the calibration code to calibrate the output signal error of the operational amplifier 001 caused by the offset voltage. However, the above calibration process requires the addition of a more complex digital circuit, and requires calculation and calibration, which increases the circuit burden.

[0061] First, in order to solve the above problems, see Figure 2A The present disclosure provides an operational amplifier, which includes a first amplifying circuit 01, a second amplifying circuit 02, a first load circuit 03, a second load circuit 04 and an offset voltage calibration circuit 05.

[0062] The offset voltage calibration circuit 05 is configured to alternately connect the first load circuit 03 to the first amplification circuit 01 and the second amplification circuit 02 , and alternately connect the second load circuit 04 to the first amplification circuit 01 and the second amplification circuit 02 .

[0063] Among them, the offset voltage calibration circuit 05 is configured to alternately connect the first load circuit 03 to the first amplifier circuit 01 and the second amplifier circuit 02, and alternately connect the second load circuit 04 to the first amplifier circuit 01 and the second amplifier circuit 02, including: when the first load circuit 03 is connected to the first amplifier circuit 01, the second load circuit 04 is connected to the second amplifier circuit 02; when the first load circuit 03 is connected to the second amplifier circuit 02, the second load circuit 04 is connected to the first amplifier circuit 01, that is, at the same time, one of the first load circuit 03 and the second load circuit 04 is always connected to the first amplifier circuit 01, and the other is connected to the second amplifier circuit 02.

[0064] Further, the offset voltage calibration circuit 05 is configured to connect the first load circuit 03 alternately to the first amplifier circuit 01 and the second amplifier circuit 02, and to connect the second load circuit 04 alternately to the first amplifier circuit 01 and the second amplifier circuit 02, including: when receiving the first control signal, the offset voltage calibration circuit 05 connects the first load circuit 03 to the first amplifier circuit 01, and connects the second load circuit 04 to the second amplifier circuit 02; when receiving the second control signal, the offset voltage calibration circuit 05 connects the first load circuit 03 to the second amplifier circuit 02, and connects the second load circuit 04 to the first amplifier circuit 01.

[0065] The first amplifier circuit 01 includes an input terminal Vip and an output terminal Vop, the first differential signal is inputted by the input terminal Vip, and is outputted by the output terminal Vop after being amplified; the second amplifier circuit 02 includes an input terminal Vim and an output terminal Vom, the second differential signal is inputted by the input terminal Vim, and is outputted by the output terminal Vom after being amplified. The first load circuit 03 is used to adjust the differential signal outputted by the first amplifier circuit 01 or the second amplifier circuit 02; the second load circuit 04 is used to adjust the differential signal outputted by the first amplifier circuit 01 or the second amplifier circuit 02.

[0066] In the actual operational amplifier circuit, due to the limitation of the manufacturing process, the first amplifier circuit 01 and the second amplifier circuit 02 cannot be completely symmetrical, and the same type of circuit devices (such as MOS tubes) in the first amplifier circuit 01 and the second amplifier circuit 02 will also have certain differences in electrical characteristics. Similarly, the first load circuit 03 and the second load circuit 04 cannot be completely symmetrical, and the same type of circuit devices (such as MOS tubes) in the first load circuit 03 and the second load circuit 04 will also have certain differences in electrical characteristics, which will lead to mismatch and the operational amplifier will have a certain offset voltage. The present disclosure adds an offset voltage calibration circuit 05 to the operational amplifier, and under the control of the first control signal and the second control signal, the first load circuit 03 and the second load circuit 04 are alternately connected to the first amplifier circuit 01 and the second amplifier circuit 02. In other words, during the continuous operation of the operational amplifier, the amplified first differential signal output by the output terminal Vop of the first amplifier circuit 01 is the first differential signal adjusted alternately through the first load circuit 03 and the second load circuit 04. Similarly, the amplified second differential signal output by the output terminal Vom of the second amplifier circuit 02 is the second differential signal adjusted alternately through the first load circuit 03 and the second load circuit 04. By alternately connecting the load circuits on both sides (i.e., the first load circuit 03 and the second load circuit 04) to the first amplifier circuit 01 and the second amplifier circuit 02, the technical effect of continuously exchanging the output paths of the differential signals (i.e., the first differential signal and the second differential signal) is achieved. In the related art, due to the differential The output path of the signal is fixed, for example, the first differential signal is fixedly output after adjustment via the first load circuit 03, and the second differential signal is fixedly output after adjustment via the second load circuit 04. Therefore, if there is a difference in electrical characteristics between the circuit components in the first load circuit 03 and the second load circuit 04, there is always a difference in the voltage amplitude between the first differential signal and the second differential signal, and the difference cannot be eliminated, thereby generating a mismatch and further generating an offset voltage. In this embodiment, since the output paths of the differential signals are continuously exchanged, the first differential signal and the second differential signal are output after adjustment via the first load circuit 03 and then output after adjustment via the second load circuit 04. Therefore, when the operational amplifier works continuously, even if there is a difference in electrical characteristics between the circuit components in the first load circuit 03 and the second load circuit 04, the difference will be eliminated, thereby being able to eliminate or reduce the offset voltage caused by the mismatch, and further being able to eliminate or reduce the error of the differential signal output by the first amplifier circuit 01 and the second amplifier circuit 02.

[0067] It should be noted that the operational amplifier provided by the present disclosure may be various types of operational amplifiers, such as an operational amplifier with differential input and single-ended output, a fully differential operational amplifier, etc. For the sake of ease of explanation, this article takes the operational amplifier as a fully differential operational amplifier as an example for explanation, but does not constitute a limitation to the present disclosure.

[0068] In some examples, the operational amplifier is electrically connected to the first clock terminal to receive the first clock signal clk1, and is electrically connected to the second clock terminal to receive the second clock signal clk2. The first clock signal clk1 and the second clock signal clk2 are used to control the first load circuit 03 and the second load circuit 04 to alternately connect to the first amplifier circuit 01 and the second amplifier circuit 02. The first control signal can be represented by the first clock signal clk1 being the first level and the second clock signal clk2 being the second level; the second control signal can be represented by the first clock signal clk1 being the second level and the second clock signal clk2 being the first level. It should be noted that the first level is different from the second level, for example, one of the first level and the second level is a high level and the other is a low level, which can be specifically set as needed. The following is an example of the first level being a high level and the second level being a low level. In other words, at the same time, the levels of the first clock signal clk1 and the second clock signal clk2 are always different (or opposite), that is, one is always a high level and the other is a low level. Furthermore, the clock periods (ie, oscillation periods) of the first clock signal clk1 and the second clock signal clk2 are the same.

[0069] In some examples, see Figure 2B , Figure 3 , the offset voltage calibration circuit 05 may include a first switch subcircuit 051 and a second switch subcircuit 052. The first switch subcircuit 051 includes a first switch S1 and a second switch S2, wherein a first end of the first switch S1 is electrically connected to the first load circuit 03, and a second end of the first switch S1 is electrically connected to the first amplifier circuit 01; a first end of the second switch S2 is electrically connected to the first load circuit 03, and a second end of the second switch S2 is electrically connected to the second amplifier circuit 02.

[0070] The second switch subcircuit 052 includes a third switch S3 and a fourth switch S4, wherein a first end of the third switch S3 is electrically connected to the second load circuit 04, and a second end of the third switch S3 is electrically connected to the first amplifier circuit 01; a first end of the fourth switch S4 is electrically connected to the second load circuit 04, and a second end of the fourth switch S4 is electrically connected to the second amplifier circuit 02.

[0071] In summary, continue to see Figure 2B, the offset voltage calibration circuit 05 includes a first input terminal In1, a second input terminal In2, a first output terminal Out1, and a second output terminal Out2. The first input terminal In1 is the first end of the first switch S1 and the first end of the second switch S2, and the first input terminal In1 is electrically connected to the first load circuit 03; the second input terminal In2 is the first end of the third switch S3 and the first end of the fourth switch S4, and the second input terminal In2 is electrically connected to the second load circuit 04; the first output terminal Out1 is the second end of the first switch S1 and the second end of the third switch S3, and the first output terminal Out1 is electrically connected to the first amplifier circuit 01; the second output terminal Out2 is the second end of the second switch S2 and the second end of the fourth switch S3, and the second output terminal Out2 is electrically connected to the second amplifier circuit 02.

[0072] Among them, the first switch S1 and the fourth switch S4 are configured to be connected in response to a first control signal (for example: the first clock signal clk1 is at a high level and the second clock signal clk2 is at a low level). In other words, if the offset voltage calibration circuit receives the first control signal, the first input terminal In1 and the first output terminal Out1 of the offset voltage calibration circuit 05 are connected to connect the first load circuit 03 to the first amplifier circuit 01, and the second input terminal In2 and the second output terminal Out2 are connected to connect the second load circuit 04 to the second amplifier circuit 02; the second switch S2 and the third switch S3 are configured to be connected in response to a second control signal (for example: the first clock signal clk1 is at a low level and the second clock signal clk2 is at a high level). In other words, if the offset voltage calibration circuit receives the second control signal, the first input terminal In1 and the second output terminal Out2 of the offset voltage calibration circuit 05 are connected to connect the first load circuit 03 to the second amplifier circuit 02, and the second input terminal In2 and the first output terminal Out1 are connected to connect the second load circuit 04 to the first amplifier circuit 01. In multiple consecutive clock cycles, the first control signal and the second control signal are output alternately, so that the first load circuit 03 and the second load circuit 04 are alternately connected to the first amplifier circuit 01 and the second amplifier circuit 02 to eliminate the error of the output signal caused by the offset voltage in the operational amplifier.

[0073] For some examples, see Figure 3 The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 can be various types of switches, for example, they can be level switches or transistor switch circuits, etc. In this example, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are transistor switch circuits as an example for explanation.

[0074] Specifically, the first switch S1 includes a first switch transistor T51 and a second switch transistor T52. A first electrode of the first switch transistor T51 is electrically connected to a first electrode of the second switch transistor T52, and both the first electrode of the first switch transistor T51 and the first electrode of the second switch transistor T52 are electrically connected to the first load circuit 03 through a first input terminal In1; a second electrode of the first switch transistor T51 is electrically connected to a second electrode of the second switch transistor T52, and both the second electrode of the first switch transistor T51 and the second electrode of the second switch transistor T52 are electrically connected to the first amplifier circuit 01 through a first output terminal Out1; a control electrode of the first switch transistor T51 is connected to a first clock signal terminal to receive a first clock signal clk1, and a control electrode of the second switch transistor T52 is connected to a second clock signal terminal to receive a second clock signal clk2.

[0075] The second switch S2 includes a third switch transistor T53 and a fourth switch transistor T54. A first electrode of the third switch transistor T53 is electrically connected to a first electrode of the fourth switch transistor T54, and both the first electrode of the third switch transistor T53 and the first electrode of the fourth switch transistor T54 are electrically connected to the first load circuit 03 through the first input terminal In1; a second electrode of the third switch transistor T53 is electrically connected to a second electrode of the fourth switch transistor T54, and both the second electrode of the third switch transistor T53 and the second electrode of the fourth switch transistor T54 are electrically connected to the second amplifier circuit 02 through the second output terminal Out2; a control electrode of the third switch transistor T53 is connected to the second clock signal terminal to receive the second clock signal clk2, and a control electrode of the fourth switch transistor T54 is connected to the first clock signal terminal to receive the first clock signal clk1.

[0076] The third switch S3 includes a fifth switch transistor T55 and a sixth switch transistor T56. A first electrode of the fifth switch transistor T55 is electrically connected to a first electrode of the sixth switch transistor T56, and both the first electrode of the fifth switch transistor T55 and the first electrode of the sixth switch transistor T56 are electrically connected to the second load circuit 04 through the second input terminal In2; a second electrode of the fifth switch transistor T55 is electrically connected to a second electrode of the sixth switch transistor T56, and both the second electrode of the fifth switch transistor T55 and the second electrode of the sixth switch transistor T56 are electrically connected to the first amplifier circuit 01 through the first output terminal Out1; a control electrode of the fifth switch transistor T55 is connected to the second clock signal terminal to receive the second clock signal clk2, and a control electrode of the sixth switch transistor T56 is connected to the first clock signal terminal to receive the first clock signal clk1.

[0077] The fourth switch S4 includes a seventh switch transistor T57 and an eighth switch transistor T58. A first electrode of the seventh switch transistor T57 is electrically connected to a first electrode of the eighth switch transistor T58, and both the first electrode of the seventh switch transistor T57 and the first electrode of the eighth switch transistor T58 are electrically connected to the second load circuit 04 through the second input terminal In2; a second electrode of the seventh switch transistor T57 is electrically connected to a second electrode of the eighth switch transistor T58, and both the second electrode of the seventh switch transistor T57 and the second electrode of the eighth switch transistor T58 are electrically connected to the second amplifier circuit 02 through the second output terminal Out2; a control electrode of the seventh switch transistor T57 is connected to the first clock signal terminal to receive the first clock signal clk1, and a control electrode of the eighth switch transistor T58 is connected to the second clock signal terminal to receive the second clock signal clk2.

[0078] It can be seen from the above structure that any switch among the first switch S1 to the fourth switch S4 includes two switching transistors, and the control electrode of one of the two switching transistors always receives the first clock signal clk1, and the control electrode of the other receives the second clock signal clk2. At the same time, the levels of the first clock signal clk1 and the second clock signal clk2 are always different (or opposite). Therefore, the conduction levels of the two switching transistors included in any switch among the first switch S1 to the fourth switch S4 are different (or opposite). In order to achieve the above effect, one of the two switching transistors included in any switch among the first switch S1 to the fourth switch S4 is a P-type MOS tube, and the other is an N-type MOS tube.

[0079] In some examples, the first switch transistor T51, the third switch transistor T53, the fifth switch transistor T55, and the seventh switch transistor T57 are P-type MOS transistors; the second switch transistor T52, the fourth switch transistor T54, the sixth switch transistor T56, and the eighth switch transistor T58 are N-type MOS transistors, that is, one of the two switch transistors included in any switch of the first switch S1 to the fourth switch S4 is a P-type MOS transistor, and the other is an N-type MOS transistor. Based on this, in the same switch, the first electrodes of the two switch transistors are electrically connected, that is, the source of the P-type MOS tube is electrically connected to the drain of the N-type MOS tube; the second electrodes of the two switch transistors are electrically connected, that is, the drain of the P-type MOS tube is electrically connected to the source of the N-type MOS tube; the control electrodes of the P-type MOS tube and the N-type MOS tube are the gates.

[0080] In summary, when the offset voltage calibration circuit 05 receives the first control signal, that is, the first clock signal clk1 is at a low level and the second clock signal clk2 is at a high level, the first switch sub-circuit 051 is taken as an example for explanation. The first switch sub-circuit 051 includes a first switch S1 and a second switch S2; the first switch S1 includes a first switch transistor T51 which is a P-type MOS tube and a second switch transistor T52 which is an N-type MOS tube. The gate of the first switch transistor T51 which is a P-type MOS tube receives the first clock signal clk1 (currently at a low level), so the first switch transistor T51 is turned on, and the gate of the second switch transistor T52 which is an N-type MOS tube receives the second clock signal clk2 (currently at a high level). , so the second switch transistor T52 is also turned on, that is, the first switch S1 is connected, so that the first load circuit 03 is connected to the first amplifier circuit 01; the second switch S2 includes a third switch transistor T54 which is a P-type MOS tube and a fourth switch transistor T54 which is an N-type MOS tube. The gate of the third switch transistor T53 which is a P-type MOS tube receives the second clock signal clk2 (currently at a high level), so the third switch transistor T53 is turned off, and the gate of the fourth switch transistor T54 which is an N-type MOS tube receives the first clock signal clk1 (currently at a low level), so the fourth switch transistor T54 is also turned off, that is, the second switch S2 is not connected, so that the first load circuit 03 will not be connected to the second amplifier circuit 02. Similarly to the above, the fifth switch transistor T55 of the third switch S3, which is a P-type MOS tube, and the sixth switch transistor T56 of the N-type MOS tube, are turned off, so the third switch S3 is not connected, so the second load circuit 04 is not connected to the first amplifier circuit 01; the seventh switch transistor T57 of the fourth switch S4, which is a P-type MOS tube, and the eighth switch transistor T58 of the fourth switch S4 are turned on, so the fourth switch S4 is connected, so the second load circuit 04 is connected to the second amplifier circuit 02. When the offset voltage calibration circuit 05 receives the second control signal, the levels of the first clock signal clk1 and the second clock signal clk2 in the second control signal are opposite to the levels of the first clock signal clk1 and the second clock signal clk2 in the first control signal, that is, when the first clock signal clk1 is high and the second clock signal clk2 is low, correspondingly, the on and off states of each switch transistor are opposite to the states under the first control signal, so the first switch S1 and the fourth switch S4 are not connected, and the second switch S2 and the third switch S4 are connected. The first clock signal clk1 and the second clock signal clk2 are used to control the first load circuit 03 and the second load circuit 04 to be alternately connected to the first amplifier circuit 01 and the second amplifier circuit 02, thereby eliminating or reducing the error of the output signal of the operational amplifier caused by the offset voltage.Furthermore, the circuit of the offset signal calibration circuit 05 provided by the present disclosure is implemented by transistors (MOS tubes), and the circuit structure is relatively simple, so there is no need to add complex circuits and occupy circuit resources. In addition, when the operational amplifier is continuously working, the offset signal calibration circuit 05 can dynamically follow the operational amplifier to calibrate the offset voltage, thereby making the calibration more timely and accurate.

[0081] For some examples, see Figure 2B , Figure 3 The first load circuit 03 includes a first load transistor T31 and a second load transistor T32. The first load transistor T31 and the second load transistor T32 can be P-type MOS transistors or N-type MOS transistors. In this example, the first load transistor T31 and the second load transistor T32 are P-type MOS transistors. The source of the first load transistor T31 is electrically connected to the drain of the second load transistor T32, and the drain of the first load transistor T31 is electrically connected to the first input terminal In1 of the offset voltage calibration circuit 05.

[0082] The second load circuit 04 includes a third load transistor T33 and a fourth load transistor T34. The third load transistor T33 and the fourth load transistor T34 can be P-type MOS transistors or N-type MOS transistors. In this example, the third load transistor T33 and the fourth load transistor T34 are P-type MOS transistors. The source of the third load transistor T33 is electrically connected to the drain of the fourth load transistor T34, and the drain of the third load transistor T33 is electrically connected to the second input terminal In2 of the offset voltage calibration circuit 05.

[0083] The source of the second load transistor T32 and the source of the fourth load transistor T34 are both connected to the first power supply voltage terminal to receive the first power supply voltage VDDA.

[0084] Further, the first load transistor T31 and the third load transistor T33 are cascode transistors, which are used to increase the output impedance of the operational amplifier. Specifically, the gate of the first load transistor T31 is electrically connected to the gate of the third load transistor T33, and is commonly electrically connected to the first bias voltage terminal to receive the first bias voltage Vpcas, and the first bias voltage Vpcas is used to bias the first load transistor T31 and the third load transistor T33.

[0085] Further, the second load transistor T32 and the fourth load transistor T34 are common-mode output voltage load transistors, and the second load transistor T32 and the fourth load transistor T34 are used to make the common-mode voltage (i.e., (Vomm+Vopp) / 2) of the operational amplifier equal to the common-mode reference voltage Vcmref. The gate of the second load transistor T32 is electrically connected to the gate of the fourth load transistor T34, and is electrically connected to the common-mode voltage output terminal to receive the common-mode output voltage Vcmfb, and the common-mode output voltage Vcmfb is used to bias the second load transistor T32 and the fourth load transistor T34.

[0086] For some examples, see Figure 4 , the operational amplifier provided by the present disclosure also includes a common-mode feedback circuit 06. The common-mode feedback circuit 06 has a first input terminal, a second input terminal, a common-mode input terminal and a common-mode output terminal, wherein the first input terminal of the common-mode feedback circuit 06 is electrically connected to the output terminal Vop of the first amplifier circuit 01 to receive the amplified first differential signal, the second input terminal of the common-mode feedback circuit 06 is electrically connected to the output terminal Vom of the second amplifier circuit 02 to receive the amplified second differential signal, the common-mode input terminal of the common-mode feedback circuit 06 receives the common-mode reference voltage Vcmref, and the common-mode output terminal of the common-mode feedback circuit 06 is connected to the gate of the second load transistor T32 of the first load circuit 03 and the gate of the fourth load transistor T34 of the second load circuit 04 to feedback and output the common-mode output voltage Vcmfb. The common-mode feedback circuit 06 is also connected to the first power supply voltage terminal to receive the first power supply voltage VDDA, and connected to the second power supply voltage terminal to receive the second power supply voltage Vss.

[0087] It should be noted that one of the first power supply voltage terminal and the second power supply voltage terminal is a high voltage terminal, and the other is a low voltage terminal. Accordingly, one of the first power supply voltage VDDA and the second power supply voltage Vss is a positive voltage, and the other is a negative voltage. In the embodiments of the present disclosure, the first power supply voltage VDDA is a positive voltage, and the second power supply voltage Vss is a negative voltage. In some examples, the second power supply voltage Vss can be grounded.

[0088] The operational amplifier provided in the present disclosure may include only a single-stage amplifier circuit or a two-stage amplifier circuit, which is not limited here.

[0089] In some examples, taking the operational amplifier including a single-stage amplifier circuit as an example, the first amplifier circuit 01 includes a first amplifier transistor T11 and a first bias transistor T12. The first amplifier transistor T11 and the first bias transistor T12 can be a P-type MOS transistor or an N-type MOS transistor. In this example, the first amplifier transistor T11 and the first bias transistor T12 are N-type MOS transistors as an example for explanation. The drain of the first amplifier transistor T11 is electrically connected to the first output terminal Out1 of the offset voltage calibration circuit 05, and the source of the first amplifier transistor T11 is electrically connected to the drain of the first bias transistor T12.

[0090] The second amplifier circuit 02 includes a second amplifier transistor T21 and a second bias transistor T22. The second amplifier transistor T21 and the second bias transistor T22 can be a P-type MOS transistor or an N-type MOS transistor. In this example, the second amplifier transistor T21 and the second bias transistor T22 are N-type MOS transistors. The drain of the second amplifier transistor T21 is electrically connected to the second output terminal Out2 of the offset voltage calibration circuit 05, and the source of the second amplifier transistor T21 is electrically connected to the source of the second bias transistor T22.

[0091] The gate of the first bias transistor T12 and the gate of the second bias transistor T22 are electrically connected to the second bias voltage terminal to receive the second bias voltage Vnbias. The second bias voltage Vnbias is used to bias the first bias transistor T12 and the second bias transistor T22 so that the first bias transistor T12 provides a given bias current to the first amplifying transistor T11, and the second bias transistor T22 provides a given bias current to the second amplifying transistor T21. The drain of the first bias transistor T12 and the source of the second bias transistor T22 are connected to the second power supply voltage terminal to receive the second power supply voltage Vss.

[0092] Furthermore, the first amplifying transistor T11 and the second amplifying transistor T21 form a differential pair of transistors, and the differential pair of transistors is used to convert the differential signal Vin input to the operational amplifier circuit into a differential current Idm1.

[0093] Specifically, the difference between the first differential signal Vipp and the second differential signal Vimm is the above differential signal Vin (i.e., Vin=Vipp-Vimm), and the difference between the first output current Id_T11 and the second output current Id_T21 is the above differential current Idm1 (i.e., Idm1=Id_T11-Id_T21). The first differential signal Vipp input to the first amplifier transistor T11 is converted into the first output current Id_T11 through the transconductance gm11 of the first amplifier transistor T11, wherein the first differential signal Vipp=Vicm+Vidm / 2, Vicm is a differential input signal, and Vidm is a common mode input signal; the first output current Id_T11=gm11×Vidm / 2. Correspondingly, the second differential signal Vimm input to the second amplifying transistor T21 is converted into a second output current Id_T21 through the transconductance gm21 of the second amplifying transistor T21, wherein the second differential signal Vimm=Vicm-Vidm / 2, Vicm is the differential input signal, and Vidm is the common mode input signal; the second output current Id_T21=gm21×(-Vidm / 2), and gm11=gm21.

[0094] In some examples, the first bias transistor T12 is multiplexed as the second bias transistor T22, thereby eliminating one transistor, wherein the input current im11 of the first amplifying transistor T11 and the input current im21 of the second amplifying transistor T21 are half of the output current im12 of the first bias transistor T12, i.e., im11=im21=im12 / 2.

[0095] In some examples, taking the operational amplifier including a two-stage amplifier circuit as an example, based on the single-stage amplifier circuit, the first amplifier circuit 01 also includes a third amplifier transistor T13 and a third bias transistor T14. The third amplifier transistor T13 and the third bias transistor T14 can be a P-type MOS transistor or an N-type MOS transistor. In this example, the third amplifier transistor T13 and the third bias transistor T14 are N-type MOS transistors as an example for explanation. The gate of the third amplifier transistor T13 is electrically connected to the source of the first amplifier transistor T11, the source of the third amplifier transistor T13 is connected to the first power supply voltage terminal to receive the first power supply voltage VDDA, the drain of the third amplifier transistor T13 is electrically connected to the source of the third bias transistor T14, the gate of the third bias transistor T14 is electrically connected to the second bias voltage terminal to receive the second bias voltage Vnbias, and the drain of the third bias transistor T14 is connected to the second power supply voltage terminal to receive the second power supply voltage Vss.

[0096] The second amplifier circuit 02 further includes a fourth amplifier transistor T23 and a fourth bias transistor T24. The fourth amplifier transistor T23 and the fourth bias transistor T24 can be a P-type MOS transistor or an N-type MOS transistor. In this example, the fourth amplifier transistor T23 and the fourth bias transistor T24 are N-type MOS transistors. The gate of the fourth amplifier transistor T23 is electrically connected to the source of the second amplifier transistor T21, the source of the fourth amplifier transistor T14 is connected to the first power supply voltage terminal to receive the first power supply voltage VDDA, the drain of the fourth amplifier transistor T23 is electrically connected to the source of the fourth bias transistor T24, the gate of the fourth bias transistor T24 is electrically connected to the second bias voltage terminal to receive the second bias voltage Vnbias, and the drain of the fourth bias transistor T24 is connected to the second power supply voltage terminal to receive the second power supply voltage Vss.

[0097] Based on the above disclosure, the first amplifier transistor T11 and the first bias transistor T12 constitute the first stage amplifier circuit of the first amplifier circuit 01, the third amplifier transistor T13 and the third bias transistor T14 constitute the second stage amplifier circuit of the first amplifier circuit 01; the second amplifier transistor T21 and the second bias transistor T22 constitute the first stage amplifier circuit of the second amplifier circuit 02, and the fourth amplifier transistor T23 and the fourth bias transistor T44 constitute the second stage amplifier circuit of the second amplifier circuit 02. The second bias voltage Vnbias is used to bias the third bias transistor T14 and the fourth bias transistor T24, so that the third bias transistor T14 provides a given bias current to the third amplifier transistor T13, and the fourth bias transistor T24 provides a given bias current to the fourth amplifier transistor T23.

[0098] Further, the voltage Vg_T13 on the gate of the third amplifier transistor T13 is determined by the first output current Id_T11 of the first amplifier transistor T11 and the output impedance Ro1_left of the branch formed by the first amplifier transistor T11, the first load transistor T31 and the second load transistor T32, that is, Vg_T13=Id_T11×Ro1_left; accordingly, the voltage Vg_T23 on the gate of the fourth amplifier transistor T23 is determined by the second output current Id_T21 of the second amplifier transistor T21 and the output impedance Ro1_right of the branch formed by the second amplifier transistor T21, the third load transistor T33 and the fourth load transistor T34, that is, Vg_T23=Id_T21×Ro1_right, wherein Ro1_left=Ro1_right.

[0099] Further, the third amplifying transistor T13 converts the voltage Vg_T13 on the gate into a third output current Id_T13 (i.e., differential current) through the transconductance gm_T13 of the third amplifying transistor T13, i.e., Id_T13=gm_T13×Vg_T13, and the amplified first differential signal Vopp outputted from the first output terminal of the first amplifying circuit 01 is calculated according to the formula: Vopp=Id_T13×Ro2_left, where Ro2_left is the output impedance of the second stage amplifying circuit of the first amplifying circuit 01; accordingly, the fourth amplifying transistor T23 converts the voltage Vg_T23 on the gate into a fourth output current Id_T23 (i.e., differential current) through the transconductance gm_T23 of the fourth amplifying transistor T23, i.e., Id_T23=gm_T23×Vg_T23. The amplified second differential signal Vomm output from the first output end of the second amplifying circuit 02 is calculated according to the formula: Vomm=Id_T23×Ro2_right, Ro2_right is the output impedance of the second stage amplifying circuit of the second amplifying circuit 02, wherein Ro2_left=Ro2_right.

[0100] In summary, the differential signal (Vopp-Vomm) output by the operational amplifier provided in the present disclosure can be calculated according to the following formula:

[0101] Vopp-Vomm

[0102] =Id_T13×Ro2_left-Id_T23×Ro2_right

[0103] =gm_T13×Ro2_left×(Vg_T13-Vg_T23)

[0104] =gm_T23×Ro2_right×(Vg_T13-Vg_T23)

[0105] =gm_T13×Ro2_left×gm_T11×Ro1_left×(Vipp-Vimm)

[0106] =gm_T23×Ro2_right×gm_T21×Ro1_right×(Vipp-Vimm).

[0107] In some examples, the operational amplifier provided by the present disclosure further includes a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2.

[0108] The first capacitor C1 and the first resistor R1 form a first filtering subcircuit of the first amplifier circuit 01, the first end of the first capacitor C1 is electrically connected to the output end Vop of the first amplifier circuit 01, the second end of the first capacitor C1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the first electrode of the first amplifier transistor T11. The second capacitor C2 and the second resistor R2 form a second filtering subcircuit of the second amplifier circuit 02, the first end of the second capacitor C2 is electrically connected to the output end Vom of the second amplifier circuit 02, the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the first electrode of the second amplifier transistor T21.

[0109] According to a second aspect of the present disclosure, a modulator is provided, the modulator comprising the operational amplifier described in any of the above embodiments. The modulator can be various types of modulators, such as a Sigma-Delta modulator (hereinafter referred to as SDM), and the following description is based on the modulator being a Sigma-Delta modulator as an example.

[0110] In some examples, the SDM generally further includes a switched capacitor circuit, the switched capacitor circuit includes a level switch, the level switch is connected to the clock signal end, and the clock signal controls the opening and closing of the level switch. In the operational amplifier provided by the present disclosure, the first control signal and the second control signal for controlling the offset voltage calibration circuit 05 both include the first clock signal clk1 and the second clock signal clk2. Therefore, when the operational amplifier is applied to the SDM, the clock signal of the switched capacitor circuit of the SDM can be directly connected to the offset voltage calibration circuit 05 of the operational amplifier, thereby eliminating the need to separately set the circuit of the clock signal end required by the offset voltage calibration circuit 05, further simplifying the circuit and saving circuit resources.

[0111] Specifically, Figure 5 Taking the SDM circuit of FIG. 1 as an example, the SDM may include a first switched capacitor circuit P1 and a second switched capacitor circuit P2.

[0112] Wherein, the first switch capacitor circuit P1 includes a first level switch K7 and a first input capacitor C3, the first end of the first level switch K7 is electrically connected to the input end Vip of the first amplifier circuit 01 of the operational amplifier OPAMP, the second end of the first level switch K7 is connected to the second plate of the first input capacitor C3, the first plate of the first input capacitor C3 is connected to the input switch (K1, K2, K3) of the first branch of the SDM, the control end of the first level switch K7 is electrically connected to the first clock signal end to receive the first clock signal clk1, and the first clock signal clk1 controls the opening and closing of the first level switch K7. In addition, the first clock signal end is electrically connected to the offset voltage calibration circuit 05 of the operational amplifier OPAMP, specifically, connected to the gates of the first switch transistor T51, the fourth switch transistor T54, the sixth switch transistor T56, and the seventh switch transistor T57 of the offset voltage calibration circuit.

[0113] The second switch capacitor circuit P2 includes a second level switch K8 and a second input capacitor C4, the first end of the second level switch K8 is electrically connected to the input end Vim of the second amplifier circuit 02 of the operational amplifier OPAMP, the second end of the second level switch K8 is connected to the second plate of the second input capacitor C4, the first plate of the second input capacitor C4 is connected to the input switch (K4, K5, K6) of the second branch of the SDM, the control end of the second level switch K8 is electrically connected to the second clock signal end to receive the second clock signal clk2, and the second clock signal clk2 controls the opening and closing of the second level switch K8. In addition, the second clock signal end is electrically connected to the offset voltage calibration circuit 05 of the operational amplifier OPAMP, specifically, connected to the gates of the second switch transistor T52, the third switch transistor T53, the fifth switch transistor T55, and the eighth switch transistor T58 of the offset voltage calibration circuit. Based on this, the first control signal received by the offset voltage calibration signal can be represented by the first clock signal clk1 being the first level and the second clock signal clk2 being the second level; the second control signal can be represented by the first clock signal clk being the second level and the second clock signal clk2 being the first level.

[0114] For some examples, see Figure 5 The SDM provided by the present disclosure may also include a first branch input switch and a second branch input switch. The differential signal input by the first branch input switch is the first differential signal of the input terminal Vip of the first amplifier circuit 01 of the input operational amplifier OPAMP, and the differential signal input by the second branch input switch is the second differential signal of the input terminal Vim of the second amplifier circuit 02 of the input operational amplifier OPAMP.

[0115] The first branch input switch may include a first branch switch K1, the first branch receives a first reference voltage Vrefp; a second branch switch K2, the second branch receives a ground voltage gnda; a third branch switch K3, the third branch receives a first input signal Inp. The second branch input switch may include a fourth branch switch K4, the fourth branch receives a second input signal Inn; a fifth branch switch K5, the fifth branch receives a ground voltage gnda; and a sixth branch switch K6, the sixth branch receives a second reference voltage Vrefn.

[0116] It should be noted that the first reference voltage Vrefp is a positive voltage, and the second reference voltage Vrefn is a negative voltage. Accordingly, the first input signal Inp is a positive phase input signal, and the second input signal Inn is a reverse input signal. The first branch switch K1 to the sixth branch switch K6 can all adopt level switches, and the six branch switches are respectively connected to six clock signals, and the clock cycles of the six clock signals are consistent, which is the sampling frequency of the SDM. Based on this, in the operational amplifier provided by the present disclosure, the clock cycle of the first clock signal clk1 and the second clock signal clk2 is less than the clock cycle of the clock signal connected to any branch switch of the first branch switch K1 to the sixth branch switch K6.

[0117] For some examples, see Figure 5 The SDM provided by the present disclosure may also include a first feedback capacitor C5 and a second feedback capacitor C6, wherein the first feedback capacitor C5 is connected between the input terminal Vip and the output terminal Vop of the first amplifying circuit 01 of the operational amplifier OPAMP; the second feedback capacitor C6 is connected between the input terminal Vim and the output terminal Vom of the second amplifying circuit 02 of the operational amplifier OPAMP.

[0118] For some examples, see Figure 5 , the SDM provided by the present disclosure may also include a comparator COMP, a first input terminal of the comparator COMP is electrically connected to the output terminal Vop of the operational amplifier, a second input terminal of the comparator COMP is electrically connected to the output terminal Vom of the operational amplifier, two differential signals (including the amplified first differential signal and the second differential signal) output by the fully differential operational amplifier OPAMP are respectively input to the two input terminals of the comparator COMP, if the first differential signal is greater than the second differential signal, the output terminal of the comparator COMP outputs 1; if the first differential signal is less than the second differential signal, the output terminal of the comparator COMP outputs 0. The comparator COMP also has a clock input terminal (not shown in the figure), the clock input terminal is connected to a clock signal source, and receives a clock signal, the clock period of the clock signal is the working period of the comparator COMP.

[0119] For some examples, see Figure 5The SDM provided in the present disclosure may also include an inverter INV1, the input end of the inverter INV1 is electrically connected to the output end of the comparator COMP, if the output end of the comparator COMP outputs 1, the output end of the inverter INV1 outputs 0; if the output end of the comparator COMP outputs 0, the output end of the inverter INV1 outputs 1, and the output end of the inverter INV1 is the output end B1 of the SDM output bitstream (Bitstream).

[0120] See also Figure 5 , taking 1-bit SDM as an example, the working principle of SDM is explained: in the first stage, the third branch switch K3 is closed to receive the first input signal Inp, and Inp is shorted to the first plate of the first input capacitor C3; the fourth branch switch K4 is closed to receive the second input signal Inn, and Inn is shorted to the first plate of the second input capacitor C4, and the branch switches on Vrefp / Vrefn / gnda are all open; the second plates of the first input capacitor C3 and the second input capacitor C4 are shorted to the first common-mode switch K9 and the second common-mode switch K10 respectively, and the first common-mode switch K9 and the second common-mode switch K10 are connected to the common-mode reference voltage terminal to receive the common-mode reference voltage Vcmref. In the first stage, K9 and K10 are closed to provide a reference voltage (i.e., Vcmref) to the first input capacitor C3 and the second input capacitor C4; in the second stage, the third branch switch K3 and the fourth branch switch K4 are opened, and the first common-mode switch K9 and The second common-mode switch K10 is also disconnected, and the first level switch K7 and the second level switch K8 are closed. The first input signal Inn is input as the first differential signal to the input terminal Vip of the OPAMP, and the second input signal Inp is input as the second differential signal to the input terminal Vim of the OPAMP. If the output of the comparator COMP is 0, the second branch switch K2 and the third branch switch K3 are disconnected, and the fifth branch switch K5 and the sixth branch switch K6 are closed, then the second differential signal is greater than the first differential signal, and the comparator COMP output is 0. After the inversion of the inverter INV1, the output terminal B1 of the SDM is 1; if the comparator COMP output is 1, the second branch switch K2 and the third branch switch K3 are closed, and the fifth branch switch K5 and the sixth branch switch K6 are disconnected, then the first differential signal is greater than the second differential signal, and the comparator COMP output is 1. After the inversion of the inverter INV1, the output of the output terminal B1 of the SDM is 0. The SDM works continuously according to the above method and can realize 1-bit Sigma-Delta conversion, and the offset voltage calibration circuit 05 of the OPAMP dynamically calibrates the offset voltage to eliminate or reduce the output error of the OPAMP, thereby improving the output reliability of the SDM. Of course, the circuit of the SDM can also adopt other types of structures, which are not limited here.

[0121] According to a third aspect of the present disclosure, a temperature sensor is provided, which includes the operational amplifier and / or the Sigma-Delta modulator. The temperature sensor may also include a temperature measurement circuit (not shown in the figure), which may be electrically connected to the Sigma-Delta modulator.

[0122] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An operational amplifier, wherein: include: A first amplifier circuit, a second amplifier circuit, a first load circuit, a second load circuit and an offset voltage calibration circuit; wherein, The offset voltage calibration circuit is configured to connect the first load circuit to the first amplification circuit and the second amplification circuit alternately, and to connect the second load circuit to the first amplification circuit and the second amplification circuit alternately.

2. The operational amplifier according to claim 1, wherein: The offset voltage calibration circuit is configured to connect the first load circuit to the first amplifier circuit and the second amplifier circuit alternately, and connect the second load circuit to the first amplifier circuit and the second amplifier circuit alternately, including: When the first load circuit is connected to the first amplifier circuit, the second load circuit is connected to the second amplifier circuit; When the first load circuit is connected to the second amplifying circuit, the second load circuit is connected to the first amplifying circuit.

3. The operational amplifier according to claim 1, wherein: The offset voltage calibration circuit is configured to connect the first load circuit to the first amplifier circuit and the second amplifier circuit alternately, and connect the second load circuit to the first amplifier circuit and the second amplifier circuit alternately, including: When receiving a first control signal, the offset voltage calibration circuit connects the first load circuit to the first amplifier circuit and connects the second load circuit to the second amplifier circuit; when receiving a second control signal, the offset voltage calibration circuit connects the first load circuit to the second amplifier circuit and connects the second load circuit to the first amplifier circuit.

4. The operational amplifier according to claim 3, wherein: The offset voltage calibration circuit includes a first switch subcircuit and a second switch subcircuit; wherein, The first switch subcircuit includes a first switch and a second switch, wherein a first end of the first switch is electrically connected to the first load circuit, and a second end of the first switch is electrically connected to the first amplifier circuit; a first end of the second switch is electrically connected to the first load circuit, and a second end of the second switch is electrically connected to the second amplifier circuit; The second switch subcircuit comprises a third switch and a fourth switch, wherein a first end of the third switch is electrically connected to the second load circuit, and a second end thereof is electrically connected to the first amplifier circuit; a first end of the fourth switch is electrically connected to the second load circuit, and a second end thereof is electrically connected to the second amplifier circuit; When a first control signal is received, the first switch is connected to the fourth switch; when a second control signal is received, the second switch is connected to the third switch.

5. The operational amplifier according to claim 4, wherein: The first switch includes a first switch transistor and a second switch transistor; a first electrode of the first switch transistor is electrically connected to a first electrode of the second switch transistor, and is electrically connected to the first load circuit; a second electrode of the first switch transistor is electrically connected to a second electrode of the second switch transistor, and is electrically connected to the first amplifier circuit; a control electrode of the first switch transistor is connected to a first clock signal terminal, and a control electrode of the second switch transistor is connected to a second clock signal terminal; The second switch includes a third switch transistor and a fourth switch transistor; a first electrode of the third switch transistor is electrically connected to a first electrode of the fourth switch transistor, and is electrically connected to the first load circuit; a second electrode of the third switch transistor is electrically connected to a second electrode of the fourth switch transistor, and is electrically connected to the second amplifier circuit; a control electrode of the third switch transistor is connected to a second clock signal terminal, and a control electrode of the fourth switch transistor is connected to a first clock signal terminal; The third switch includes a fifth switch transistor and a sixth switch transistor; the first electrode of the fifth switch transistor is electrically connected to the first electrode of the sixth switch transistor, and is electrically connected to the second load circuit; the second electrode of the fifth switch transistor is electrically connected to the second electrode of the sixth switch transistor, and is electrically connected to the first amplifier circuit; the control electrode of the fifth switch transistor is connected to the second clock signal terminal, and the control electrode of the sixth switch transistor is connected to the first clock signal terminal; The fourth switch includes a seventh switch transistor and an eighth switch transistor; the first electrode of the seventh switch transistor is electrically connected to the first electrode of the eighth switch transistor, and is electrically connected to the second load circuit; the second electrode of the seventh switch transistor is electrically connected to the second electrode of the eighth switch transistor, and is electrically connected to the second amplifier circuit; the control electrode of the seventh switch transistor is connected to the first clock signal terminal, and the control electrode of the eighth switch transistor is connected to the second clock signal terminal; Among them, the first clock signal end is used to provide a first clock signal, and the second clock signal end is used to provide a second clock signal; the first control signal is represented by the first clock signal being a first level and the second clock signal being a second level; the second control signal is represented by the first clock signal being a second level and the second clock signal being a first level, and the first level is different from the second level.

6. The operational amplifier according to claim 5, wherein: The first switch transistor, the third switch transistor, the fifth switch transistor and the seventh switch transistor are P-type field effect transistors; The second switch transistor, the fourth switch transistor, the sixth switch transistor and the eighth switch transistor are N-type field effect transistors.

7. The operational amplifier according to any one of claims 1 to 6, wherein: The first load circuit includes a first load transistor and a second load transistor; the first electrode of the first load transistor is electrically connected to the second electrode of the second load transistor, and the second electrode is electrically connected to the first input terminal of the offset voltage calibration circuit; The second load circuit includes a third load transistor and a fourth load transistor; the first electrode of the third load transistor is electrically connected to the second electrode of the fourth load transistor, and the second electrode is electrically connected to the second input terminal of the offset voltage calibration circuit; The first electrode of the second load transistor and the first electrode of the fourth load transistor are connected to a first power supply voltage terminal; the control electrode of the first load transistor is electrically connected to the control electrode of the third load transistor, and they are jointly electrically connected to a first bias voltage terminal; the control electrode of the second load transistor is electrically connected to the control electrode of the fourth load transistor, and they are jointly electrically connected to a common-mode voltage output terminal.

8. The operational amplifier according to any one of claims 1 to 6, wherein: The first amplifier circuit includes a first amplifier transistor and a first bias transistor; a first electrode of the first amplifier transistor is electrically connected to a first output terminal of the offset voltage calibration circuit, and a second electrode is electrically connected to a first electrode of the first bias transistor; The second amplifier circuit includes a second amplifier transistor and a second bias transistor; A first electrode of the second amplifying transistor is electrically connected to a second output terminal of the offset voltage calibration circuit, and a second electrode is electrically connected to a first electrode of the second biasing transistor; The control electrode of the first bias transistor and the control electrode of the second bias transistor are electrically connected to a second bias voltage terminal; the second electrode of the first bias transistor and the second electrode of the second bias transistor are connected to a second power supply voltage terminal.

9. The operational amplifier according to claim 8, wherein: The first bias transistor is multiplexed as the second bias transistor.

10. The operational amplifier according to claim 8, wherein: The first amplifier circuit further includes a third amplifier transistor and a third bias transistor; the control electrode of the third amplifier transistor is electrically connected to the first electrode of the first amplifier transistor, the first electrode is connected to the first power supply voltage terminal, and the second electrode is electrically connected to the first electrode of the third bias transistor; the control electrode of the third bias transistor is electrically connected to the second bias voltage terminal, and the second electrode is connected to the second power supply voltage terminal; The second amplifier circuit also includes a fourth amplifier transistor and a fourth bias transistor; The control electrode of the fourth amplifying transistor is electrically connected to the first electrode of the second amplifying transistor, the first electrode is connected to the first power supply voltage terminal, and the second electrode is electrically connected to the first electrode of the fourth biasing transistor; the control electrode of the fourth biasing transistor is electrically connected to the second biasing voltage terminal, and the second electrode is connected to the second power supply voltage terminal.

11. The operational amplifier according to any one of claims 1 to 6, wherein: Also includes: a first capacitor, a second capacitor, a first resistor and a second resistor; The first end of the first capacitor is electrically connected to the output end of the first amplifier circuit, the second end of the first capacitor is connected to the first end of the first resistor, and the second end of the first resistor is electrically connected to the input end of the first amplifier circuit; The first end of the second capacitor is electrically connected to the output end of the second amplifier circuit, the second end is connected to the first end of the second resistor, and the second end of the second resistor is electrically connected to the input end of the second amplifier circuit.

12. The operational amplifier according to any one of claims 1 to 6, wherein: It also includes: a common-mode feedback circuit; the first input end of the common-mode feedback circuit is electrically connected to the output end of the first amplifier circuit, the second input end is electrically connected to the output end of the second amplifier circuit, and the common-mode voltage output end is electrically connected to the first load circuit and the second load circuit.

13. The operational amplifier according to claim 12, wherein: The first load circuit includes a first load transistor and a second load transistor, wherein a first electrode of the first load transistor is electrically connected to a second electrode of the second load transistor; The second load circuit comprises a third load transistor and a fourth load transistor, wherein a first electrode of the third load transistor is electrically connected to a second electrode of the fourth load transistor; The first electrode of the second load transistor and the first electrode of the fourth load transistor are connected to the first power supply voltage terminal; the control electrode of the second load transistor is electrically connected to the control electrode of the fourth load transistor, and are electrically connected to the common mode voltage output terminal.

14. A modulator, wherein: Comprising the operational amplifier described in any one of claims 1-13.

15. The modulator of claim 14, wherein: Also included: a first switched capacitor circuit and a second switched capacitor circuit; The first switched capacitor circuit comprises a first level switch, a first end of the first level switch is electrically connected to the input end of the first amplifier circuit, and a control end is electrically connected to the first clock signal end; The second switched capacitor circuit comprises a second level switch, a first end of the second level switch is electrically connected to the input end of the second amplifier circuit, and a control end is electrically connected to the second clock signal end; The offset voltage calibration circuit is electrically connected to the first clock signal terminal and the second clock signal terminal; wherein, The first clock signal terminal is used to provide a first clock signal, and the second clock signal terminal is used to provide a second clock signal; the first control signal indicates that the first clock signal is a first level and the second clock signal is a second level; the second control signal indicates that the first clock signal is a second level and the second clock signal is a first level.

16. A temperature sensor, wherein: It comprises the operational amplifier described in any one of claims 1-13, and / or the modulator described in any one of claims 14-15.

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