Package structure

Abstract

The utility model provides a packaging structure comprising a first packaging assembly comprising a dielectric layer comprising a top surface; a silicon-containing dielectric layer over and in contact with the dielectric layer, where the silicon-containing dielectric layer has a first thickness of less than about 100 angstroms; and a second package component bonded to the silicon-containing dielectric layer of the first package component. According to the utility model, the thermal resistance in a heat dissipation path can be reduced, and the bonding strength is improved.

Description

Technical Field

[0001] The embodiment of the utility model relates to a packaging structure. Background Art

[0002] Fusion bonding is a common bonding scheme for bonding two package components (such as wafers and / or dies) to each other. In the bonding process, the package components are first bonded by pre-bonding at a lower temperature, and then a bonding process is performed at a higher temperature to bond the package components together. Utility Model Content

[0003] An embodiment of the utility model provides a packaging structure, comprising: a first packaging component, comprising: a dielectric layer, including a top surface; a silicon-containing dielectric layer, located above the dielectric layer and contacting the dielectric layer, wherein the silicon-containing dielectric layer has a first thickness of less than about 100 angstroms; and a second packaging component, bonded to the silicon-containing dielectric layer of the first packaging component.

[0004] An embodiment of the utility model provides a packaging structure, comprising: a device die, comprising: a first semiconductor substrate; a dielectric layer; a conductive feature located in the dielectric layer; and a first bonding film located above the dielectric layer and the conductive feature, and in physical contact with the dielectric layer and the conductive feature, wherein the first bonding film has a thickness of less than about 50 angstroms; and a second package, comprising: a second bonding film bonded to the first bonding film; and a second semiconductor substrate located above the second bonding film. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] When read in conjunction with the accompanying drawings, the aspects of the present invention are best understood from the following detailed description. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1-Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 6 , Figure 7 and 8A A cross-sectional view of an intermediate stage in package formation including a fusion bonding process is shown in accordance with some embodiments.

[0007] Figure 8B A cross-sectional view of a package according to an alternative embodiment is shown.

[0008] Fig. 9 , Fig.10 and Fig.11Packages formed by a wafer-to-carrier bonding process, a chip-to-wafer bonding process, and a chip-to-chip bonding process according to some embodiments are respectively illustrated.

[0009] Fig. 12A and Fig. 12B A processing pattern of a bonding film in a device die is shown according to some embodiments.

[0010] Fig.13 Processed patterns in a wafer are shown according to some embodiments.

[0011] Fig.14 and Fig.15 Some oxygen distribution curves in a treated portion and an adjacent untreated portion are shown according to some embodiments.

[0012] Fig.16 Surface roughness of bonding films according to some embodiments is shown as a function of thickness.

[0013] Fig.17 The signal intensity of Si—OH measured in the bonding film by FTIR spectroscopy according to some embodiments is shown.

[0014] Fig.18 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0015] The following utility model content provides many different embodiments or examples for implementing the different features of the provided theme. Specific examples of components and configurations are described below to simplify the utility model content. Of course, these specific examples are only examples and are not intended to be restrictive. For example, in the following description, a first feature is formed above or on a second feature, which may include an embodiment in which the first feature is directly contacted with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the utility model content may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "lower," "above," "upper," and the like may be used to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of a component in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] A package and a method for forming a package by fusion bonding. According to some embodiments, a flat surface of a package component is formed. A thin bonding film is deposited on the flat surface. The process of forming the bonding film is controlled so that the surface of the thin bonding film is rich in Si-OH. The thin bonding film is deposited by atomic layer deposition, and the thickness of the thin bonding film is small. The surface roughness of the bonding film is small, so there is no need to perform a flattening process on the thinner bonding film, and the surface roughness of the bonding film is small enough for fusion bonding to connect the package component to another package component. The embodiments discussed herein are intended to provide examples to implement or use the subject matter of the present disclosure, and those with general knowledge in the art will easily understand the modifications that can be made while remaining within the intended scope of different embodiments. In various views and illustrative embodiments, the same reference numerals are used to indicate the same components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0018] Figure 1-Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 6 , Figure 7 and 8A 1 shows a cross-sectional view of an intermediate stage in package formation including a fusion bonding process according to some embodiments. The corresponding process is also schematically shown in FIG. Fig.18 The process flow shown.

[0019] Figure 1 A cross-sectional view of a package assembly 20 is shown. According to some embodiments, the package assembly 20 is or includes a device wafer that includes active devices and possible passive devices (which are represented as integrated circuit devices 26). The package assembly 20 may include a plurality of dies 22, of which details of one die 22 are shown. According to an alternative embodiment, the package assembly 20 is an interposer wafer that does not contain active devices and may or may not include passive devices. According to yet another alternative embodiment, the package assembly 20 is or includes a package such as an integrated fan-out (InFO) package. For example, the package assembly 20 may be a reconstructed wafer that includes device dies and / or wafers bonded together and encapsulated in an encapsulation compound such as a molding compound. The package assembly 20 may also be a silicon carrier that may be free of metal features (except alignment marks) and free of active devices therein.

[0020] The package assembly 20 may be at the die level, rather than the wafer level, and may be a device die, an interposer die, a separate package (which has been cut from a reconstituted wafer), etc. In the subsequent discussion, the device wafer is discussed as an example of the package assembly 20, and the package assembly 20 may also be referred to as the wafer 20. These embodiments may also be applied to an interposer wafer, a reconstituted wafer, a separate package, a separate device die, a separate interposer die, etc.

[0021] According to some embodiments, wafer 20 includes a semiconductor substrate 24 and features formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may be made of crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, etc. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate.

[0022] According to some embodiments, wafer 20 includes integrated circuit devices 26 formed at a top surface of semiconductor substrate 24. Integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like according to some embodiments. Details of integrated circuit devices 26 are not described herein.

[0023] An interlayer dielectric (ILD) layer 28 is formed over semiconductor substrate 24 and fills spaces between gate stacks of transistors (not shown) in integrated circuit device 26. According to some embodiments, ILD layer 28 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride, etc. ILD layer 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), etc.

[0024] Contact plugs 30 are formed in ILD layer 28 and are used to electrically connect integrated circuit device 26 to the overlying metal lines and vias. According to some embodiments, contact plugs 30 are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.

[0025] Interconnect structure 32 is formed above ILD layer 28 and contact plug 30. Interconnect structure 32 may include metal lines 34 and vias 36, which are formed in dielectric layer 38 (also referred to as intermetallic dielectric (IMD) layer). Metal lines of the same level are collectively referred to as metal layers below. According to some embodiments, interconnect structure 32 includes interconnection with multiple metal layers through vias 36. Metal lines 34 and vias 36 may be formed of copper, copper alloys and / or another metal. According to some embodiments, dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be less than about 3.0. Dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen siloxane (HSQ), methyl siloxane (MSQ), etc.

[0026] The interconnect structure 32 may also include a passivation layer, which may be formed of a non-low-k dielectric material over the low-k dielectric layer. The passivation layer may be formed of or include undoped silicate glass (USG), silicon nitride, silicon oxide, etc., or multiple layers thereof. There may also be metal pads (e.g., aluminum-copper pads), post-passivation interconnects (PPIs), metal pads, etc., which are referred to as conductive features.

[0027] Figures 1 to 3 The formation of the top conductive feature 35 according to some embodiments is shown. Figure 1 As shown, a dielectric layer 39 is formed. The dielectric layer 39 may be a passivation layer and may be formed of USG, SiN, SiC, SiCN, etc. According to other embodiments, the dielectric layer 39 may be formed of or include a low-k dielectric material. The dielectric layer 39 may be a single layer formed of a homogeneous material, or may be a composite layer including more than one layer (e.g., two dielectric layers and an etch stop layer located therebetween).

[0028] An opening 37 is formed in the dielectric layer 39 by an etching process. Fig.18 As shown, the various processes are shown as process 202 in process flow 200. Opening 37 may include via opening 37A and trench 37B.

[0029] Next, if Figure 2 As shown, a conductive material is deposited. Fig.18 As shown, the corresponding process is shown as process 204 in process flow 200. According to some embodiments, the conductive material includes a conductive diffusion barrier layer 35A and a metal layer 35B. The conductive diffusion barrier layer 35A may be formed of Ti, TiN, Ta, TaN, etc. The metal layer 35B may include copper, copper alloy, aluminum, nickel, tungsten, etc.

[0030] refer to Figure 3 , and perform a planarization process. Fig.18As shown, each process is shown as process 206 in process flow 200. The planarization process can be performed by a chemical mechanical polishing (CMP) process, a mechanical grinding process, etc. For example, the wafer 20 can be placed on the polishing pad 41 (opposite to the direction shown) while rotating the wafer 20 and / or the polishing pad 41 to planarize the wafer 20. The remaining portion of the conductive diffusion barrier layer 35A and the metal layer 35B is referred to as the conductive feature 35 below. The top surfaces of the conductive feature 35 and the dielectric layer 39 are coplanar and have as low a roughness as possible. The planarization process is controlled to achieve good uniformity, which can be less than 1%, where the uniformity is the thickness uniformity of the entire layer. The root mean square of the surface roughness Ra and the surface roughness Rq can be controlled to be less than about 1 angstrom.

[0031] refer to Figure 4A , depositing the bonding film 42. Fig.18 As shown, the corresponding process is shown as process 208 in process flow 200. According to some embodiments, the bonding film 42 is deposited using atomic layer deposition (ALD), which can be plasma enhanced ALD (PECVD). According to some embodiments, the PEALD process includes multiple cycles. Each cycle includes pulse treatment and then cleaning the first precursor (the first precursor is a silicon-containing precursor), and pulse treatment and then cleaning the second precursor (the second precursor contains an element selected from oxygen, nitrogen, carbon, etc. and combinations thereof). Each cycle further includes turning on the plasma and then turning off the plasma to react the precursor. According to some embodiments, the silicon-containing precursor can be selected from silane, disilane, aminosilane, di-sec-butylaminosilane (DSBAS), bis (tert-butylamino) silane (BTBAS) and combinations thereof. The silicon-containing precursor may include or not include oxygen and / or carbon. The second precursor may be selected from N2O, N2, O2 and / or the like and combinations thereof, and may include or not include carbon.

[0032] The material of the bonding film 42 can be expressed as SiO x N y C z , wherein x is in a range between about 0 and about 2, y is in a range between about 0 and about 1.33, and z is in a range between about 0 and about 1. At least one or more values ​​of x, y, and z are greater than zero. For example, the bonding film 42 may be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, SiO2, or the like.

[0033] The ALD (PEALD) process is used for deposition, and also because the bonding film 42 is deposited on a highly flat surface, the top surface of the bonding film 42 is sufficiently flat, with small uniformity and small roughness. As a result, the bonding film 42 does not need to be flattened (e.g., by CMP or mechanical grinding) for subsequent bonding processes. For example, the thickness uniformity of the bonding film 42 is less than 1%. The root mean square of the surface roughness Ra and the surface roughness Rq can also be less than about 1 angstrom. Experimental results show that the uniformity of the bonding film 42 is less than 1% (and less than 5 angstroms), the values ​​of the surface roughness Ra and the surface roughness Rq are less than 1 angstrom, and the bonding can achieve the bonding strength required for strong bonding greater than 2.5 joules / square meter.

[0034] Conventionally, bonding films are deposited using plasma enhanced chemical vapor deposition (PECVD) because the high deposition rate of PECVD can meet the requirements of conventional thick bonding films, while the deposition rate of ALD is too low to deposit thick bonding films. However, the bonding film formed using PECVD has high non-uniformity values ​​greater than 1% and greater than 50 angstroms. The corresponding surface roughness Ra and surface roughness Rq values ​​will also be greater than 3 angstroms. Such a rough bonding film cannot be directly used for bonding without a planarization process. According to an embodiment of the present disclosure, the planarization process can be skipped without sacrificing the bonding quality.

[0035] Fig.16 The surface roughness of the bonding film is illustrated as a function of the thickness of the deposited film. Fig.16 It is shown that as the thickness of the deposited film increases, the values ​​of surface roughness Ra and Rq also increase. For example, when the deposition thickness is 20 angstroms, 50 angstroms, 100 angstroms, and 1,500 angstroms, the measured Rq values ​​are 0.738 angstroms, 0.797 angstroms, 0.961 angstroms, and 1.61 angstroms, respectively. The measured Ra values ​​are 0.586 angstroms, 0.633 angstroms, 0.767 angstroms, and 1.27 angstroms, respectively. Therefore, in order to meet the requirement of the bonding film having a roughness of less than 1 angstrom described in the specification, the bonding film 42 ( Figure 4A ) is less than 100 angstroms, and may be less than about 50 angstroms to provide sufficient process margins. The thickness T1 may also be in a range between about 20 angstroms and about 50 angstroms.

[0036] In order to achieve strong bonding, it is desirable that the bonding film 42 is rich in Si-OH (when bonding). According to some embodiments, due to the rich Si-OH, when measured using phase FTIR spectroscopy, the signal intensity SS SiOH / Signal StrengthSS SiO The ratio is higher than 0.015, where the signal strength SS SiOH is the signal intensity of the Si-OH peak measured near the junction energy of 3,500 eV. The signal intensity SS SiOis the total signal intensity of all SiO networks measured around the junction energy of 1,100 eV. Signal intensity SS SiOH like Fig.17 As shown, the measured signal strength SS SiO The junction energy of 1,100eV exceeds Fig.17 The engagement shown can be shown to the extent possible.

[0037] The percentage of N2O and N2 in the second precursor for the PEALD cycle can be increased. For example, when the second precursor is introduced into the ALD chamber, the flow rate ratio of (N2O+N2) / (N2O+N2+O2) can be greater than about 0.2, and can be in a range between about 0.2 and about 1. In addition, to increase the number of Si-OH bonds, the duration of plasma on in each PEALD cycle can be shortened, for example, shorter than about 0.5 seconds, and can be between about 0 seconds and about 0.5 seconds. In addition, the RF power used to turn on the plasma can be increased, for example, greater than about 3000 watts, and can be in a range between about 3000 watts and about 6000 watts.

[0038] Figure 4B and Figure 4C The formation of a bonding film and underlying structure according to alternative embodiments is shown. These embodiments are similar to Figure 4A The embodiment shown in FIG. 1 is different in that a planarization layer 43 is formed between the bonding film 42 and the conductive feature 35. According to these embodiments, after the conductive feature 35 is formed, as shown in FIG. Figure 4B As shown, a planarization layer 43 is deposited. The planarization layer 43 may be formed by a high deposition rate deposition process such as CVD, PECVD, etc. The thickness T2 of the planarization layer 43 is greater than the thickness T1 of the subsequently deposited bonding film 42, and may be in the range between about 2k angstroms (2000 angstroms) and about 4k angstroms (4000 angstroms). The material of the planarization layer 43 may be selected from SiON, SiO, SiN, SiC, SiCN, SiOCN, USG, etc. and combinations thereof.

[0039] Since the planarization layer 43 is thick, the surface roughness is high, for example, the surface roughness is greater than about 50 angstroms. Therefore, a planarization process (using the polishing pad 41) is performed to reduce the values ​​of the surface roughness Ra and Rq to the range of the specification, for example, less than 1 angstrom, and can be less than about 0.8 angstroms. It should be understood that the wafer 20 can be polished while being placed on the polishing pad 41.

[0040] The bonding film 42 is formed as follows Figure 4C As shown, its formation process, material and thickness are similar to Figure 4AThe description in is basically the same and will not be repeated here. According to some embodiments, although the planarization layer 43 and the bonding film 42 can be selected from the same group of materials, the material of the planarization layer 43 can be the same as or different from the material of the bonding film 42. For example, the planarization layer 43 and the bonding film 42 may include the same or different elements selected from Si, O, C, N and H. When the planarization layer 43 and the bonding film 42 include the same element, the atomic percentage of the element in the planarization layer 43 may be the same as or different from the atomic percentage of the corresponding element in the bonding film 42. It can be understood that when the planarization layer 43 and the bonding film 42 are formed of the same material, better bonding can be achieved by planarizing the planarization layer 43 and then forming the bonding film 42 using the selected method (e.g., PEALD) and process conditions discussed above.

[0041] Figure 5A and Figure 5B 2 shows a selective processing process according to some embodiments. Fig.18 As shown, the corresponding process is shown as process 210 in process flow 200. According to an alternative embodiment, the processing process is skipped. Figure 5A , forming a patterned process mask 44. According to some embodiments, the patterned process mask 44 may be or may include a photoresist. The patterned process mask 44 covers some portions of the bonding film 42 while leaving some other portions exposed.

[0042] The selective treatment process 46 is performed to selectively treat the selected portion of the bonding film 42 exposed by the opening in the treatment mask 44. According to some embodiments, the treatment process 46 includes plasma treatment. The process gas used to perform the plasma selective treatment process 46 may include nitrogen (N2), oxygen (O2), argon, etc. or a combination thereof. The treatment time may be less than about 60 seconds, and may be in a range between about 10 seconds and about 60 seconds.

[0043] According to some embodiments, the treatment process 46 is performed using a plasma generated locally from the process gas. The treatment can be performed with an RF power of less than about 100 watts, and can be in a range between about 50 watts and about 100 watts. According to some embodiments, a small bias power is applied, the bias power is less than about 200 watts, for example, between about 0 watts and about 200 watts. According to an alternative embodiment, the treatment process 46 is performed without applying a bias power. According to yet another alternative embodiment, the treatment process 46 is performed using a remote plasma, wherein the plasma is generated in a process chamber separate from the process chamber in which the selective treatment process 46 is performed, and the remote plasma is directed to the process chamber.

[0044] The selective treatment process 46 causes light bombardment on the exposed surface portion of the bonding film 42. Some of the bonds in the bonding film 42 are thus destroyed. The processed portion of the bonding film 42 is referred to as the processed portion 42PT hereinafter, and the unprocessed portion is referred to as the unprocessed portion 42UPT. The processed portion 42PT may not be visually distinguishable from the unprocessed portion 42UPT. Therefore, the pattern of the processed portion 42PT is referred to as an invisible pattern. However, the processed portion 42PT and the unprocessed portion 42UPT can be distinguished from each other using tools such as X-ray photoelectron spectroscopy (XPS), energy dispersive X-ray spectroscopy (EDX), etc.

[0045] Fig. 12A and Fig. 12B Some exemplary device dies 22 and processing portions 42PT therein are shown according to some embodiments. Fig.13 The device die 22 and corresponding wafer 20 are found in. It is understood that the processing portion 42PT can have any suitable pattern, provided that the processing portion 42PT is changing and can change the propagation behavior of the bonding wave as it propagates, as discussed below.

[0046] The processing portion 42PT may be formed into a plurality of rings, and the rings may be equally spaced. Fig. 12A As shown, the processing portion 42PT forms a plurality of square patterns, with outer squares surrounding respective inner squares. Fig. 12B The processing portion 42PT is illustrated as forming a plurality of circles. The processing portion 42PT may have any other shape, including but not limited to a hexagon, an octagon, a triangle, etc. The ring of the processing portion may be a complete ring with no breaks therein, or may be a ring with breaks therein.

[0047] Fig.13 An embodiment in which the processing portion 42PT is formed at the wafer level is shown, which is employed when bonding is performed by wafer-to-wafer bonding. The processing portion 42PT may have any other shape, such as a ring, including but not limited to a rectangle, a loop, a hexagon, an octagon, a triangle, etc., which may be broken or may be a complete ring that is not broken. One or more (or all) of the processing portions 42PT may extend into multiple device dies 22. The breaks in the outer ring may not be aligned to the same radius as the directly adjacent inner ring.

[0048] After the selective processing, the wafer 20 is taken out of the corresponding chamber (vacuum break). The patterned processing mask 44 is then removed, for example, by an etching process. Figure 5A), wherein ammonia water may be used as an etchant. Since some of the bonds in the treated portion 42PT of the bonding film 42 are destroyed in the previous processing process, a dangling bond is formed. These dangling bonds may react with oxygen or moisture in the air to form oxides. As a result, the oxygen atomic percentage OAP of the treated portion 42PT is 42PT Higher than the oxygen atomic percentage OAP in the untreated part 42UPT 42UPT .

[0049] According to some embodiments, the treated portion 42PT has a thickness T3 ( Figure 5A ), which may be less than about 100 angstroms, and may be in a range between about 40 angstroms and about 100 angstroms. In addition, thickness T3 may be equal to, less than, or greater than thickness T1 of bonding film 42. Thus, treated portion 42PT may be completely inside bonding film 42 or may extend to the bottom or to below the bottom of bonding film 42. Portions of conductive features 35 may be processed (or may not be processed).

[0050] Figure 5B FIG. 4 shows a process according to an alternative embodiment. In addition to forming a planarization layer 43, these embodiments are similar to Figure 5A Therefore, the processing portion 42PT may be completely inside the bonding film 42 or may extend to the bottom of the bonding film 42. According to some embodiments, the processing portion 42PT may also extend into the planarization layer 43.

[0051] Figure 6 The structure is shown after processing process 46 has been performed and processing mask 44 has been removed. Figure 6 In FIG. 4 , the planarization layer 43 is shown as a dotted line to indicate that the planarization layer 43 may or may not be formed. The unprocessed portion 42UPT is also shown as a dotted line to indicate that the treatment process 46 may or may not be performed.

[0052] refer to Figure 7 , forming a package assembly 120, and aligning and pre-bonding with the device die 22 in the wafer 20. The various processes are shown as follows Fig.18 Process 212 in process flow 200 is shown. According to some embodiments, package assembly 120 is a device die, an interposer die, a package, etc. Alternatively, package assembly 120 can be a device wafer, an interposer wafer, a reconstituted wafer including a bonded device die, etc. Figure 7 A device die is illustrated.

[0053] In some example embodiments, package component 120 has a structure similar to that of package component 20. The structure and materials of features in package component 120 can be found with reference to similar features in wafer 20, and similar features in package component 120 are indicated by adding the number "1" in front of the reference number of the corresponding feature in wafer 20. For example, the substrate in wafer 20 is indicated as substrate 24, and correspondingly, the substrate in package component 120 is indicated as substrate 124. Package component 120 may include an integrated circuit device 126, an ILD layer 128, a contact plug 130, an interconnect structure 132, a dielectric layer 138, a metal line 134, and a through hole 136. The details of these features may be similar to the corresponding features in wafer 20, and are not repeated here.

[0054] The package component 120 further includes a bonding film 142 on the surface, and the bonding film 142 may or may not be subjected to a selective treatment process to form a treated portion 142PT, the treated portions 142PT being distinguished from each other by the untreated portion 142UPT. If performed, the selective treatment process may also use a process gas selected from the same set of candidate process gases used for the selective treatment process 46.

[0055] During pre-bonding, package assembly 120 is contacted with wafer 20, and pressure is applied to press package assemblies 20 and 120 toward each other. Pre-bonding can be performed at room temperature (between about 20° C. and about 25° C.), or higher temperatures can be used.

[0056] Pre-bonding may start by contacting the center of the package component 120 with the wafer 20. The contact propagates from the contact point to the edges of the package components 20 and 120, and the propagation generates a bonding wave that propagates from the contact point to the wafer 20. As the bonding wave propagates from the contact point to the edge, the air between the package components 20 and 120 is gradually squeezed out, so that no bubbles or moisture are trapped between the package components 20 and 120. If bubbles or moisture are trapped, the corresponding parts of the package components 20 and 120 cannot be bonded, resulting in yield loss.

[0057] By performing a selective treatment process 46 to form alternating treated portions 42PT and untreated portions 42UPT, and / or performing a selective treatment process to form alternating treated portions 142PT and untreated portions 142UPT, the corresponding bonding film 42 (and / or bonding film 142) has different compositions and different properties. The bonding wave passes through the treated portions 42PT / 142PT and the untreated portions 42UPT / 142UPT at different speeds. Therefore, when entering the treated portions, the bonding wave propagation is disrupted and discontinuous. This will eliminate the Joule-Thomson effect, which causes moisture to condense in tiny pockets between the packaging components 20 and 120 and disadvantageously creates tiny non-bonding areas. The Joule-Thomson effect will at least be reduced and may even be eliminated.

[0058] The plurality of package components 120 may be pre-bonded to the wafer 20. After the pre-bonding, an annealing process is performed, for example, to form a Si-O-Si bond between the bonding films 42 and 142 so that the bonding films 42 and 142 are bonded to each other by fusion bonding. Fig.18 As shown, the corresponding process is shown as process 214 in process flow 200. According to some embodiments, the annealing process is performed at a temperature in a range between about 250° C. and about 300° C. According to some embodiments, the annealing duration may be in a range between about 5 minutes and about 30 minutes.

[0059] refer to Fig. 8A , the package component 120 is packaged in the packaging glue 54 (dielectric gap filling area). Fig.18 As shown, each process is shown as process 216 in process flow 200. According to some embodiments, encapsulation glue 54 may include a dielectric liner and a dielectric filling material on the dielectric liner. The dielectric liner may be formed of or include silicon nitride, and the dielectric filling material may include silicon oxide. A planarization process such as a CMP process is performed to make the top surface of encapsulation glue 54 flush with the top surface of package component 120.

[0060] Contact plugs 56 may be formed through package component 120 and electrically connect metal pads 135 in package component 120 to conductive features 35 in wafer 20. The various processes are shown as process 218 in process flow 200, as shown in FIG. Fig.18 The contact plug 56 passes through the bonding films 42 and 142 and may pass through and contact the processed portion 42PT and the unprocessed portion 42UPT. A dielectric isolation ring 57 may be formed to electrically isolate the contact plug 56 from the semiconductor substrate 124.

[0061] A dielectric layer 58 may be formed to cover the contact plugs 56 and the substrate 124. Thus, a reconstructed wafer 60 is formed. A dicing process may then be performed along the scribe lines 50 to saw the reconstructed wafer 60 and form a package 60'. Fig.18 As shown, the corresponding process is shown as process 220 in process flow 200. Each package 60' may include a package component 22 (eg, a device die) bonded to a package component 122 (eg, a device die).

[0062] Figure 8B A reconstituted wafer 60 and a package 60' are shown according to alternative embodiments. These embodiments are similar to Fig. 8A , except that the planarization layer 43 is formed according to these embodiments.

[0063] It should be understood that Figures 1 to 8A and Figure 8B The bonding of the device chip to the device wafer shown is an example, and a thin bonding film may be used to bond other package components. Fig. 9 FIG. 4 shows a package in which a package component 420 is bonded to a package component 320, which is a carrier according to some embodiments. The formation of the bonding film 42 and the optional processing portion 42PT in the carrier 320 is similar to Figure 4A and Figure 5A According to an alternative embodiment, the bonding film 42 is not formed, and the bonding film 42 is directly bonded to the silicon in the silicon wafer 322 .

[0064] According to some embodiments, the carrier 320 includes a crystalline silicon wafer 322. The bonding film 42 is formed on the silicon wafer 322. The carrier 320 may have roughness Ra and Rq values ​​less than about 1 angstrom when supplied, and therefore no planarization process is performed on the silicon wafer 322. Alternatively, if the roughness Ra and Rq values ​​of the silicon wafer 322 are greater than 1 angstrom, the silicon wafer 322 may be further planarized to have roughness Ra and Rq values ​​less than about 1 angstrom.

[0065] The packaging component 420 may be a chip cut from a device wafer, a reconstructed wafer, or the like. For example, in the example shown, the packaging component 420 is a reconstructed wafer, including a device die 440 encapsulated in a gap-filling region 442 and a device die 444 encapsulated in a gap-filling region 446. A bonding film 142 is formed as a surface layer of the packaging component 420. The details of the bonding film 142 may be substantially the same as the details of the bonding film 42 discussed in the aforementioned embodiment, and are not repeated here. A planarization layer 443 may or may not be formed. The details of the planarization layer 443 may be substantially the same as those of the planarization layer 43, and are not repeated here. After bonding the packaging components 420 and 320, the resulting reconstructed wafer 82 is sawn into a plurality of packages, one of which is a package 82'. Fig. 9 shown.

[0066] According to some embodiments, in Fig. 9 In the package shown, the remaining silicon chip 322' of the silicon wafer 322 is used as a heat sink. For example, a fan 80 is shown as a heat dissipation mechanism of the package 82. Heat is dissipated from the die in the package assembly 420 to the silicon chip 322' and is dissipated. The heat dissipation efficiency is related to the thickness and material of the planarization layer 443 (if formed) and the bonding film 42 and the bonding film 142. The thermal resistance of the device die 440 / 444 to the silicon chip 322' is proportional to the thickness T4 of the material between them. Therefore, by thinning the bonding films 42 and 142, the thermal resistance is reduced. The heat dissipation from the heat-generating device die 440 and 444 to the silicon chip 322' is improved.

[0067] Fig.10 An example of wafer-to-wafer bonding is shown, where a reconstructed wafer 420' including a device die 450, a gap-filling region 448, and a device wafer 20' is bonded to a device wafer 20 (device wafer 20 is another device wafer). Bonding is performed through thin bonding films 42 and 142, which may be processed (in a selective processing process 46) or unprocessed. A planarization layer 143 may be formed, or may be skipped.

[0068] Fig.11 An example of chip-to-chip bonding is shown, where chip 22 is bonded to chip 122. Bonding is performed through thin bonding films 42 and 142, which may be treated or untreated. A planarization layer 143 may be formed, or may be omitted.

[0069] As described above, the selective treatment results in the treated portion having a composition different from the composition of the untreated portion. Oxygen atomic percentage OAP of the treated portion 42PT 42PT The oxygen atomic percentage OAP can be higher than 42UPT of the untreated part 42UPT Difference (oxygen atomic percentage OAP 42PT -Oxygen atomic percentage OAP42UPT ) may be greater than about 2%, and may be in a range between about 2% and about 10%.

[0070] Fig.14 The schematic diagram shows the oxygen atomic percentage in the treated portion 42PT as a function of its position. The surface portion of the bonding film 42 is also Fig.14 The positions corresponding to the treated portion 42PT and the untreated portion 42UPT and their oxygen atomic percentages are shown in FIG. Fig.14 Line 90 representing atomic percent oxygen is illustrated. Fig.14 It is shown that the oxygen atomic percentage in the treated portion 42PT is higher than the oxygen atomic percentage in the untreated portion 42UPT.

[0071] Fig.15 Schematically illustrates the oxygen atomic percentage in the treated portion 42PT and the untreated portion as a function of its depth into the bonding film 42. The symbol "43 / 39 / 35" represents the planarization layer 43, or the conductive feature 35 and the dielectric layer 39. The X-axis represents Fig.14 62 and 63. Line 94 represents the oxygen atomic percentage along the path of arrow 62, and line 96 represents the oxygen atomic percentage along the path of arrow 63. It shows that the treated portion 42PT can have a higher oxygen atomic percentage, while the untreated portion 42UPT has a lower atomic percentage. XPS, EDX, etc. can be used to find the difference in composition.

[0072] Embodiments of the present disclosure have some advantageous features. By thinning the bonding film, the thermal resistance in the heat dissipation path can be reduced. For example, by reducing the thickness of the bonding film and the planarization layer, the thermal resistance can be reduced by about 85%. Reducing the thickness of the bonding film also makes the roughness of the bonding film low, allowing bonding with high bonding strength without the need to planarize the bonding film. By using PEALD with controlled process conditions, the number of OH groups on the surface of the bonding film is increased, thereby further improving the bonding strength. The bonding quality can be further improved by selectively treating some but not all parts of the bonding film.

[0073] According to some embodiments of the present disclosure, a method for forming a package includes: forming a feature for a first package component, wherein forming the feature includes a planarization process to make the top surface of the feature flush; depositing a silicon-containing dielectric layer above the feature and the silicon-containing dielectric layer is in contact with the feature, and the feature serves as a surface feature of the first package component; and bonding a second package component to the silicon-containing dielectric layer by fusion bonding, wherein the silicon-containing dielectric layer has the same thickness in the two steps of depositing and bonding.

[0074] In some embodiments, the silicon-containing dielectric layer is deposited using a plasma enhanced atomic layer deposition process. In some embodiments, the plasma enhanced atomic layer deposition process has a flow rate ratio (N2O+N2) / (N2O+N2+O2) greater than about 0.2. In some embodiments, the same thickness of the silicon-containing dielectric layer is less than about 100 angstroms. In some embodiments, the same thickness of the silicon-containing dielectric layer is less than about 50 angstroms. In some embodiments, the silicon-containing dielectric layer has a roughness value less than about 1 angstrom. In some embodiments, the first portion of the silicon-containing dielectric layer is selectively treated and a second portion of the silicon-containing dielectric layer is left untreated. In some embodiments, the first portion and the second portion are alternately positioned.

[0075] In some embodiments, the selective treatment has a treatment depth greater than the same thickness of the silicon-containing dielectric layer. In some embodiments, the selective treatment includes: forming a treatment mask over the silicon-containing dielectric layer; patterning the treatment mask to expose the first portion of the silicon-containing dielectric layer while the second portion is covered by the treatment mask; performing a plasma treatment process on the first portion of the silicon-containing dielectric layer; and removing the treatment mask. In some embodiments, forming the feature includes: depositing a conductive material into an opening in an additional dielectric layer; performing the planarization process to level a first top surface of the conductive material with a second top surface of the additional dielectric layer.

[0076] According to some embodiments of the present disclosure, a packaging structure includes: a first packaging component, including: a dielectric layer including a top surface; a silicon-containing dielectric layer located above and contacting the dielectric layer, wherein the silicon-containing dielectric layer has a first thickness less than about 100 angstroms; and a second packaging component, bonded to the silicon-containing dielectric layer by fusion bonding.

[0077] In some embodiments, wherein the first thickness is less than about 50 angstroms. In some embodiments, wherein there are no conductive features in the dielectric layer. In some embodiments, wherein the second package component comprises a silicon substrate, and wherein the silicon substrate is in physical contact with the silicon-containing dielectric layer. In some embodiments, wherein the dielectric layer and the silicon-containing dielectric layer together comprise: a first portion extending from an additional top surface of the silicon-containing dielectric layer into the dielectric layer, wherein the first portion has a first oxygen atomic percentage; and a second portion separated from the first portion, wherein the second portion has a second oxygen atomic percentage less than the first oxygen atomic percentage. In some embodiments, wherein the first portion extends to a bottom surface of the silicon-containing dielectric layer. In some embodiments, wherein the first portion and the second portion are alternately positioned.

[0078] According to some embodiments of the present disclosure, a package structure includes: a device die, including: a first semiconductor substrate; a dielectric layer; a conductive feature located in the dielectric layer; a first bonding film located above the dielectric layer and the conductive feature and in physical contact with the dielectric layer and the conductive feature, wherein the first bonding film has a thickness of less than about 50 angstroms; and a second package, including: a second bonding film bonded to the first bonding film; and a second semiconductor substrate located above the second bonding film. In some embodiments, the second semiconductor substrate is in physical contact with the second bonding film.

[0079] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art can better understand the aspects of the present invention. Those of ordinary skill in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and those of ordinary skill in the art can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A packaging structure, characterized in that: include: The first packaging component comprises: a dielectric layer including a top surface; a silicon-containing dielectric layer overlying and contacting the dielectric layer, wherein the silicon-containing dielectric layer has a first thickness of less than 100 angstroms; and The second packaging component is bonded to the silicon-containing dielectric layer of the first packaging component.

2. The packaging structure according to claim 1, characterized in that: The first thickness is less than 50 angstroms.

3. The packaging structure according to claim 1, characterized in that: The dielectric layer has no conductive features therein.

4. The packaging structure according to claim 1, characterized in that: The second packaging component includes a silicon substrate, and wherein the silicon substrate is in physical contact with the silicon-containing dielectric layer.

5. The packaging structure according to claim 1, characterized in that: The dielectric layer and the silicon-containing dielectric layer together include: a plurality of first portions extending from an additional top surface of the silicon-containing dielectric layer into the dielectric layer; and A plurality of second portions separate the plurality of first portions from each other, wherein the plurality of second portions are different from the plurality of first portions.

6. The packaging structure according to claim 5, characterized in that: The plurality of first portions extend to a bottom surface of the silicon-containing dielectric layer.

7. The packaging structure according to claim 5, characterized in that: The plurality of first portions and the plurality of second portions are positioned alternately.

8. The packaging structure according to claim 1, characterized in that: The silicon-containing dielectric layer has a roughness value of less than 1 angstrom.

9. A packaging structure, characterized in that: include: A device die, comprising: a first semiconductor substrate; Dielectric layer; a conductive feature located in the dielectric layer; a first bonding film located above and in physical contact with the dielectric layer and the conductive features, wherein the first bonding film has a thickness of less than 100 angstroms; and The second package includes: a second bonding film bonded to the first bonding film; and The second semiconductor substrate is located above the second bonding film.

10. The packaging structure according to claim 9, characterized in that: The second semiconductor substrate is in physical contact with the second bonding film.

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