Semiconductor test structure

Abstract

The embodiment of the utility model provides a semiconductor test structure. The semiconductor test structure comprises a test transistor. The test transistor includes: a gate structure over the active region and extending in a first direction; the source electrode structure and the drain electrode structure are located in the active region and located on the two sides of the orthographic projection of the gate electrode structure on the active region respectively; each of the source electrode structure and the drain electrode structure comprises a plurality of conductive regions and a plurality of isolation regions; the conductive regions and the isolation regions of the source electrode structure are alternately arranged in rows along a first direction; the conductive regions and the isolation regions of the drain electrode structure are alternately arranged in rows along a first direction; the conductive region, located at the tail end of one side in the first direction and close to the shallow trench isolation structure, in the source electrode structure forms a test source electrode, the conductive region, located at the tail end of one side in the first direction and close to the shallow trench isolation structure, in the drain electrode structure forms a test drain electrode, and the test source electrode and the test drain electrode are located at the tail end of the same side in the first direction. The method is used for accurately monitoring the electric leakage phenomenon at the junction of the active area and the STI.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor test structure. Background Art

[0002] The Shallow Trench Isolation (STI) process achieves isolation between active regions of devices by embedding oxide in substrate trenches. In metal oxide semiconductor (MOS) transistors, parasitic MOS is easily present at the junction of the active region and the STI structure, resulting in high subthreshold leakage of the transistor.

[0003] In the test based on the existing conventional semiconductor test structure, it is usually judged whether there is leakage in the transistor by observing the double hump phenomenon in the transfer characteristic curve (IDVG curve) of the transistor. However, the existing test method is difficult to accurately judge whether there is parasitic MOS at the junction of the active area and the STI structure of the transistor, and to accurately monitor the leakage phenomenon at the junction of the active area and the STI structure. Utility Model Content

[0004] Based on this, it is necessary to provide a semiconductor test structure for accurately monitoring the leakage phenomenon at the junction of the active region and the STI structure in order to solve the above technical problems.

[0005] Some embodiments of the present disclosure provide a semiconductor test structure, including: a substrate and a test transistor. The substrate has a first doping type well region, and a shallow trench isolation structure arranged in a ring shape in the first doping type well region; the first doping type well region in the shallow trench isolation structure ring constitutes an active region. The test transistor includes a gate structure, a source structure and a drain structure. The gate structure is located above the active region and extends along a first direction; the source structure and the drain structure are located in the active region and are respectively located on both sides of the positive projection of the gate structure on the active region. Among them, the source structure and the drain structure both include a plurality of conductive regions and a plurality of isolation regions; the conductive regions and the isolation regions of the source structure are alternately arranged in a row along the first direction; the conductive regions and the isolation regions of the drain structure are alternately arranged in a row along the first direction. The conductive region in the source structure located at the end of one side of the first direction and close to the shallow trench isolation structure constitutes a test source, and the conductive region in the drain structure located at the end of one side of the first direction and close to the shallow trench isolation structure constitutes a test drain, and the test source and the test drain are located at the end of the same side of the first direction.

[0006] In some embodiments, the conductive region is a second type doping region, and the isolation region is a first type doping region.

[0007] In some other embodiments, the conductive region is a second type doped region, and the isolation region is a shallow trench isolation region.

[0008] In some embodiments, the conductive regions in the same source structure are arranged at equal intervals in the first direction; and the conductive regions in the same drain structure are arranged at equal intervals in the first direction.

[0009] In some embodiments, the semiconductor test structure further includes a common electrode. The common electrode is arranged in a ring shape on the outer side of the shallow trench isolation structure away from the active area.

[0010] In some embodiments, the common electrode includes a first type doped region.

[0011] In some embodiments, the gate structure includes a polysilicon gate; the gate structure extends from above the active region to above the shallow trench isolation structure.

[0012] In some embodiments, the semiconductor test structure further includes a source lead-out electrode, a drain lead-out electrode, and a gate lead-out electrode. The source lead-out electrode is electrically connected to the test source; the drain lead-out electrode is electrically connected to the test drain; the gate lead-out electrode is located beside the test source and the test drain, and is arranged at the end of the gate structure extending to the shallow trench isolation structure.

[0013] In some embodiments, the semiconductor test structure further includes a source contact layer and a drain contact layer. The source contact layer is located between the test source and the source lead-out electrode, and is electrically connected to the test source and the source lead-out electrode; the drain contact layer is located between the test drain and the drain lead-out electrode, and is electrically connected to the test drain and the drain lead-out electrode.

[0014] In some embodiments, the source contact layer and / or the drain contact layer includes a metal silicide layer.

[0015] In the above embodiments of the present disclosure, the source structure and the drain structure both include a plurality of conductive regions and a plurality of isolation regions, and the conductive regions and the isolation regions of the source structure are alternately arranged in rows along the first direction, and the conductive regions and the isolation regions of the drain structure are alternately arranged in rows along the first direction; that is, the above semiconductor test structure can alternately set isolation regions and conductive regions in the source structure and the drain structure, respectively, so as to divide the source structure and the drain structure into a plurality of mutually isolated conductive regions. In this way, the conductive region of the source structure located at the end of one side of the first direction and close to the shallow trench isolation structure can constitute a test source, and the conductive region of the drain structure located at the end of one side of the first direction and close to the shallow trench isolation structure can constitute a test drain, and at the same time, the test source and the test drain are located at the ends of the same side of the first direction, so as to accurately monitor the leakage phenomenon at the junction of the active area (AA) and the STI structure.

[0016] In this way, the unexpected effect that can be achieved by the semiconductor test structure provided by the embodiment of the present disclosure is: when performing relevant test stages (such as wafer acceptance testing), the test source and test drain located at the ends on the same side of the first direction and close to the shallow trench isolation structure (i.e., close to the junction between the active area and the STI structure) can be lead out for testing to directly monitor the leakage phenomenon at the junction between the active area and the STI structure; therefore, the above-mentioned semiconductor test structure can directly and accurately monitor the leakage phenomenon at the junction between the active area and the STI structure through a simple testing method, which is beneficial to improving the accuracy and efficiency of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic structural diagram of a semiconductor test structure provided in some embodiments;

[0019] Figure 2 for Figure 1 A schematic cross-sectional structure diagram of a semiconductor test structure along the AA' direction is shown;

[0020] Figure 3 for Figure 1 A schematic cross-sectional structure diagram of the semiconductor test structure shown along the BB' direction;

[0021] Figure 4 A curve diagram showing a change in leakage current versus gate-source voltage obtained from a semiconductor test structure provided in some embodiments;

[0022] Figure 5 A schematic structural diagram of another semiconductor test structure provided in some embodiments;

[0023] Figure 6 for Figure 5 The cross-sectional structure diagram of the semiconductor test structure along the BB' direction is shown.

[0024] Description of reference numerals:

[0025] 1-substrate, 11-first doping type well region, 111-active region, G-ring trench, 12-shallow trench isolation structure, 2-test transistor, 21-gate structure, 21A-gate lead electrode, 22-source structure, 221-test source, 22A-source lead electrode, 22B-source contact layer, 23-drain structure, 231-test drain, 23A-drain lead electrode, 23B-drain contact layer, R1-conductive region, R2-isolation region, 3-common electrode, 3A-common electrode lead electrode, 3B-common electrode contact layer, Id-drain current, Vgs-gate-source voltage. DETAILED DESCRIPTION

[0026] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0028] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0029] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0030] The Shallow Trench Isolation (STI) process achieves isolation between device active areas by embedding oxide in substrate trenches. The STI process can not only solve the bird's beak effect and white band effect inherent in the Local Oxidation of Silicon (LOCOS) process, but also can greatly improve the parasitic field effect transistor effect and latch-up effect.

[0031] In a metal oxide semiconductor (MOS) transistor, in order to ensure that the polysilicon gate can completely control the channel between the source structure and the drain structure, the polysilicon gate is usually extended above the shallow trench isolation structure. However, if the corner of the substrate trench in the direction perpendicular to the substrate that is away from the substrate is too sharp (for example, less than 90 degrees), it is easy to cause an inversion layer to form at the side wall of the substrate trench (for example, at the junction of the shallow trench isolation structure and the active area) when the transistor is working, resulting in a larger subthreshold leakage of the device; in addition, as the oxide layer in the shallow trench isolation structure is continuously consumed in the subsequent process of preparing the semiconductor structure, if the surface of the oxide layer at the junction of the shallow trench isolation structure and the active area away from the substrate is lower than the surface of the active area away from the substrate, it will also cause a larger subthreshold leakage of the device, and in severe cases, it may even cause the polysilicon gate to remain at the edge of the active area, causing the device to short-circuit.

[0032] Based on this, some embodiments of the present disclosure provide a semiconductor test structure for accurately monitoring leakage phenomena at the interface between an active region and an STI structure.

[0033] In some embodiments, see Figure 1 to Figure 3 , the semiconductor test structure includes: a substrate 1 and a test transistor 2. The substrate 1 has a first doping type well region 11, and a shallow trench isolation structure 12 arranged in a ring shape in the first doping type well region 11; the first doping type well region 11 in the ring of the shallow trench isolation structure 12 constitutes an active region 111. The test transistor 2 includes a gate structure 21, a source structure 22 and a drain structure 23. The gate structure 21 is located above the active region 111 and extends along a first direction (for example, the X direction); the source structure 22 and the drain structure 23 are located in the active region 111 and are respectively located on both sides of the positive projection of the gate structure 21 on the active region 111. Among them, the source structure 22 and the drain structure 23 each include a plurality of conductive regions R1 and a plurality of isolation regions R2; the conductive regions R1 and the isolation regions R2 of the source structure 22 are alternately arranged in rows along the first direction (for example, the X direction); the conductive regions R1 and the isolation regions R2 of the drain structure 23 are alternately arranged in rows along the first direction (for example, the X direction).

[0034] Please continue reading Figure 1 to Figure 3The conductive region R1 in the source structure 22 located at the end of one side in the first direction (for example, the X direction) and close to the shallow trench isolation structure 12 constitutes a test source 221, and the conductive region R1 in the drain structure 23 located at the end of one side in the first direction (for example, the X direction) and close to the shallow trench isolation structure 12 constitutes a test drain 231. The test source 221 and the test drain 231 are located at the ends on the same side of the first direction (for example, the X direction).

[0035] In the embodiment of the present disclosure, the conductive region R1 in the source structure 22 and the drain structure 23 is divided into a plurality of mutually isolated regions by a plurality of isolation regions R2; and the conductive region R1 in the source structure 22 located at the end of one side in the first direction (e.g., the X direction) and close to the shallow trench isolation structure 12 can constitute a test source 221, and the conductive region R1 in the drain structure 23 located at the end of one side in the first direction (e.g., the X direction) and close to the shallow trench isolation structure 12 can constitute a test drain 231, and at the same time, the test source 221 and the test drain 231 are located at the ends on the same side of the first direction (e.g., the X direction). In this way, when performing relevant test phases (such as wafer acceptance testing), the test source 221 and the test drain 231 located at the ends of the same side of the first direction (such as the X direction) and close to the end of the shallow trench isolation structure 12 (i.e., close to the junction of the active area 111 and the shallow trench isolation structure 12) can be led out for testing, so as to directly and accurately monitor the leakage phenomenon at the junction of the active area 111 and the shallow trench isolation structure 12, thereby improving the accuracy of the test and facilitating the improvement of the test efficiency.

[0036] It should be noted that the semiconductor test structure in the embodiment of the present disclosure may be, for example, a power metal oxide semiconductor (Power Metal Oxide Semiconductor, Power MOS for short) test structure.

[0037] For example, the material of the substrate 1 can be any suitable substrate 1 material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

[0038] By way of example, the first doping type well region 11 may be an N-type well region or a P-type well region.

[0039] For some examples, see Figure 1 to Figure 3 The substrate 1 also has an annular trench G, which is arranged in the first doping type well region 11; the shallow trench isolation structure 12 is formed by the annular trench G and an insulating medium filled in the annular trench G.

[0040] For some examples, see Figure 2 and Figure 3 , the annular trench G does not penetrate the first doping type well region 11 of the substrate 1 .

[0041] For example, the depth of the annular groove G (ie, the dimension in the direction perpendicular to the substrate) may be 2 μm, 3 μm, 4 μm or 5 μm. The depth of the annular groove G (ie, the dimension in the direction perpendicular to the substrate) is, for example, 3 μm.

[0042] For example, the shape of the annular groove G includes but is not limited to a rectangular ring, a circular ring, an elliptical ring, etc.

[0043] In some examples, the gate structure 21 includes a polysilicon gate; Figure 1 As shown, the gate structure 21 extends from above the active region 111 to above the shallow trench isolation structure 12 .

[0044] In some examples, there is a gate dielectric layer between the gate structure 21 and the active region 111, and the gate dielectric layer includes an oxide layer. For example, the material of the gate dielectric layer may be silicon dioxide (SiO2).

[0045] In some embodiments, see Figure 1 to Figure 3 The semiconductor test structure further includes a source lead electrode 22A, a drain lead electrode 23A and a gate lead electrode 21A. The source lead electrode 22A is electrically connected to the test source 221. The drain lead electrode 23A is electrically connected to the test drain 231. The gate lead electrode 21A is located beside the test source 221 and the test drain 231, and is disposed at the end of the gate structure 21 extending to the shallow trench isolation structure 12.

[0046] For example, the source lead electrode 22A, the drain lead electrode 23A and the gate lead electrode 21A may be formed of conductive pillars or conductive interconnect structures including conductive pillars, such as conductive pillars and metal wires. The conductive pillars may be formed of metal materials, for example.

[0047] By way of example, the orthographic projection of the gate extraction electrode 21A on the substrate 1 is located outside the active region 111 .

[0048] It should be noted that the semiconductor test structure provided in the embodiment of the present disclosure can connect the gate structure 21, the source structure 22 and the drain structure 23 through the gate lead electrode 21A, the source lead electrode 22A and the drain lead electrode 23A to achieve testing of the electrical characteristics of the test transistor 2.

[0049] For some possible implementations, please continue to refer to Figure 1 to Figure 3 , the conductive region R1 is a second type doping region, and the isolation region R2 is a first type doping region.

[0050] For example, the first type doping region and the first doping type well region 11 have the same conductivity type, and the second type doping region and the first doping type well region 11 have different conductivity types. Also, the first type doping region and the first doping type well region 11 may have different ion doping concentrations.

[0051] For example, the first doping type well region 11 is a P-type well region, the first type doping region is a P-type doping region (P+), the ion doping concentration of the first type doping region is higher than the ion doping concentration of the first doping type well region, and the second type doping region is an N-type doping region (N+).

[0052] In some embodiments, see Figure 1 , the conductive regions R1 in the same source structure 22 are arranged at equal intervals in the first direction (eg, X direction); the conductive regions R1 in the same drain structure 23 are arranged at equal intervals in the first direction (eg, X direction).

[0053] In some examples, each conductive region R1 in the source structure 22 corresponds to each conductive region R1 in the drain structure 23 .

[0054] In some embodiments, see Figure 1 to Figure 3 The semiconductor test structure further includes a common electrode 3. The common electrode 3 is arranged in a ring shape on the outer side of the shallow trench isolation structure 12 away from the active area 111.

[0055] For some examples, see Figure 2 and Figure 3 , the common electrode 3 can be arranged in the first doping type well region 11 .

[0056] In some embodiments, the common electrode 3 includes a first type doping region (for example, a P-type doping region). It can be understood that when the common electrode 3 is formed by the first type doping region, the ion doping concentration of the common electrode 3 corresponding to the first type doping region is different from the ion doping concentration when the isolation region R2 is the first type doping region, for example: the ion doping concentration of the common electrode 3 corresponding to the first type doping region is greater than the ion doping concentration when the isolation region R2 is the first type doping region.

[0057] In some embodiments, please refer to Figure 1 to Figure 3 The semiconductor test structure further includes a plurality of common electrode lead-out electrodes 3A. The plurality of common electrode lead-out electrodes 3A are located on the surface of the common electrode 3 away from the substrate 1 and are electrically connected to the common electrode 3 and are arranged in a ring shape with equal intervals along the common electrode 3 .

[0058] For example, the common electrode lead-out electrode 3A may be a conductive column or a conductive interconnect structure including a conductive column, for example, it may be composed of a conductive column and a metal lead. The conductive column may be composed of a metal material, for example.

[0059] In some embodiments, see Figure 2 and Figure 3 The semiconductor test structure further includes a source contact layer 22B and a drain contact layer 23B. The source contact layer 22B is located between the test source 221 and the source lead-out electrode 22A, and is electrically connected to the test source 221 and the source lead-out electrode 22A; the drain contact layer 23B is located between the test drain 231 and the drain lead-out electrode 23A, and is electrically connected to the test drain 231 and the drain lead-out electrode 23A.

[0060] For some examples, see Figure 2 and Figure 3 The semiconductor test structure further includes a common electrode contact layer 3B. The common electrode contact layer 3B is located between the common electrode 3 and the common electrode lead-out electrode 3A, and is electrically connected to the common electrode 3 and the common electrode lead-out electrode 3A.

[0061] In some embodiments, the source contact layer 22B, the drain contact layer 23B, and / or the common electrode contact layer 3B include a metal silicide layer.

[0062] By way of example, the material of the source contact layer 22B, the drain contact layer 23B and / or the common electrode contact layer 3B may be cobalt silicide (CoSi).

[0063] In the embodiment of the present disclosure, by providing a source contact layer 22B, a drain contact layer 23B and a common electrode contact layer 3B, the contact resistance between the test source 221 and the source lead-out electrode 22A, between the test drain 231 and the drain lead-out electrode 23A, and between the common electrode 3 and the common electrode lead-out electrode 3A can be effectively reduced, thereby facilitating the improvement of the accuracy of the test results, so as to achieve accurate monitoring of leakage phenomena at the junction of the active area 111 and the shallow trench isolation structure 12.

[0064] Based on the above, the following embodiments are provided in some embodiments of the present disclosure: Figure 1 to Figure 3 When the semiconductor test structure shown is tested (eg, wafer acceptance test), it can be accurately determined whether there is leakage at the interface between the active region 111 and the shallow trench isolation structure 12 based on the leakage current Id between the test source 221 and the test drain 231 .

[0065] For the above semiconductor test structure, the following test method can be used for wafer acceptance test:

[0066] It should be noted that the following examples take a semiconductor test structure as a power metal oxide semiconductor (Power Metal Oxide Semiconductor, Power MOS for short) test structure with a threshold voltage of 0.8V as an example.

[0067] See also Figure 4 , apply a positive gate voltage Vg to the gate lead electrode 21A, and apply a drain voltage Vd to the drain lead electrode 23A, wherein the drain voltage Vd is a positive constant voltage; the source lead electrode 22A and the common electrode lead electrode 3A are grounded, that is, the source voltage Vs is zero; at this time, the current path flows from the test drain 231 to the test source 221, and the source lead electrode 22A can be used as a current reading terminal to read the leakage current Id. For example, with the difference between the gate voltage Vg and the source voltage Vs (that is, the gate-source voltage Vgs) as the horizontal coordinate, the variation curve of the leakage current Id of the semiconductor test structure with the gate-source voltage Vgs can be obtained as shown in Figure 4 As shown in curve A.

[0068] In addition, in order to accurately detect the leakage phenomenon of the power metal oxide semiconductor, the conventional test structure corresponding to the power metal oxide semiconductor can be used as a reference, and the same test can be performed on the conventional test structure to obtain a change curve of the leakage current Id with the gate-source voltage Vgs when the drain-source voltage Vds is used as a parameter (i.e., a transfer characteristic curve) as shown in FIG. Figure 4 As shown in the middle curve B.

[0069] From the above, by comparing curve A and curve B, it can be seen that when the gate-source voltage Vgs is 0.2V, the leakage current Id-A that can be measured by the semiconductor test structure of the embodiment of the present disclosure is significantly greater than the leakage current Id-B that can be measured by the conventional test structure under the same gate-source voltage Vgs, for example, it can reach two or more orders of magnitude. It can be seen that when the semiconductor test structure provided in the embodiment of the present disclosure performs wafer acceptance testing, more obvious and more analytical test results can be obtained, which is conducive to realizing batch testing to effectively improve test efficiency.

[0070] For other possible implementations, please continue to refer to Figure 5 and Figure 6 , the conductive region R1 is a second type doping region, and the isolation region R2 is a shallow trench isolation region.

[0071] By way of example, the shallow trench isolation region is formed by an isolation trench and an insulating medium filled in the isolation trench.

[0072] For example, the shallow trench isolation region and the shallow trench isolation structure 12 can be formed simultaneously to fill the insulating medium with the same material. The insulating medium can be, for example, silicon dioxide (SiO2), but is not limited thereto.

[0073] It should be noted that the annular trench G of the isolation trench and the shallow trench isolation structure 12 can be formed based on the mask pattern of the same mask plate, so that the insulating medium is simultaneously filled in the isolation trench and the annular trench G to form the shallow trench isolation region and the shallow trench isolation structure 12. In this way, the shallow trench isolation region and the shallow trench isolation structure 12 can be formed by defining the mask plate once, without adding a new mask plate, saving costs and having a high process efficiency.

[0074] Based on the above, the following embodiments are provided in some embodiments of the present disclosure: Figure 5 and Figure 6 When the semiconductor test structure shown is tested (eg, wafer acceptance test), it can be accurately determined whether there is leakage at the interface between the active region 111 and the shallow trench isolation structure 12 based on the leakage current Id between the test source 221 and the test drain 231 .

[0075] It is worth mentioning that for Figure 5 and Figure 6 The semiconductor test structure shown can be used to perform wafer acceptance test using the same test method as in some of the aforementioned embodiments. Figure 5 and Figure 6 In the semiconductor test structure shown in FIG. 1 , the isolation region R2 is a shallow trench isolation region, and the isolation effect of the shallow trench isolation region on the adjacent conductive region R1 can be significantly better than the isolation effect when the isolation region R2 is a first type doping region. Therefore, in the semiconductor test structure (such as FIG. 1 ) with the shallow trench isolation region as the isolation region R2 Figure 5 and Figure 6 When a test (such as a wafer acceptance test) is performed, the semiconductor test structure can have a more obvious and easier to analyze test result, so as to further facilitate batch testing and effectively improve test efficiency.

[0076] In summary, the unexpected effect that can be achieved by the semiconductor test structure provided by the embodiment of the present disclosure is: when performing relevant test stages (such as wafer acceptance testing), the test source and the test drain located at the end on the same side of the first direction and close to the shallow trench isolation structure (that is, close to the junction of the active area and the STI structure) can be lead out for testing to directly monitor the leakage phenomenon at the junction of the active area and the STI structure; therefore, the above-mentioned semiconductor test structure can directly and accurately monitor the leakage phenomenon at the junction of the active area and the STI structure through a simple testing method, which is beneficial to improving the accuracy and efficiency of the test.

[0077] In the description of this specification, the descriptions with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc., mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0078] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A semiconductor test structure, characterized in that: include: A substrate having a first doping type well region and a shallow trench isolation structure arranged in a ring shape in the first doping type well region; The first doping type well region within the shallow trench isolation structure ring constitutes an active region; Testing transistors, including: A gate structure, located above the active area and extending along a first direction; A source structure and a drain structure, located in the active area and respectively located on two sides of the orthographic projection of the gate structure on the active area; Wherein, the source structure and the drain structure each include a plurality of conductive regions and a plurality of isolation regions; the conductive regions and the isolation regions of the source structure are alternately arranged in rows along the first direction; the conductive regions and the isolation regions of the drain structure are alternately arranged in rows along the first direction; A conductive area in the source structure located at one end of the first direction and close to the shallow trench isolation structure constitutes a test source, and a conductive area in the drain structure located at one end of the first direction and close to the shallow trench isolation structure constitutes a test drain. The test source and the test drain are located at the ends on the same side of the first direction.

2. The semiconductor test structure according to claim 1, characterized in that: The conductive region is a second type doping region, and the isolation region is a first type doping region.

3. The semiconductor test structure according to claim 1, characterized in that: The conductive region is a second type doping region, and the isolation region is a shallow trench isolation region.

4. The semiconductor test structure according to claim 1, characterized in that: The conductive regions in the same source structure are arranged at equal intervals in the first direction; The conductive regions in the same drain structure are arranged at equal intervals in the first direction.

5. The semiconductor test structure according to claim 1, characterized in that: Also includes: The common electrode is arranged in a ring shape on the outer side of the shallow trench isolation structure away from the active area.

6. The semiconductor test structure according to claim 5, characterized in that: The common electrode includes a first type doping region.

7. The semiconductor test structure according to claim 1, characterized in that: The gate structure includes a polysilicon gate; the gate structure extends from above the active area to above the shallow trench isolation structure.

8. The semiconductor test structure according to any one of claims 1 to 7, characterized in that: Also includes: A source lead-out electrode electrically connected to the test source; A drain lead-out electrode electrically connected to the test drain; The gate lead-out electrode is located beside the test source and the test drain, and is arranged at the end of the gate structure extending to the shallow trench isolation structure.

9. The semiconductor test structure according to claim 8, characterized in that: Also includes: A source contact layer, located between the test source and the source lead-out electrode, and electrically connected to the test source and the source lead-out electrode; The drain contact layer is located between the test drain and the drain lead-out electrode, and is electrically connected to the test drain and the drain lead-out electrode.

10. The semiconductor test structure according to claim 9, characterized in that: The source contact layer and / or the drain contact layer includes: a metal silicide layer.

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