Semiconductor structure

Abstract

The utility model provides a semiconductor structure. The semiconductor structure includes a wafer circuit structure, at least one first semiconductor die, at least one first support structure, and an encapsulation. The at least one first semiconductor die is disposed over and electrically connected to the wafer circuit structure in a device region of the semiconductor structure. The at least one first support structure is disposed over the wafer circuit structure in the peripheral region of the semiconductor structure. The encapsulation body is disposed over the wafer circuit structure and encapsulates the at least one first semiconductor die and the at least one first support structure, wherein a thickness of the encapsulation body at an edge of the semiconductor structure is less than a thickness of the encapsulation body within a device region of the semiconductor structure.

Description

Technical Field

[0001] The utility model relates to a semiconductor structure. Background Art

[0002] Advances in reducing the size of semiconductor devices and electronic components have made it possible to integrate more devices and components into a given volume and achieve high integration densities of various semiconductor devices and / or electronic components. Utility Model Content

[0003] The utility model provides a semiconductor structure, comprising: a chip circuit structure; at least one first semiconductor die, which is arranged on the chip circuit structure in a device area of ​​the semiconductor structure and electrically connected to the chip circuit structure; at least one first supporting structure, which is arranged on the chip circuit structure in a peripheral area of ​​the semiconductor structure; and an encapsulation body, which is arranged on the chip circuit structure and encapsulates the at least one first semiconductor die and the at least one first supporting structure, wherein the thickness of the encapsulation body at the edge of the semiconductor structure is less than the thickness of the encapsulation body in the device area of ​​the semiconductor structure.

[0004] The utility model provides a semiconductor structure, comprising: a chip circuit structure; at least one first semiconductor tube core, which is arranged on the chip circuit structure in a device area of ​​the semiconductor structure and is electrically connected to the chip circuit structure; a plurality of support structures, which are arranged on the chip circuit structure in a peripheral area of ​​the semiconductor structure, wherein the plurality of support structures are arranged in a point-symmetrical manner relative to the center of the semiconductor structure; and an insulating encapsulation body, which is arranged on the chip circuit structure and encapsulates the at least one first semiconductor tube core and the plurality of support structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figures 1 to 10 are schematic cross-sectional views of various stages in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0007] Fig.11 is a schematic cross-sectional view showing a semiconductor structure according to an alternative embodiment of the present disclosure.

[0008] Fig.12 is a schematic cross-sectional view showing a semiconductor structure according to an alternative embodiment of the present disclosure.

[0009] Fig.13 It is shown Fig.10 Schematic plan view of the semiconductor structure shown in FIG.

[0010] Fig.14 and Fig.15 is an enlarged schematic cross-sectional view illustrating various embodiments of a bonding interface between a semiconductor die and a bridge die overlapping the semiconductor die according to some embodiments of the present disclosure.

[0011] Figures 16 to 20 Schematic plan views of semiconductor structures according to some alternative embodiments of the present disclosure.

[0012] Fig.21 is a schematic plan view showing a semiconductor structure according to some embodiments of the present disclosure.

[0013] Fig. 22 yes Fig.21 Schematic cross-sectional view of the semiconductor structure shown.

[0014] Fig.23 and Fig.24 Schematic plan views of semiconductor structures according to some alternative embodiments of the present disclosure.

[0015] Figure 25 to Figure 28 are schematic cross-sectional views of various stages in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0016] Fig.29 is a schematic cross-sectional view showing a semiconductor structure according to an alternative embodiment of the present disclosure.

[0017] Fig.30 and Fig.31 are enlarged schematic cross-sectional views illustrating various embodiments of a bonding interface between a semiconductor die and a metallization layer overlapping the semiconductor die according to some embodiments of the present disclosure.

[0018] Fig.32 is a schematic cross-sectional view showing a semiconductor structure according to some embodiments of the present disclosure.

[0019] Fig.33 is a schematic cross-sectional view showing a semiconductor structure according to an alternative embodiment of the present disclosure.

[0020] Figure 34 to Figure 35 are schematic cross-sectional views of various stages in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0021] Fig.36 is a schematic cross-sectional view showing a semiconductor structure according to an alternative embodiment of the present disclosure.

[0022] [Description of Figure Numbers]

[0023] 50A, 50B, 50C: connector;

[0024] 90: Isolation layer;

[0025] 100, 100A, 100B, 100C, 100D, 400: semiconductor die;

[0026] 101, 101', 103, 106: carrier;

[0027] 102, 104, 105: peeling layer;

[0028] 110, 210, 310, 410: semiconductor substrate;

[0029] 120, 420: device layer;

[0030] 130, 230, 430: internal connection structure;

[0031] 132, 232, 324, 432, 610, 610A, 610B, 610C, 710, 710A, 710B, 710C, 1022: dielectric layer;

[0032] 134, 234, 434: metallization layer;

[0033] 140, 240, 330, 440: connection pads;

[0034] 150, 250, 450, 360: connecting through holes;

[0035] 160, 260, 460, 370: protective layer;

[0036] 170, 470, 380: conductive columns;

[0037] 180, 480, 390: padding;

[0038] 200: dummy die;

[0039] 300: Deep Trench Capacitor (DTC);

[0040] 320: capacitor;

[0041] 322, 326, 1024: conductive layer;

[0042] 340, 740: passivation layer;

[0043] 350: rear passivation layer;

[0044] 500, 500n, 500m: insulation enclosure;

[0045] 500a: insulation enclosure / first part;

[0046] 500b: insulation enclosure / second part;

[0047] 600, 600m: chip structure;

[0048] 620, 620A, 620B, 720, 720A, 720B, 720C: seed layer;

[0049] 630, 630A, 630B: wiring layer;

[0050] 630t, 730t: line part;

[0051] 630v, 730v: through-hole part;

[0052] 700: Re-route line structure;

[0053] 730, 730A, 730B, 730C: patterned conductive layer;

[0054] 800: Under ball metal (UBM) pattern;

[0055] 900, 3000: conductive terminals;

[0056] 1000: Intermediary layer;

[0057] 1010: core part;

[0058] 1012: core dielectric layer;

[0059] 1014: Perforation;

[0060] 1016: core conductive layer;

[0061] 1018: conductive cover;

[0062] 1020: Wiring part;

[0063] 1030A, 1030B: solder mask;

[0064] 2000: bottom filler;

[0065] A-A', B-B': line;

[0066] BL1: first accumulation layer;

[0067] BL2: second stacking layer;

[0068] CT: central;

[0069] D1, D3, D5: horizontal distance;

[0070] D2, D4, D6: vertical distance;

[0071] D7, D8, D9: minimum distance;

[0072] D10: diameter;

[0073] DL1, DL2, DL3, DL4, DL5, DL6: diameter line;

[0074] DR: device area;

[0075] IF1, IF2, IF3: bonding interfaces;

[0076] OP: Opening;

[0077] PR: peripheral region;

[0078] S1, S2: side;

[0079] S110b, S210b, S310b, S410b, S500b: bottom surface;

[0080] S110f, S210f, S310f, S410f: active surfaces;

[0081] S100, S150t, S160t, S200, S250t, S260t, S300, S360t, S370t, S400, S450t, S460t, S610t, S630t: top surface;

[0082] S100b, S200b, S300b, S400b: bottom side / rear side / bottom side surface / rear side surface;

[0083] S100t, S200t, S300t, S400t: front side / front side surface;

[0084] S500t1, S500t3: substantially inclined flat surface;

[0085] S500t2, S500t4: substantially flat surface;

[0086] S600t, S730t: surface;

[0087] SL: cutting lane;

[0088] SP1: semiconductor structure / semiconductor package;

[0089] SP1', SP1", SP2, SP3, SP3', SP4, SP4', SP5, SP6: semiconductor structure;

[0090] SW1, SW3, SW5: side walls;

[0091] SW2: Edge;

[0092] SW2c: cut edge;

[0093] T1: first level;

[0094] T2: The second level;

[0095] U1, U2: dotted boxes;

[0096] X, Y: direction;

[0097] Z: Stacking direction. DETAILED DESCRIPTION

[0098] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0099] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0100] In addition, for ease of description, terms such as "first", "second", "third", "fourth" and similar terms may be used herein to describe similar components or features or different components or features shown in the figures, and may be used interchangeably depending on the order of existence or the context of description.

[0101] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those with ordinary knowledge in the art to which the present disclosure belongs. It should be further understood that terms (such as terms defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted as an idealized or overly formal meaning unless explicitly defined herein.

[0102] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may, for example, include a test pad formed in a redistribution layer or on a substrate to enable testing of a 3D package or 3DIC device, use of a probe and / or a probe card, and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method including intermediate verification of a known good die to improve yield and reduce cost.

[0103] It should be understood that the following embodiments of the present disclosure provide applicable concepts that can be implemented in a variety of specific contexts. The embodiments are intended to provide further explanation, but are not intended to limit the scope of the present disclosure. The specific embodiments described herein are related to a semiconductor (package) structure, which contains one or more semiconductor tube cores encapsulated in an insulating encapsulation at the wafer level, wherein one or more dummy tube cores and / or one or more deep trench capacitors (deep trench capacitors, DTCs) are close to the one or more semiconductor tube cores near the edge of the insulating encapsulation, and the specific embodiments are not intended to limit the scope of the present disclosure. Due to the presence of the one or more dummy tube cores and / or the one or more deep trench capacitors (DTCs), potential damage to the one or more semiconductor tube cores (having functionality) can be avoided during the planarization process of the insulating encapsulation in the manufacturing process of the semiconductor (package) structure, thereby enhancing the reliability of the semiconductor (package) structure. It should be understood that additional processes can be provided before, during and after the method shown, and some other processes can only be briefly described herein. Throughout the present disclosure, it is to be understood that throughout the figures, illustrations of components are schematic and not drawn to scale.

[0104] In all the various views and exemplary embodiments of the present disclosure, components that are similar or substantially the same as previously described components will use the same reference numbers, and certain details or descriptions of the same components (e.g., materials, formation processes, positioning configurations, electrical connections, etc.) will not be repeated. For clarity of illustration, the drawings are shown using orthogonal axes (X, Y, and Z) of a Cartesian coordinate system, and the drawings are oriented according to the Cartesian coordinate system; however, the present disclosure is not specifically limited thereto.

[0105] Figures 1 to 10 Schematic cross-sectional views of various stages in a method for manufacturing a semiconductor structure SP1 according to some embodiments of the present disclosure. Fig.11 is a schematic cross-sectional view showing a semiconductor structure SP1 ′ according to an alternative embodiment of the present disclosure. Fig.12 is a schematic cross-sectional view showing a semiconductor structure SP1″ according to an alternative embodiment of the present disclosure. Fig.13 It is shown Fig.10 A schematic plan view of a semiconductor structure SP1 is shown in FIG. Figures 1 to 10 The cross-sectional view shown is along Fig.13 The diagram is taken along the line AA' shown in FIG. Fig.14 and Fig.15 is an enlarged schematic cross-sectional view showing various embodiments of a bonding interface between a semiconductor die and a bridge die overlapping the semiconductor die according to some embodiments of the present disclosure, wherein Fig.14 and Fig.15 The enlarged schematic cross-sectional view shown is Figure 4 The dashed box U1 shown in FIG. 1 is an outline. Figures 16 to 20 1 and 2 are schematic plan views respectively showing semiconductor structures according to some alternative embodiments of the present disclosure. In some embodiments, the manufacturing method is part of a wafer-level packaging process. In some embodiments, the semiconductor structure SP1 is in the form of a wafer or a panel. The semiconductor structure SP1 may be in the form of a diameter (e.g., Fig.13 The semiconductor structure SP1 may be in the form of a wafer size having a diameter (e.g., D10) of about 4 inches or more. The semiconductor structure SP1 may be in the form of a wafer size having a diameter (e.g., D10) of about 6 inches or more. The semiconductor structure SP1 may be in the form of a wafer size having a diameter (e.g., D10) of about 8 inches or more. Alternatively, the semiconductor structure SP1 may be in the form of a wafer size having a diameter (e.g., D10) of about 12 inches or more. On the other hand, the semiconductor structure SP1 may be in the form of a panel size having a major axis of about 4 inches or more, about 6 inches or more, about 8 inches or more, about 12 inches or more, or any other suitable size. The present disclosure is not limited thereto.

[0106] Reference Figure 1 , in some embodiments, a carrier is provided. In some embodiments, the carrier 101 is a glass carrier, a ceramic carrier, or any carrier suitable for carrying a semiconductor wafer or a reconstituted wafer for the manufacturing method of the semiconductor structure. However, as another option, the carrier 101 may be a reclaim wafer or a reconstituted wafer for the manufacturing method of the semiconductor structure. For non-limiting examples, when the material of the carrier 101 is a Si substrate, the carrier 101 can be used as a heat dissipation component of the semiconductor structure SP1. In this case, the carrier 101 can be further used for warpage control. In one embodiment, the carrier 101 is a glass carrier, wherein the carrier 101 is removed after the semiconductor structure SP1 is manufactured. In this case, the carrier 101 may be a temporary support structure that can be removed during the manufacturing method of the semiconductor structure SP1. In one embodiment, the carrier 101 may be a mechanical support structure that may not be removed after the manufacturing method of the semiconductor structure SP1. As another option, the carrier 101 may be a mechanical support structure that can be thinned to a thickness having sufficient mechanical support strength after the manufacturing method of the semiconductor structure SP1.

[0107] In some embodiments, a debond layer 102 is used to coat a carrier 101 (eg Figure 1 ). The material of the peeling layer 102 may be any material suitable for bonding and peeling the carrier 101 relative to the upper layer or any wafer disposed on the carrier 101. In some embodiments, the peeling layer 102 includes a dielectric material layer made of a dielectric material, and the dielectric material includes any suitable polymer-based dielectric material (e.g., benzocyclobutene (BCB), polybenzoxazole (PBO)). For a non-limiting example, the peeling layer 102 includes a dielectric material layer made of an epoxy resin-based thermal release material (e.g., a light-to-heat-conversion (LTHC) release coating film) that loses its adhesive properties when heated. For another non-limiting example, the peeling layer 102 includes a dielectric material layer made of a UV glue that loses its adhesive properties when exposed to ultraviolet (UV) light. The release layer 102 may be dispensed as a liquid and cured on the carrier 101, may be a laminate film laminated to the carrier 101, or may be formed on the carrier 101 by any suitable method. Figure 1As shown in FIG. 1 , the top surface of the peeling layer 102 (which is opposite to the bottom surface contacting the carrier 101) is flattened and has a high degree of planarity. In some embodiments, the peeling layer 102 is a LTHC layer with good chemical resistance, and such a layer can be peeled off from the carrier 101 at room temperature by applying laser irradiation, but the present disclosure is not limited thereto.

[0108] In an alternative embodiment, a buffer layer (not shown) is coated on the peeling layer 102, wherein the peeling layer 102 is sandwiched between the buffer layer and the carrier 101, and the top surface of the buffer layer can further provide a high degree of planarity. In some embodiments, the buffer layer can be a dielectric material layer. In some embodiments, the buffer layer can be a polymer layer made of polyimide (PI), PBO, BCB, or any other suitable polymer-based dielectric material. In some embodiments, the buffer layer can be an Ajinomoto Buildup Film (ABF), a Solder Resist Film (SRF), or a similar film. In other words, the buffer layer is an optional dielectric layer and can be omitted based on demand; the present disclosure is not limited thereto. For example, the buffer layer can be formed by suitable manufacturing techniques such as spin-coating, lamination, deposition, or similar techniques.

[0109] In some embodiments, at least one semiconductor die is provided. In some embodiments, as Fig.13 Combination Figure 1 As shown, one or more semiconductor dies 400 are provided, and then the one or more semiconductor dies 400 are placed on a peeling layer 102 located on a carrier 101. For illustrative purposes, Fig.13 Only four semiconductor dies 400 are shown, and along Fig.13 The line A-A' shown in FIG. Figures 1 to 10 Only one semiconductor die 400 is shown in the cross-sectional view. However, the number of semiconductor dies 400 is selected and specified based on requirements and design layout, and the number may be one, two, three, four, or more. The present disclosure is not limited thereto.

[0110] In some embodiments, each of the semiconductor dies 400 includes a semiconductor substrate 410, a device layer 420 formed on the semiconductor substrate 410 and having a plurality of semiconductor devices (not shown), an interconnect structure 430 formed on the device layer 420 and above the semiconductor substrate 410, a plurality of connection pads 440 formed on the interconnect structure 430, a plurality of connection vias 450 formed on the connection pads 440, a protection layer 460 covering the interconnect structure 430, the connection pads 440, and the connection vias 450, and a plurality of conductive pillars 470 formed (embedded) in the semiconductor substrate 410. In some embodiments, the semiconductor substrate 410 includes a bulk semiconductor substrate that may be doped or undoped, a semiconductor-on-insulator (SOI) substrate, other supporting substrates (e.g., quartz, glass, etc.), combinations thereof, or the like. In some embodiments, the semiconductor substrate 410 includes an elemental semiconductor (e.g., silicon or germanium in a crystalline structure, a complex structure, or an amorphous structure), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (e.g., silicon-germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), a combination thereof, or other suitable materials. The compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure. Alloy SiGe may be formed on a silicon substrate. The SiGe substrate may be strained.

[0111] In some embodiments, the device layer 420 includes semiconductor devices formed on the semiconductor substrate 410 (and / or partially formed in the semiconductor substrate 410), wherein the semiconductor devices include active devices (e.g., transistors, diodes, memories, etc.), passive devices (e.g., capacitors, resistors, inductors, jumpers, etc.), other suitable electrical components, and / or combinations thereof. Figure 1 As shown in , the device layer 420 may be disposed at an active surface S410f of the semiconductor substrate 410 near the interconnect structure 430. In some embodiments, the semiconductor substrate 410 has the active surface S410f and a bottom surface S410b opposite to the active surface S410f along a stacking direction Z of the interconnect structure 430, the device layer 420, and the semiconductor substrate 410. In some embodiments, the device layer 420 is sandwiched between the interconnect structure 430 and the active surface S410f of the semiconductor substrate 410.

[0112] The device layer 420 may include a circuit system (not shown) formed in the front-end-of-line (FEOL) process, and the interconnect structure 430 may be formed in the back-end-of-line (BEOL) process. In some embodiments, the interconnect structure 430 includes an inter-layer dielectric (ILD) layer formed on the device layer 420 and an inter-metallization dielectric (IMD) layer formed on the ILD layer. In some embodiments, the ILD layer and the IMD layer are formed of low-K dielectric materials or extreme low-K (ELK) materials such as oxide, silicon dioxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), fluorinated silicate glass (FSG), SiOxCy (where x>0, y>0), spin-on glass, spin-on polymer, silicon-carbon materials, compounds thereof, composites thereof, combinations thereof, or the like. The ILD layer and the IMD layer may include any suitable number of dielectric material layers, and the number of the dielectric material layers is not limited thereto.

[0113] In some embodiments, the interconnect structure 430 includes alternating one or more dielectric layers 432 and one or more metallization layers 434. The metallization layers 434 may be embedded in the dielectric layers 432. In some embodiments, the interconnect structure 430 electrically couples the semiconductor devices of the device layer 420 to each other and to external components (e.g., test pads, bonding conductors, etc.) formed on the semiconductor devices. For example, the metallization layers 434 in the dielectric layers 432 route electrical signals between the semiconductor devices of the device layer 420. The semiconductor devices of the device layer 420 and the metallization layers 434 are interconnected to perform one or more functions including memory structures (e.g., memory cells), processing structures (e.g., logic cells), input / output (I / O) circuit systems (e.g., I / O cells), or the like. The topmost layer of the interconnect structure 430 may be a passivation layer made of one or more suitable dielectric materials (e.g., silicon oxide, silicon nitride, low-k dielectric, PI, combinations thereof, or the like). Figure 1As shown in FIG. 4 , the passivation layer (eg, the uppermost layer of the dielectric layer 432 ) of the interconnect structure 430 has a plurality of openings that expose at least a portion of the topmost layer of the metallization layer 434 for further electrical connection.

[0114] The dielectric layer 432 may be PI, PBO, BCB, nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), PSG, borosilicate glass (BSG), BPSG, combinations thereof, or the like, which may be patterned using photolithography and / or etching processes. The etching process may include dry etching, wet etching, or a combination thereof. In some embodiments, the dielectric layer 432 is formed by a suitable fabrication technique such as spin coating, chemical vapor deposition (CVD) (e.g., plasma-enhanced chemical vapor deposition (PECVD)), or the like.

[0115] The metallization layer 434 may be made of a conductive material (e.g., copper, copper alloy, aluminum, aluminum alloy, or a combination thereof) formed by electroplating or deposition and patterned using photolithography and etching processes. The etching process may include dry etching, wet etching, or a combination thereof. In some embodiments, the metallization layer 434 is a patterned copper layer or other suitable patterned metal layer. For example, the metallization layer 434 may be a metal line, a metal via, a metal pad, a metal trace, etc. Throughout this specification, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium. The number of dielectric layers 432 and the number of metallization layers 434 are not limited in the present disclosure and may be selected and specified based on requirements and design layout.

[0116] In some embodiments, Figure 1As shown in , the connection pad 440 is disposed on the topmost layer of the metallization layer 434 of the interconnect structure 430 exposed by the passivation layer (e.g., the topmost layer of the dielectric layer 432) of the interconnect structure 430 and is electrically coupled to the topmost layer of the metallization layer 434 of the interconnect structure 430 for testing and / or further electrical connection. The connection pad 440 may be made of aluminum, copper, or an alloy thereof, or a similar material, and the connection pad 440 may be formed by an electroplating process. The present disclosure is not limited to this. Some of the connection pads 440 may be test pads, and some of the connection pads 440 may be conductive pads for further electrical connection. In alternative embodiments, the connection pad 440 may be optional to achieve a simple structure and cost-effectiveness. In such alternative embodiments, the connection via 450 may be directly connected to the topmost metallization layer 434.

[0117] In some embodiments, the connecting vias 450 are respectively disposed on the connecting pads 440 and electrically connected to the connecting pads 440 to provide external electrical connections for the circuit system and the semiconductor device of the device layer 420. In one embodiment, the connecting vias 450 can be formed of a conductive material (e.g., copper, gold, aluminum, a similar material, or a combination thereof), and the connecting vias 450 can be formed by an electroplating process or a similar process. The connecting vias 450 can be bonding vias, bonding pads, bonding bumps, or a combination thereof. The present disclosure is not limited thereto. The connecting vias 450 can be used as bonding conductors for further electrical connections, and can be formed on the connecting pads 440 (used as conductive pads for further electrical connections). The connecting vias 450 can be electrically coupled to the semiconductor device of the device layer 420 via the internal wiring structure 430 and the connecting pads 440.

[0118] Alternatively, both the connection pad 440 and the connection via 450 may be formed on the interconnect structure 430. For example, the connection via 450 is disposed on the topmost layer of the metallization layer 434 of the interconnect structure 430 exposed by the passivation layer of the interconnect structure 430 (e.g., the topmost layer of the dielectric layer 432) and is electrically connected to the topmost layer. That is, the connection via 450 and the connection pad 440 may be disposed side-by-side on the topmost layer of the metallization layer 434 of the interconnect structure 430 exposed by the passivation layer of the interconnect structure 430. In such an embodiment, the connection pad 440 may be a test pad for testing, and the connection via 450 may be a bonding conductor for further electrical connection. The connection via 450 may be electrically coupled to the semiconductor device of the device layer 420 via the interconnect structure 430. The number of connection pads 440 and the number of connection vias 450 may be selected and specified based on requirements and design layout, and thus are not limited thereto.

[0119] In some embodiments, the protection layer 460 is formed on the interconnect structure 430 to cover the interconnect structure 430, the connection pads 440, and the connection vias 450. That is, the protection layer 460 prevents any possible damage from occurring on the connection pads 440 and the connection vias 450 during the transfer of the semiconductor die 400. In addition, in some embodiments, the protection layer 460 is further used as a passivation layer to provide better planarization and evenness. In some embodiments, as shown in FIG. Figure 1 As shown in FIG. 4 , the top surface of the connecting via 450 is not exposed in an accessible manner through the top surface S400 of the protection layer 460 .

[0120] The protective layer 460 may include one or more layers formed of a dielectric material, such as silicon nitride, silicon oxide, high-density plasma (HDP) oxide, tetra-ethyl-ortho-silicate (TEOS), undoped silicate glass (USG), silicon oxynitride, PBO, PI, silicon carbon, silicon oxynitride carbon, diamond like carbon (DLC), similar materials or combinations thereof. It should be understood that, depending on the process requirements, the protective layer 460 may include an etch stop material layer (not shown) sandwiched between the dielectric material layers. For example, the etch stop material layer is different from the overlying dielectric material layer or the underlying dielectric material layer. The etch stop material layer may be formed of a material having a high etch selectivity relative to the overlying dielectric material layer or the underlying dielectric material layer so as to be used to stop etching the dielectric material layer.

[0121] In some embodiments, the conductive pillar 470 is embedded in the semiconductor substrate 410. For example, the conductive pillar 470 is formed in the semiconductor substrate 410 and extends from the active surface S410f toward the bottom surface S410b along the stacking direction Z. Figure 1 As shown in FIG. 4 , for example, the conductive pillar 470 penetrates the device layer 420 to electrically connect to the metallization layer 434 of the interconnect structure 430 and is electrically connected to the semiconductor device of the device layer 420 via the interconnect structure 430. Figure 1As shown in , for example, the conductive pillar 470 makes physical contact with the bottommost layer of the metallization layer 434 of the interconnect structure 430 that is exposed by the bottommost layer of the dielectric layer 432 of the interconnect structure 430. That is, the conductive pillar 470 is electrically connected to the semiconductor device included in the device layer 420 via the interconnect structure 430, and is electrically connected to the connection via 450 via the interconnect structure 430 and the connection pad 440. The conductive pillar 470 may be formed of a conductive material (e.g., copper, tungsten, aluminum, silver, a combination thereof, or the like) that can be formed by plating or deposition (e.g., CVD). Alternatively, the conductive pillar 470 may not penetrate through the device layer 420, wherein the top surface of the conductive pillar 470 may be substantially coplanar with the active surface S410f of the semiconductor substrate 410 to directly connect to the semiconductor device of the device layer 420. In this case, the conductive pillar 470 may be electrically connected to the interconnect structure 430 via the semiconductor device of the device layer 420 .

[0122] like Figure 1 As shown in FIG. 4 , the conductive pillar 470 is exposed in a touchable manner through the bottom surface S410b of the semiconductor substrate 410. However, the present disclosure is not limited thereto, and as another option, the conductive pillar 470 may not be exposed in a touchable manner through the bottom surface S410b of the semiconductor substrate 410. In some embodiments, the conductive pillar 470 may taper from the interconnect structure 430 to the bottom surface S410b of the semiconductor substrate 410. As another option, the conductive pillar 470 has a substantially vertical sidewall.

[0123] In the cross-sectional view along the stacking direction Z, the shape of the conductive pillar 470 may depend on the design requirements and is not intended to be limited in the present disclosure. For example, in the (planar) top view on the XY plane perpendicular to the stacking direction Z, the shape of the conductive pillar 470 is a circular shape. However, depending on the design requirements, the shape of the conductive pillar 470 may be an elliptical shape, a rectangular shape, a polygonal shape, or a combination thereof; the present disclosure is not limited thereto. The number of the conductive pillars 470 is not limited to the figures of the present disclosure, and the number of the conductive pillars 470 may be selected and specified based on the requirements and the design layout.

[0124] In some embodiments, each of the conductive pillars 470 is covered by a liner 480. For example, the liner 480 is formed between the conductive pillar 470 and the semiconductor substrate 410 and between the conductive pillar 470 and the device layer 420. In some embodiments, the sidewall of each of the conductive pillars 470 may be covered by a corresponding one of the liner 480. The liner 480 may be formed of a barrier material (e.g., TiN, Ta, TaN, Ti, or the like). In alternative embodiments, a dielectric liner (not shown) (e.g., silicon nitride, oxide, polymer, combination thereof, etc.) may be further formed between the liner 480 and the semiconductor substrate 410 and between the liner 480 and the device layer 420 as needed. In some embodiments, the conductive pillars 470, the liner 480, and the optional dielectric liner are formed by, but not limited to, the following methods: forming a plurality of grooves in the semiconductor substrate 410 and the device layer 420; depositing dielectric material, barrier material, and conductive material in the grooves, respectively; and removing excess material on the device layer 420. For example, the recess of the semiconductor substrate 410 and the recess of the device layer 420 are lined with a dielectric liner to laterally separate the liner 480 lined on the sidewall of the conductive pillar 470 from the semiconductor substrate 410 and the device layer 420. Alternatively, the liner 480 may be omitted. Alternatively, both the conductive pillar 470 and the liner 480 may be omitted.

[0125] In some embodiments, a via-first approach is used to form the conductive pillar 470. The conductive pillar 470 may be formed before forming the interconnect structure 430. Alternatively, a via-last approach may be used to form the conductive pillar 470, and the conductive pillar 470 may be formed after forming the interconnect structure 430.

[0126] In an alternative embodiment in which the conductive pillars 470 are not exposed in a tangible manner through the bottom surface S410b of the semiconductor substrate 410, the sidewalls and the bottom surface (away from the device layer 420) of each of the conductive pillars 470 may be covered by a corresponding one of the pads 480. In this case, the aforementioned dielectric liner may be further formed between the pad 480 and the semiconductor substrate 410 and between the pad 480 and the device layer 420 as needed. If necessary, the conductive pillars 470 may be exposed in a tangible manner through the bottom surface S410b of the semiconductor substrate 410 by performing a planarization process or an etching process in a subsequent step, but the present disclosure is not limited thereto.

[0127] In some embodiments, each of the semiconductor dies 400 further includes an isolation layer (not shown) disposed on the semiconductor substrate 410 and laterally covering an end portion of the conductive pillar 470, wherein the semiconductor substrate 410 is located between the isolation layer and the device layer 420. The isolation layer may be formed by, but not limited to, the following methods: recessing the semiconductor substrate 410 to allow the conductive pillar 470 to protrude out of the semiconductor substrate 410 after the conductive pillar 470 is accessible through the semiconductor substrate 410; forming a blanket layer of an isolation material (e.g., oxide, nitride, oxynitride, carbide, or polymer, etc.) on the entirety by spin coating or deposition (e.g., CVD) to cover the semiconductor substrate 410 and the conductive pillar 470; and performing a planarization process on the isolation material blanket layer to accessibly expose the end surface of the conductive pillar 470, wherein the remaining isolation material blanket layer disposed on the semiconductor substrate 410 and laterally covering a portion of the conductive pillar 470 is referred to as the isolation layer. Alternatively, a native oxide may be formed on the bottom surface S410 b of the semiconductor substrate 410 before forming the isolation layer.

[0128] In some embodiments, Figure 1 Combination Fig.13As shown, semiconductor die 400 faces up and is placed on a release layer 102 over carrier 101. Semiconductor die 400 may be independently referred to as a semiconductor die or a semiconductor chip, including a digital chip, an analog chip, or a mixed signal chip. In some embodiments, the semiconductor die 400 is independently: a logic die, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), a tensor processing unit (TPU), a system-on-a-chip (SoC), a system-on-integrated circuit (SoIC), an application processor (AP) and a microcontroller; a power management die, such as a power management integrated circuit (PMIC) die; a wireless and radio frequency (RF) die; a baseband (BB) die; a sensor die, such as an optical / image sensor chip; a micro-electro-mechanical-system (MEMS) die; a signal processing die, such as a digital signal processing (DSP) die; a microcontroller; a microprocessor ... processing, DSP) die; front-end die, such as analog front-end (AFE) die; application-specific die, such as application-specific integrated circuit (ASIC), field-programmable gate array (FPGA); combinations thereof; or similar components.In alternative embodiments, the semiconductor die 400 is independently a memory die with or without a controller, wherein the memory die includes: a single form die, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a resistive random-access memory (RRAM), a magnetic random access memory (MRAM), a NAND flash memory, or a wide I / O (WIO) memory; a pre-stacked memory cube, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module; a combination thereof; or the like. In some alternative embodiments, the semiconductor die 400 independently is: an artificial intelligence (AI) engine, such as an AI accelerator; a computing system, such as an AI server, a high-performance computing (HPC) system, a high-power computing device, a cloud computing system, a networking system, an edge computing system, an immersive memory computing system (ImMC), a SoIC system, etc.; a combination thereof; or a similar component. In some other embodiments, the semiconductor die 400 is independently an electrical input / output (I / O) interface die and / or an optical input / output (I / O) interface die, an integrated passive die (IPD), a voltage regulator (VR) die, a local silicon interconnect (LSI) die with or without a deep trench capacitor (DTC) feature, a local silicon interconnect die with multi-level functions (e.g., an electrical network circuit interface and / or an optical network circuit interface, IPD, VR, DTC, or the like). The type of semiconductor die 400 can be selected and specified based on needs and design requirements, and is therefore not specifically limited in the present disclosure.

[0129] According to some embodiments of the present disclosure, some of the semiconductor dies 400 are of different types, while some of the semiconductor dies 400 are of the same type. In alternative embodiments, all of the semiconductor dies 400 are of different types. In yet other alternative embodiments, all of the semiconductor dies 400 are of the same type. According to some embodiments of the present disclosure, some of the semiconductor dies 400 are of different sizes, while some of the semiconductor dies 400 are of the same size. In yet other alternative embodiments, all of the semiconductor dies 400 are of different sizes. In yet other alternative embodiments, all of the semiconductor dies 400 are of the same size. According to some embodiments of the present disclosure, some of the semiconductor dies 400 are of different shapes, while some of the semiconductor dies 400 are of the same shape. In yet other alternative embodiments, all of the semiconductor dies 400 are of the same shape. The type, size, and shape of each of the semiconductor dies 400 are independent of each other and can be selected and designed based on requirements and design layout, and the present disclosure is not limited thereto. Figure 1 and Fig.13 As shown in FIG. 4 , the semiconductor die 400 is disposed in a device region DR of the semiconductor structure SP1 , wherein the device region DR is surrounded by (eg, enclosed by) a peripheral region PR of the semiconductor structure SP1 .

[0130] Reference Figure 2 In some embodiments, the semiconductor die 400 is encapsulated in an insulating material. In some embodiments, an insulating encapsulant 500m is conformally formed on the semiconductor die 400 and on the carrier 101, wherein the semiconductor die 400 and the peeling layer 102 exposed by the semiconductor die 400 are completely covered by the insulating encapsulant 500m. The insulating encapsulant 500m may be made of a dielectric material (e.g., an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), TEOS, or a similar material) or any insulating material suitable for gap filling, and the insulating encapsulant 500m may be formed by deposition (e.g., a CVD process). Figure 2 Combination Fig.13 As shown, for example, a top surface S400 of the semiconductor die 400 is not accessible through the insulating encapsulation 500m.

[0131] Alternatively, the insulating enclosure 500m may be a molding compound, a molding underfill, a resin (e.g., an epoxy resin), or a similar material that can be formed by a molding process. The molding process may include a compression molding process or a transfer molding process. The insulating enclosure 500m may include a polymer (e.g., an epoxy resin, a phenolic resin, a silicone resin, or other suitable resin) or other suitable material. Alternatively, the insulating enclosure 500m may include an acceptable insulating enclosure material. In some embodiments, the insulating enclosure 500m further includes an inorganic filler or an inorganic compound (e.g., silica, clay, etc.) that can be added to the insulating enclosure 500m to optimize the coefficient of thermal expansion (CTE) of the insulating enclosure 500m. The present disclosure is not limited thereto.

[0132] Reference Figure 2 and Figure 3 In some embodiments, a planarization process is performed on the insulating encapsulant 500m to form an insulating encapsulant 500a exposing the semiconductor die 400. For example, a portion of the insulating encapsulant 500m is removed to form the insulating encapsulant 500a, the insulating encapsulant 500a having a top surface composed of a substantially slanted planar surface S500t1 at the peripheral region PR and a substantially planar surface S500t2 at the device region DR surrounded (or defined) by the substantially slanted planar surface S500t1, wherein the substantially slanted planar surface S500t1 is connected to the substantially planar surface S500t2 and the (substantially vertical) sidewalls of the insulating encapsulant 500a (the sidewalls are Fig.10 and Fig.13 ). Figure 3 and Fig.13As shown in, for example, the substantially flat surface S500t2 is connected to the substantially inclined flat surface S500t1 and is surrounded by the substantially inclined flat surface S500t1. The substantially flat surface S500t2 can be considered as a substantially horizontal flat surface extending along the XY plane. In this case, the substantially flat surface S500t2 exposes the semiconductor die 400 in a touchable manner. For example, the top surface S450t of the connection through hole 450 of each of the semiconductor die 400 and the top surface S460t of the protection layer 460 are substantially flush with the substantially flat surface S500t2 of the insulating encapsulation 500a. In other words, the top surface S450t of the connection through hole 450 of the semiconductor die 400 and the top surface S460t of the protection layer 460 are substantially coplanar with the substantially flat surface S500t2 of the insulating encapsulation 500a. For each semiconductor die 400, the top surface S450t of the connecting via 450 and the top surface S460t of the protection layer 460 are collectively referred to as the front side or the front side surface S400t, and the bottom surface S410b is referred to as the bottom side, the back side, the bottom side surface or the back side surface S400b, wherein the bottom side S400b is opposite to the front side S400t in the stacking direction Z. Figure 3 As shown in , the bottom side S400b may be substantially coplanar with a bottom surface S500b of the insulation encapsulation 500a, wherein the bottom surface S500b of the insulation encapsulation 500a is opposite to a substantially flat surface S500t2 of the insulation encapsulation 500a.

[0133] On the other hand, the substantially inclined flat surface S500t1 may be considered as a beveledge, wherein the insulating encapsulation 500a has a thickness (not marked) that gradually decreases in a direction from the device region DR toward the sidewall of the semiconductor structure SP1 at the peripheral region PR. Such a beveledge may be formed at or near the edge / sidewall of the object to be ground during the planarization process due to over-grinding / grinding or a lower metal (or pattern) density compared to the central region of the object to be ground (e.g., the semiconductor structure SP1). If a semiconductor die (having an active device) is considered to be located at or near the edge / sidewall of the semiconductor structure SP1, such a semiconductor die will be damaged due to the generated beveledge, which may result in abnormal functionality or loss of functionality. To avoid such damage, one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (i.e., DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) may be employed at the peripheral region PR to serve as structural supports during the planarization (or thinning) process, whereby the resulting chamfered edges will terminate at / within the desired peripheral region PR without extending further into the device region DR. Thus, the semiconductor die formed in the device region DR defined by the desired peripheral region PR (where one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (i.e., DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) will be prevented from being damaged by the planarization (or thinning) process (which will be discussed in more detail later).

[0134] In some embodiments, the sidewalls (not marked) of the semiconductor die 400 and the peeling layer 102 exposed by the semiconductor die 100 are still covered by the insulating encapsulation body 500a. Figure 3 and Fig.13 As shown in FIG. 4 , the insulating encapsulation 500 a covers the semiconductor die 400 in a lateral direction.

[0135] During the planarization process, the protective layer 460 of one or more semiconductor dies 400 may be further planarized. In addition to the protective layer 460, the connecting vias 450 of one or more semiconductor dies 400 may also be further planarized. In some embodiments, the planarization process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof. The etching process may include dry etching, wet etching, or a combination thereof. After the planarization process, a cleaning process may be performed as needed, for example, to clean and remove the residues generated by the planarization process. However, the present disclosure is not limited thereto, and the planarization process may be performed by any other suitable method.

[0136] Reference Figure 4 In some embodiments, one or more semiconductor dies 100, one or more dummy dies 200, and one or more DTCs 300 are picked up and placed on the insulating package 500a and on the carrier 101. In some embodiments, as Figure 4 and Fig.13 As shown in FIG. 1 , the semiconductor die 100 is arranged in the device region DR, and the one or more dummy dies 200 and the one or more DTCs 300 are arranged in the peripheral region PR. Fig.13 Only twenty-two semiconductor dies 100, six dummy dies 200, and four DTCs 300 are shown in FIG. Figure 1 Only three semiconductor dies 100 are shown (for simplicity, Figure 4 100A, 100B, and 100C), one dummy die 200, and one DTC 300, but the present disclosure is not limited thereto. The number of semiconductor dies 100 may be more than twenty-two or less than twenty-two, the number of dummy dies 200 may be zero, less than six, or more than six, and the number of DTCs 300 may be zero, less than four, or more than four. The number of semiconductor dies 100, the number of dummy dies 200, and the number of DTCs 300 may be selected and specified based on requirements or design layout.

[0137] like Figure 4 and Fig.13As shown in , for example, the semiconductor dies 100 are arranged in the device region DR and arranged side by side with each other along the direction X and the direction Y, wherein the direction X and the direction Y are different from each other and different from the stacking direction Z of the carrier 101 and the peeling layer 102. The direction X and the direction Y may be substantially perpendicular to the stacking direction Z, and the direction X may be substantially perpendicular to the direction Y. Each semiconductor die 100 may be arranged in an array. For a non-limiting example, each semiconductor die 100 is arranged in the form of a matrix along the direction X and the direction Y, such as an N×N array or an N×M array (N, M>0, N may be equal to M or may not be equal to M). In some embodiments, each semiconductor die 100 arranged in directly adjacent columns and / or rows is positioned on the XY plane in an aligned manner (e.g., in an array form). In some other embodiments, each semiconductor die 100 arranged in directly adjacent columns and / or rows is positioned on the XY plane in a staggered manner (e.g., in a staggered form). In yet other embodiments, the semiconductor dies 100 are arranged in a concentric manner into a predetermined pattern, wherein at least one of the semiconductor dies 100 is located at the center of the device region DR (eg, Fig.13 The semiconductor structure SP1 is located at a center CT) of the semiconductor structure SP1 shown in FIG. 1 and is surrounded by other semiconductor dies 100 on the XY plane, and the semiconductor dies 100 surrounding the at least one semiconductor die 100 located at the center are arranged in a radial manner in the device region DR.

[0138] However, the present disclosure is not limited thereto. For example, Fig.13In the top view shown, the semiconductor dies 100 are each arranged in the device region DR and are separated from the directly adjacent device (e.g., another semiconductor die 100) by a horizontal distance D1 (e.g., the shortest distance measured along the direction X) and a vertical distance D2 (e.g., the shortest distance measured along the direction Y). In the case, some of the semiconductor dies 100 arranged in directly adjacent columns can be positioned in a staggered manner and / or aligned manner, and / or some of the semiconductor dies 100 arranged in directly adjacent rows can be positioned in a staggered manner and / or aligned manner. The horizontal distance D1 can be approximately in the range from 0.5 micrometers (μm) to 80 micrometers, but other suitable horizontal distances can be used alternatively. The vertical distance D2 can be approximately in the range from 0.5 micrometers to 80 micrometers, but other suitable vertical distances can be used alternatively. In some embodiments, the outermost semiconductor die 100 is spaced a minimum distance D7 from an edge (e.g., sidewall SW1) of the semiconductor package SP1. In some embodiments, the minimum distance D7 should be large enough to accommodate at least one of the dummy die 200 or the DTC 300. However, the present disclosure is not limited thereto; alternatively, the minimum distance D7 may be greater than or substantially equal to 0 millimeters (mm). The minimum distance D7 may be approximately within a range from 0 mm to 3 mm, but other suitable minimum distances may alternatively be utilized.

[0139] In some embodiments, each of the semiconductor dies 100 includes a semiconductor substrate 110 (having an active surface S110f and a bottom surface S110b opposite to the active surface S110f), a device layer 120 formed on the semiconductor substrate 110 and having a plurality of semiconductor devices (not shown), an interconnect structure 130 formed on the device layer 120 and on the semiconductor substrate 110 (including one or more dielectric layers 132 and one or more metallization layers 134 alternating), a plurality of connection pads 140 formed on the interconnect structure 130, a plurality of connection vias 150 formed on the connection pads 140, a protection layer 160 covering the interconnect structure 130, the connection pads 140, and the connection vias 150, and a plurality of conductive pillars 170 formed (embedded) in the semiconductor substrate 110. In some embodiments, each of the semiconductor dies 100 further includes an isolation layer (composed of a dielectric layer 132) disposed on the semiconductor substrate 110 and covering end portions of the conductive pillars 170 in a lateral direction. Fig.14 and Fig.15 ), wherein the semiconductor substrate 110 is located between the isolation layer (eg, 90) and the device layer 120. In some embodiments, as Figure 4As shown in , the conductive pillars 170 of the semiconductor die 100 penetrate through the device layer 120. In some embodiments, each of the conductive pillars 170 is covered by a liner 180. In addition, a dielectric liner (not shown) (e.g., silicon nitride, oxide, polymer, combination thereof, etc.) may be further formed between the liner 180 and the semiconductor substrate 110 and between the liner 180 and the device layer 120 as needed. As an alternative, the conductive pillars 170 of the semiconductor die 100 do not penetrate through the device layer 120. In embodiments in which the conductive pillars 170 of the semiconductor die 100 do not penetrate through the device layer 120, an optional dielectric liner may be formed only between the liner 180 and the semiconductor substrate 110.

[0140] like Figure 4 As shown in , for example, the semiconductor devices of the device layer 120 are interconnected via the interconnect structure 130, the connecting vias 150 are electrically connected to the interconnect structure 130 via the connecting pads 140, and the conductive pillars 170 are electrically connected to the semiconductor devices of the device layer 120 via the interconnect structure 130. Alternatively, the semiconductor devices of the device layer 120 are interconnected via the interconnect structure 130, the connecting vias 150 are electrically connected to the interconnect structure 130 via the connecting pads 140, and the conductive pillars 170 are electrically connected to the semiconductor devices of the device layer 120 via physical contacts. The formation, materials, and details of the semiconductor die 100 (e.g., semiconductor substrate 110, device layer 120, interconnect structure 130, connecting pads 140, connecting vias 150, protective layer 160, conductive pillars 170, liner 180, optional dielectric liner, and isolation layer (e.g., 90)) are similar to or substantially the same as those of Figure 1 The formation, materials and details of the semiconductor die 400 (e.g., semiconductor substrate 410, device layer 420, internal wiring structure 430, connection pads 440, connection vias 450, protective layer 460, conductive pillars 470, pads 480, optional dielectric pads and isolation layers) described in the present invention are not described herein and are therefore not repeated herein for the sake of brevity.

[0141] The semiconductor die 100 may be independently referred to as a semiconductor die or a semiconductor chip, including a digital chip, an analog chip, or a mixed signal chip. In some embodiments, the semiconductor die 100 is independently: a logic die, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), a tensor processing unit (TPU), a system chip (SoC), a system on an integrated circuit (SoIC), an application processor (AP), and a microcontroller; a power management die, such as a power management integrated circuit (PMIC) die; a wireless and radio frequency (RF) die; a baseband (BB) die; a sensor die, such as a light / image sensor chip; a microelectromechanical system (MEMS) die; a signal processing die, such as a digital signal processing (DSP) die; a front-end die, such as an analog front-end (AFE) die; an application-specific die, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA); a combination thereof; or a similar component. In alternative embodiments, the semiconductor die 100 is independently a memory die with or without a controller, wherein the memory die includes: a single form die, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a NAND flash memory, or a wide I / O (WIO) memory; a pre-stacked memory cube, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module; a combination thereof; or a similar component. In yet other alternative embodiments, the semiconductor die 100 is independently: an artificial intelligence (AI) engine, such as an AI accelerator; a computing system, such as an AI server, a high performance computing (HPC) system, a high power computing device, a cloud computing system, a networked system, an edge computing system, an immersive memory computing system (ImMC), a SoIC system, etc.; a combination thereof; or a similar component. In some other embodiments, the semiconductor die 100 is independently an electrical input / output (I / O) interface die and / or an optical input / output (I / O) interface die, an integrated passive die (IPD), a voltage regulator (VR) die, a local silicon interconnect (LSI) die with or without a deep trench capacitor (DTC) feature, a local silicon interconnect die with multi-level functions (e.g., an electrical network circuit interface and / or an optical network circuit interface, IPD, VR, DTC, or the like). The type of semiconductor die 100 may be selected and specified based on needs and design requirements, and is therefore not specifically limited in the present disclosure.

[0142] According to some embodiments of the present disclosure, some of the semiconductor dies 100 are of different types, while some of the semiconductor dies 100 are of the same type. In alternative embodiments, all of the semiconductor dies 100 are of different types. In yet other alternative embodiments, all of the semiconductor dies 100 are of the same type. According to some embodiments of the present disclosure, some of the semiconductor dies 100 are of different sizes, while some of the semiconductor dies 100 are of the same size. In yet other alternative embodiments, all of the semiconductor dies 100 are of different sizes. In yet other alternative embodiments, all of the semiconductor dies 100 are of the same size. According to some embodiments of the present disclosure, some of the semiconductor dies 100 are of different shapes, while some of the semiconductor dies 100 are of the same shape. In yet other alternative embodiments, all of the semiconductor dies 100 are of the same shape. The type, size, and shape of each of the semiconductor dies 100 are independent of each other and may be selected and designed based on requirements and design layout, and the present disclosure is not limited thereto.

[0143] Continue to refer to Figure 4 and Fig.13In some embodiments, the dummy die 200 and the DTC 300 are arranged in the peripheral region PR and close to the semiconductor die 100. For example, the dummy die 200 are grouped into a plurality of pairs of dummy die 200, wherein the two dummy die 200 in each pair of dummy die 200 are placed in the peripheral region PR at two opposite ends of a diameter line (e.g., diameter line DL3, DL5, and / or DL6) passing through the center CT of the semiconductor package SP1. Similarly, the DTC 300 are grouped into a plurality of pairs of DTCs 300, wherein the two DTCs 300 in each pair of DTCs 300 are placed in the peripheral region PR at two opposite ends of another diameter line (e.g., diameter line DL2 and / or DL4) passing through the center CT of the semiconductor package SP1. The first diameter line (e.g., diameter line DL2) may be substantially perpendicular to the second diameter line (e.g., diameter line DL4). In some alternative embodiments, one dummy die 200 and one DTC 300 are grouped into a pair, and the dummy die 200 and the DTC 300 in the corresponding pair may be placed in the peripheral region PR at two opposite ends of a diameter line passing through the center CT of the semiconductor package SP1. In a non-limiting example, the dummy die 200 is arranged in a point-symmetrical form or a point (e.g., center CT) reflection form. Alternatively, the dummy die 200 is arranged in a line-symmetrical form. In another non-limiting example, the DTC 300 is arranged in a point-symmetrical form or a point (e.g., center CT) reflection form. Alternatively, the DTC 300 is arranged in a line-symmetrical form. Alternatively, the dummy die 200 and the DTC 300 are arranged together in a point-symmetrical form or a point (e.g., center CT) reflection form. Alternatively, the dummy die 200 and the DTC 300 are arranged together in a line-symmetrical form.

[0144] In some embodiments, each of the dummy dies 200 includes: a semiconductor substrate 210 (having an active surface S210f and a bottom surface S210b opposite to the active surface S210f), an internal connection structure 230 formed on the semiconductor substrate 210 (including one or more dielectric layers 232 and one or more metallization layers 234 alternating), a plurality of connection pads 240 formed on the internal connection structure 230, a plurality of connection through holes 250 formed on the connection pads 240, and a protective layer 260 covering the internal connection structure 230, the connection pads 240, and the connection through holes 250. The internal connection structure 230 may be omitted. Alternatively, the internal connection structure 230 and the connection pads 240 may be omitted. Or alternatively, the internal connection structure 230, the connection pads 240, the connection through holes 250, and the protective layer 260 may be omitted. In other words, the dummy die 200 may be made of only silicon or silicon oxide. In the described situation, active devices and passive devices are not formed in the dummy die 200. That is, the dummy die 200 can further exclude metal routing lines. Due to the configuration of the dummy die 200, the dummy die 200 can be used as a heat dissipation component (or heat sink) of the semiconductor structure SP1. The type, size and shape of each of the dummy dies 200 are independent of each other and can be selected and designed based on requirements and design layout, but the present disclosure is not limited to this. The formation, materials and details of the dummy die 200 (for example, the semiconductor substrate 210, the internal connection structure 230, the connection pads 240, the connection vias 250 and the protective layer 260) are similar to or substantially the same as Figure 1 The formation, materials and details of the semiconductor die 400 (eg, semiconductor substrate 410, interconnect structure 430, connection pads 440, connection vias 450 and protection layer 460) described in the prior art are not described herein for brevity.

[0145] For example, in Fig.13In the top view shown, the dummy dies 200 are each arranged in the peripheral region PR and are separated from the directly adjacent device (e.g., another semiconductor die 100, another dummy die 200, or another DTC 300) by a horizontal distance D3 (e.g., the shortest distance measured along the direction X) and a vertical distance D4 (e.g., the shortest distance measured along the direction Y). The horizontal distance D3 may be approximately in the range from 0.5 microns to 100 microns (e.g., about 80 microns), but other suitable horizontal distances may be used alternatively. The vertical distance D4 may be approximately in the range from 0.5 microns to 100 microns (e.g., about 80 microns), but other suitable vertical distances may be used alternatively. In some embodiments, each of the dummy dies 200 is a minimum distance D8 from the edge (e.g., sidewall SW1) of the semiconductor package SP1. The minimum distance D8 may be approximately in the range from 0 mm to 3 mm, but other suitable minimum distances may be used alternatively. The minimum distance D8 may be 0 mm, 0.5 mm, 1.0 mm, 1.5 mm, 2.0 mm, 2.5 mm, or 3.0 mm.

[0146] In some embodiments, each of the DTCs 300 includes: a semiconductor substrate 310 (having an active surface S310f and a bottom surface S310b opposite to the active surface S310f), a capacitor 320 embedded in the semiconductor substrate 310, a plurality of connection pads 330 disposed on the capacitor 320 and electrically coupled to the capacitor 320, a passivation layer 340 formed on the connection pads 330 and above the semiconductor substrate 310, a post-passivation layer 350 formed on the connection pads 330 and the passivation layer 340, a plurality of connection vias 360 formed on the connection pads 330 and electrically connected to the connection pads 330 and located on the post-passivation layer 350, a protection layer 370 covering the connection vias 360 and the post-passivation layer 350, and at least one conductive pillar 380 formed (embedded) in the semiconductor substrate 310 near the capacitor 320 and electrically connected to a corresponding one of the connection pads 330. In some embodiments, each of the DTCs 300 further includes an isolation layer (not shown) disposed on the semiconductor substrate 310 and laterally covering the end portion of the conductive pillar 380, wherein the semiconductor substrate 310 is located between the isolation layer and the connection pad 330. Alternatively, the connection via 360 and the protection layer 370 may be omitted. Figure 4 and Fig.13As shown in , the conductive pillars 380 of the DTC 300 penetrate through the semiconductor substrate 310. In some embodiments, each of the conductive pillars 380 is covered by a liner 390. In addition, a dielectric liner (not shown) (e.g., silicon nitride, oxide, polymer, combination thereof, etc.) may be further formed between the liner 390 and the semiconductor substrate 310 as needed. As an alternative, the conductive pillars 380 of the DTC 300 do not penetrate through the semiconductor substrate 310. The formation, materials, and details of the DTC 300 (e.g., the semiconductor substrate 310, the connection pads 330, the connection vias 360, the protection layer 370, the conductive pillars 380, the liner 390, the optional dielectric liner, and the isolation layer) are similar to or substantially the same as those of the DTC 300. Figure 1 The formation, materials and details of the semiconductor die 400 (e.g., semiconductor substrate 410, connection pads 440, connection vias 450, protection layer 460, conductive pillars 470, liner 480, optional dielectric liner and isolation layer) described in the foregoing are not described in detail herein and are therefore not described in detail herein for the sake of brevity. The number of capacitors 320, the number of connection pads 330, the number of connection vias 360 and the number of conductive pillars 380 are not limited to the described embodiments and may be selected and specified based on requirements and design layout.

[0147] like Figure 4 As shown in, for example, in each DTC 300, a capacitor 320 is electrically connected to a connection through hole 360 ​​via a connection pad 330, and a conductive column 380 is electrically connected to the connection through hole 360 ​​via the connection pad 330, wherein the capacitor 320 is electrically connected to the conductive column 380 via the connection pad 330. In some embodiments, the capacitor 320 includes a conductive layer 322, a conductive layer 326, and a dielectric layer 324 sandwiched between the conductive layer 322 and the conductive layer 326. In one embodiment, the capacitor 320 may be a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor. In some embodiments, the capacitance density of the capacitor 320 is greater than or substantially equal to 100 nF / mm2. 2). Due to the capacitor 320, the power integrity and system performance of the semiconductor die to be electrically connected to the capacitor 320 later will be improved. In some embodiments, the passivation layer 340 and / or the post-passivation layer 350 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials. In some alternative embodiments, the passivation layer 340 and / or the post-passivation layer 350 may be a PI layer, a PBO layer, or a dielectric layer formed of other suitable polymers. It should be noted that in some alternative embodiments, the formation of each of the passivation layer 340 and / or the post-passivation layer 350 is independently optional. In one embodiment, the material of the passivation layer 340, the material of the post-passivation layer 350, and the material of the protective layer 370 may be the same. In an alternative embodiment, the material of the passivation layer 340, the material of the post-passivation layer 350, and the material of the protective layer 370 may be different. The type, size, and shape of each of the DTC 300 are independent of each other and can be selected and designed based on requirements and design layout, and the present disclosure is not limited thereto.

[0148] For example, in Fig.13 In the top view shown, each of the DTCs 300 is arranged in the peripheral region PR and is separated from an immediately adjacent device (e.g., another semiconductor die 100, another dummy die 200, or another DTC 300) by a horizontal distance D5 (e.g., the shortest distance measured along the direction X) and a vertical distance D6 (e.g., the shortest distance measured along the direction Y). The horizontal distance D5 may be approximately in the range from 0.5 microns to 100 microns (e.g., about 80 microns), but other suitable horizontal distances may be utilized alternatively. The vertical distance D6 may be approximately in the range from 0.5 microns to 100 microns (e.g., about 80 microns), but other suitable vertical distances may be utilized alternatively. In some embodiments, each of the DTCs 300 is a minimum distance D9 from an edge (e.g., sidewall SW1) of the semiconductor package SP1. The minimum distance D9 may be approximately in the range from 0 mm to 3 mm, but other suitable minimum distances may be utilized alternatively. The minimum distance D9 may be 0 mm, 0.5 mm, 1.0 mm, 1.5 mm, 2.0 mm, 2.5 mm, or 3.0 mm. In addition, the DTC 300 may be a small die or chiplet having a die area greater than or substantially equal to about 0.0001 mm2 and less than or substantially equal to about 5.0 mm2 (compared to the semiconductor die 100 disposed in the device region DR). The DTC 300 may have a die area from about 1 mm2 to about 5 mm2.

[0149] In some embodiments, after placing the semiconductor die 100, the dummy die 200, and the DTC 300, a bonding process is performed to bond the semiconductor die 100 (e.g., 100B and 100C) to a corresponding one of the semiconductor dies 400 overlapping the semiconductor die 100 along the stacking direction Z. For example, the semiconductor dies 100 (e.g., semiconductor dies 100B, 100C) are electrically connected to each other and electrically communicate with each other via the semiconductor die 400. In the present disclosure, the semiconductor die 400 may be referred to as a bridge die (or bridge chip) or a semiconductor bridge die (or semiconductor bridge chip).

[0150] For example, the semiconductor die 100B and the semiconductor die 100C are bonded to the semiconductor die 400 by a bonding process including both metal-to-metal bonding and dielectric-to-dielectric bonding. Figure 4 As shown in , each of the semiconductor dies 100 (e.g., semiconductor dies 100B, 100C) is disposed on (e.g., physically contacts) the semiconductor die 400 (encapsulated in the insulating encapsulation body 500a) and electrically connected to the semiconductor die 400. In some embodiments, as Figure 4 and Fig.14 As shown in , the end surface (not labeled) of the conductive pillar 170 in each of the semiconductor dies 100 (e.g., semiconductor dies 100B, 100C) and the top surface S450t of the connecting via 450 of the semiconductor die 400 abut against each other and are bonded together by direct metal-to-metal bonding (e.g., copper-to-copper bonding). Figure 4 and Fig.14 As shown in , the surface (not marked) of the isolation layer 90 (covering the end portion of the conductive pillar 170 in the lateral direction and located on the semiconductor substrate 110) in each of the semiconductor dies 100 (e.g., semiconductor dies 100B, 100C) and the top surface S460t of the protection layer 460 of the semiconductor die 400 abut against each other and are bonded together by, for example, direct dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding, nitride-to-nitride bonding, or oxide-to-nitride bonding). In such an embodiment, the bonding interface IF1 between the semiconductor die 100 (e.g., semiconductor die 100B, 100C) and the semiconductor die 400 includes a (direct) dielectric-to-dielectric bonding interface (e.g., oxide-to-oxide bonding interface, nitride-to-nitride bonding interface, or oxide-to-nitride bonding interface) and a (direct) metal-to-metal bonding interface (e.g., copper-to-copper bonding interface).

[0151] It should be noted that the above-described bonding methods are merely examples and are not intended to be limiting. Figure 4 and Fig.14, there may be an offset between the sidewalls of the connecting via 450 and the sidewalls of the conductive pillar 170 overlying the connecting via 450. Since one of the connecting via 450 and the conductive pillar 170 may have a larger bonding surface than the other, direct metal-to-metal bonding may be achieved even in the event of misalignment, thereby ensuring the reliability of the electrical connection between the semiconductor die 100 (e.g., semiconductor die 100B, 100C) and the semiconductor die 400. As such, for some embodiments, the protection layer 460 directly adjacent to the connecting via 450 is bonded to a portion of each of the conductive pillars 170 (e.g., dielectric-to-metal bonding), or the isolation layer 90 directly adjacent to the conductive pillar 170 is bonded to a portion of each of the connecting via 450 (e.g., dielectric-to-metal bonding, see Figure 4 and Fig.14 ).

[0152] However, the present disclosure is not limited thereto; as another option, the semiconductor die 100 (eg, semiconductor die 100B, 100C) may be bonded to the semiconductor die 400 by flip-chip bonding, see Fig.15 In an alternative embodiment, there are multiple joints 50A between the conductive pillars 170 of each of the semiconductor dies 100 (e.g., semiconductor dies 100B, 100C) and the connecting through holes 450 of the semiconductor die 400 for mechanically and electrically connecting the semiconductor dies 100 (e.g., semiconductor dies 100B, 100C) and the semiconductor die 400. The joints 50A include microbumps, metal pillars, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG), controlled collapse chip connection (C4) bumps (e.g., which may have a size of but not limited to about 80 microns), ball grid array (BGA) bumps or BGA balls (e.g., which may have a size of but not limited to about 400 microns), solder balls, or similar components. The present disclosure is not limited thereto. When solder is used, the solder may include eutectic solder or non-eutectic solder. The solder may contain lead or may not contain lead, and may contain Sn-Ag, Sn-Cu, Sn-Ag-Cu, or similar materials. When solder is used, joint 50A may be referred to as a solder joint or solder region. In such alternative embodiments, an underfill (not shown) may be applied as needed to surround the sidewalls of joint 50A to ensure bonding strength between semiconductor die 100 (e.g., semiconductor die 100B, 100C) and semiconductor die 400. The underfill may be omitted.

[0153] Reference Figure 5 In some embodiments, the semiconductor die 100, the dummy die 200, and the DTC 300 are encapsulated in an insulating material. In some embodiments, an insulating encapsulant 500n is conformally formed on the semiconductor die 100, the dummy die 200, and the DTC 300 and on the carrier 101, wherein the semiconductor die 100, the dummy die 200, the DTC 300, and the insulating encapsulant 500a exposed by the semiconductor die 100, the dummy die 200, and the DTC 300 are completely covered by the insulating encapsulant 500n. The formation and material of the insulating encapsulant 500n are similar to or substantially the same as those of Figure 2 The formation and materials of the insulating enclosure 500m described in , and therefore, for the sake of brevity, are not repeated herein. Figure 5 Combination Fig.13 As shown, the top surface S100 of the semiconductor die 100 , the top surface S200 of the dummy die 200 , and the top surface S300 of the DTC 300 are not exposed in a touchable manner by the insulating encapsulation 500 n .

[0154] In some embodiments, Figure 5 As shown in , the material of the insulating enclosure 500n is the same as the material of the insulating enclosure 500m, wherein there is no clear interface between the insulating enclosure 500n and the insulating enclosure 500a. Alternatively, the material of the insulating enclosure 500n may be different from the material of the insulating enclosure 500m, wherein there will be a clear interface between the insulating enclosure 500n and the insulating enclosure 500a.

[0155] Reference Figure 5 and Figure 6 In some embodiments, a planarization process is performed on the insulating encapsulant 500n to form an insulating encapsulant 500b exposing the semiconductor die 100, the dummy die 200, and the DTC 300. For example, a portion of the insulating encapsulant 500n is removed to form the insulating encapsulant 500b, the insulating encapsulant 500b having a top surface composed of a substantially inclined flat surface S500t3 at the peripheral region PR and a substantially flat surface S500t4 surrounded (or defined) by the substantially inclined flat surface S500t3 at the device region DR, wherein the substantially inclined flat surface S500t3 is connected to the substantially flat surface S500t4 and the (substantially vertical) sidewalls of the insulating encapsulant 500b (the sidewalls are Fig.10 and Fig.13 ). Figure 6 and Fig.13As shown in, for example, the substantially flat surface S500t4 is connected to the substantially inclined flat surface S500t3 and is surrounded by the substantially inclined flat surface S500t3. The substantially flat surface S500t4 can be considered as a substantially horizontal flat surface extending along the XY plane. In this case, the substantially flat surface S500t4 exposes the semiconductor die 100 in a touchable manner. For example, the top surface S150t of the connection through hole 150 of each of the semiconductor die 100 and the top surface S160t of the protection layer 160 are substantially flush with the substantially flat surface S500t4 of the insulating encapsulation 500b. In other words, the top surface S150t of the connection through hole 150 of the semiconductor die 100 and the top surface S160t of the protection layer 160 are substantially coplanar with the substantially flat surface S500t4 of the insulating encapsulation 500b. For each semiconductor die 100, the top surface S150t of the connecting through hole 150 and the top surface S160t of the protective layer 160 are collectively referred to as the front side or front side surface S100t, and the bottom surface S110b is referred to as the bottom side, the back side, the bottom side surface or the back side surface S100b, wherein the bottom side S100b is opposite to the front side S100t in the stacking direction Z.

[0156] In some cases, the substantially flat surface S500t4 further partially exposes the dummy die 200 and / or the DTC 300 in an accessible manner. For example, the top surface S250t of some connecting vias 250 of each of the dummy die 200 and the top surface S260t of a portion of the protection layer 260 and / or the top surface S360t of some connecting vias 360 of each of the DTC 300 and the top surface S370t of a portion of the protection layer 370 are substantially flush with the substantially flat surface S500t4 of the insulating encapsulation 500b. In other words, the top surface S250t of some of the connecting vias 250 of each of the dummy dies 200 and the top surface S260t of the portion of the protective layer 260 and / or the top surface S360t of some of the connecting vias 360 of each of the DTCs 300 and the top surface S370t of the portion of the protective layer 370 are substantially coplanar with the substantially flat surface S500t4 of the insulating encapsulation 500b. For each dummy die 200, the top surface S250t of the connecting vias 250 and the top surface S260t of the protective layer 260 are collectively referred to as the front side or the front side surface S200t, and the bottom surface S210b is referred to as the bottom side, the back side, the bottom side surface or the back side surface S200b, wherein the bottom side S200b is opposite to the front side S200t in the stacking direction Z. The front side S200t may be uneven. On the other hand, for each DTC 300, the top surface S360t of the connecting through hole 360 ​​and the top surface S370t of the protection layer 370 are collectively referred to as the front side or the front side surface S300t, and the bottom surface S310b is referred to as the bottom side, the back side, the bottom side surface or the back side surface S300b, wherein the bottom side S300b is opposite to the front side S300t in the stacking direction Z. The front side S300t may be uneven.

[0157] On the other hand, the substantially inclined flat surface S500t3 can be considered as a bevel edge, wherein the insulating encapsulation body 500b has a thickness (not marked) that gradually decreases in the direction from the device region DR toward the sidewall SW1 of the semiconductor structure SP1 at the peripheral region PR. Such a bevel edge may be formed at or near the edge / sidewall of the object to be ground during the planarization process due to over-grinding / grinding or a lower metal (or pattern) density compared to the central region of the object to be ground (e.g., the semiconductor structure SP1). If it is considered that a semiconductor die (having an active device) is located at or near the edge / sidewall of the semiconductor structure SP1, such a semiconductor die will be damaged due to the presence of the bevel edge, which may result in abnormal functionality or loss of functionality. To avoid such damage, one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) may be employed at the peripheral region PR to serve as structural supports during the planarization (or thinning) process, whereby the resulting chamfered edge will terminate at / within the desired peripheral region PR without further extending into the device region DR. Therefore, since the presence of the dummy die 200 and / or the DTCs 300 improves the edge uniformity of the semiconductor structure SP1, the semiconductor die 100 formed in the device region DR defined by the desired peripheral region PR (where one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) will be protected from damage caused by the planarization (or thinning) process. That is, due to at least one of the dummy die 200 and the DTC 300, the substantially inclined flat surface S500t3 of the insulating encapsulation body 500b will terminate at the peripheral region PR (e.g., at the dummy die 200 and / or the DTC 300), thereby enhancing the reliability of the semiconductor structure SP1. Figure 6 As shown in FIG. 5 , the substantially flat surface S500t4 of the insulating encapsulation 500b extends into the peripheral region PR. Alternatively, the substantially flat surface S500t4 of the insulating encapsulation 500b may reach and terminate at the edge of the peripheral region PR.

[0158] After the planarization process, the semiconductor die 100, the dummy die 200, and the DTC 300 are exposed in a tangible manner through, for example, the insulating encapsulant 500b. In some embodiments, the sidewalls (not marked) of the semiconductor die 100, the sidewalls (not marked) of the dummy die 200, the sidewalls (not marked) of the DTC 300, and the insulating encapsulant 500a exposed through the semiconductor die 100, the dummy die 200, and the DTC 300 are still covered by the insulating encapsulant 500b. In this case, Figure 6 and Fig.13 As shown in FIG. 5 , the insulating encapsulation body 500 b covers the semiconductor die 100 , the dummy die 200 , and the DTC 300 in a lateral direction.

[0159] During the planarization process, the protective layer 160 of one or more semiconductor dies 100, the protective layer 260 of one or more dummy dies 200, and / or the protective layer 370 of one or more DTCs 300 may be further planarized. In addition to the protective layer, the connecting vias 150 of one or more semiconductor dies 100, the connecting vias 250 of one or more dummy dies 200, and / or the connecting vias 360 of one or more DTCs 300 may be further planarized. In some embodiments, the planarization process may include a grinding process, a CMP process, an etching process, or a combination thereof. The etching process may include dry etching, wet etching, or a combination thereof. After the planarization process, a cleaning process may be performed as needed, for example, to clean and remove the residues generated by the planarization process. However, the present disclosure is not limited thereto, and the planarization process may be performed by any other suitable method. In some embodiments, the insulating enclosure 500a and the insulating enclosure 500b may be collectively referred to as an insulating enclosure 500. In some embodiments, the thickness of the insulating enclosure 500 at its edge is less than the thickness of the insulating enclosure 500 at its center. The insulating enclosure 500a, the insulating enclosure 500b, and the insulating enclosure 500 may be referred to as enclosures or encapsulating insulators, respectively.

[0160] Reference Figure 7In some embodiments, a wafer structure 600m is formed on the insulating encapsulation 500b and on the carrier 101. In some embodiments, the wafer structure 600m includes one or more dielectric layers 610 (e.g., 610A, 610B, and 610C), one or more seed layers 620 (e.g., 620A and 620B), and one or more wiring layers 630 (e.g., 630A and 630B). In some embodiments, each wiring layer 630 includes a line portion 630t extending along a horizontal direction (e.g., direction X or direction Y), a through-hole portion 630v extending along a vertical direction (e.g., direction Z), and / or a combination thereof. One seed layer 620 and a corresponding one wiring layer 630 overlying the one seed layer 620 may be collectively referred to as a metallization layer or a redistribution layer for a wiring function. In some embodiments, in the wafer structure 600m, the dielectric layer (e.g., 610) and the metallization layer (e.g., 620 and 630) are arranged alternately. However, in the present disclosure, the number of dielectric layers 610, the number of seed layers 620, and the number of wiring layers 630 are not limited to Figure 7 The number shown in , and can be selected and specified based on requirements and design layout.

[0161] In some embodiments, the chip structure 600m can be formed by, but not limited to, the following methods: forming a first dielectric material blanket layer on the insulating package 500b; patterning the first dielectric material blanket layer to form a dielectric layer 610A, the dielectric layer 610A having a plurality of first openings (not marked), the plurality of first openings penetrating the dielectric layer 610A and exposing the connection vias 150 of the semiconductor die 100 and the connection vias 360 of the DTC 300 in an accessible manner; forming a first seed layer material blanket layer on the dielectric layer 610A, the first seed layer material blanket layer extending into the first openings to be lined on the first openings and in contact with the exposed connection vias 150 and DTC 300 of the semiconductor die 100. 300; forming a first conductive material blanket layer on the first seed layer material blanket layer; patterning the first conductive material blanket layer to form a wiring layer 630A; using the wiring layer 630A as an etching mask to pattern the first seed layer material blanket layer and form a seed layer 620A; forming a second dielectric layer material blanket layer on the wiring layer 630A, the seed layer 620A and the dielectric layer 610A; patterning the second dielectric material blanket layer to form a dielectric layer 610B, the dielectric layer 610B having a plurality of second openings (not marked), the plurality of second openings penetrating the dielectric layer 610B and The top surface of the wiring layer 630A is exposed in a tangible manner; a second blanket layer of seed layer material is formed on the dielectric layer 610B, the second blanket layer of seed layer material extends into the second opening to line the second opening and contact the exposed wiring layer 630A; a second blanket layer of conductive material is formed on the second blanket layer of seed layer material; the second blanket layer of conductive material is patterned to form the wiring layer 630B; the second blanket layer of seed layer material is patterned using the wiring layer 630B as an etching mask and forms the seed layer 620B; a third blanket layer of dielectric material is formed on the wiring layer 630B, the seed layer 620B and the dielectric layer 610B. Thus, the wafer structure 600m is manufactured.

[0162] The material of each of dielectric layers 610A, 610B, and 610C may be PI, PBO, BCB, nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), PSG, BSG, BPSG, combinations thereof, or similar materials that can be patterned using photolithography and / or etching processes. The first dielectric material blanket layer, the second dielectric material blanket layer, and / or the third dielectric material blanket layer may be formed by suitable fabrication techniques such as spin coating, CVD (e.g., PECVD), or similar processes. In one embodiment, the material of dielectric layer 610A, the material of dielectric layer 610B, and the material of dielectric layer 610C are the same as each other. Alternatively, the material of dielectric layer 610A, the material of dielectric layer 610B, and the material of dielectric layer 610C may be partially or entirely different from each other.

[0163] The seed layers 620A and 620B are each referred to as metal layers, and may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. For example, the seed layers 620A and 620B may each be or may include a titanium layer and a copper layer located on the titanium layer. The first seed layer material blanket layer and / or the second seed layer material blanket layer may be formed in the form of a blanket layer made of a metal or metal alloy material, but the present disclosure is not limited thereto. The material of each of the first seed layer material blanket layer and / or the second seed layer material blanket layer may include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like, which may be formed using, for example, sputtering, physical vapor deposition (PVD), or the like. The first seed layer material blanket layer and / or the second seed layer material blanket layer may be patterned by etching, such as a dry etching process, a wet etching process, or a combination thereof, but the present disclosure is not limited thereto. In one embodiment, the material of the seed layer 620A and the material of the seed layer 620B are the same as each other. Alternatively, the material of the seed layer 620A and the material of the seed layer 620B may be different from each other.

[0164] The material of each of the first conductive material blanket layer used to form the wiring layer 630A and the second conductive material blanket layer used to form the wiring layer 630B can be made of a conductive material (e.g., copper, copper alloy, aluminum, aluminum alloy, or a combination thereof) formed by electroplating or deposition, and the conductive material can be patterned using photolithography and etching processes to form a plurality of conductive patterns / conductive segments. In some embodiments, each of the conductive patterns / conductive segments includes a line portion 630t extending along a horizontal direction (e.g., direction X and / or direction Y) and / or a through-hole portion 630v connected to the line portion 630t and extending along a vertical direction (e.g., direction Z) in addition to the line portion 630t extending along the horizontal direction (e.g., direction X and / or direction Y). In one embodiment, the material of the wiring layer 630A and the material of the wiring layer 630B are the same as each other. Alternatively, the material of the wiring layer 630A and the material of the wiring layer 630B may be different from each other.

[0165] However, as another option, the chip structure 600m may be formed on the insulating package 500 by lamination. The present disclosure is not limited thereto.

[0166] like Figure 7As shown in FIG. 5 , for example, due to the substantially inclined flat surface S500t3, the top surface (not labeled) of the wafer structure 600m may not have sufficient planarity to facilitate the formation of components formed later. In other words, it can be considered that the wafer structure 600m has a warpage problem. A planarization process can be further performed on the wafer structure 600m to facilitate the manufacture of the semiconductor structure SP1.

[0167] Reference Figure 8 In some embodiments, a planarization process is performed on the wafer structure 600m to form a wafer structure 600 having a surface S600t, the surface S600t being composed of the top surface S610t of the dielectric layer 610C and the top surface S630t of the wiring layer 630 exposed by the dielectric layer 610C. For example, the surface S600t of the wafer structure 600 is flattened and has a high degree of planarity. In other words, the surface S600t of the wafer structure 600 can be referred to as a flat surface or a substantially horizontal flat surface. The planarization process may include a grinding process, a CMP process, an etching process, or a combination thereof. The etching process may include dry etching, wet etching, or a combination thereof. After the planarization process, a cleaning process may be performed as needed, for example, to clean and remove the residues generated by the planarization process. However, the present disclosure is not limited thereto, and the planarization process may be performed by any other suitable method. The wafer structure 600 may be referred to as a wafer-level circuit structure or a wafer circuit structure.

[0168] like Figure 8 and Fig.13 As shown in , in some embodiments, the semiconductor die 100 and the DTC 300 are electrically connected to the wafer structure 600, and the dummy die 200 is electrically isolated from the wafer structure 600, the semiconductor die 100, 400, and the DTC 300. In some embodiments, the semiconductor die 400 is electrically connected to the wafer structure 600 via the semiconductor die (e.g., 100B and 100C) electrically connected to the semiconductor die 400. In some embodiments, the DTC 300 is electrically coupled to one or more semiconductor dies 100 via the wafer structure 600. Or on the other hand, one or more semiconductor dies 100 are electrically coupled to one or more DTCs 300 via the wafer structure 600. The present disclosure is not limited thereto. The DTC 300 may be electrically coupled to one or more semiconductor dies 400 via the semiconductor die 100 electrically connected to the DTC 300 and via the wafer structure 600.

[0169] like Figure 8As shown in , for example, the thickness of the wafer structure 600 at its edge is greater than the thickness of the wafer structure 600 at its center. In addition, one metallization layer (e.g., 620A and 630A) and the dielectric layer covering the one metallization layer in the lateral direction are considered as the first build-up layer of the wafer structure 600, and another metallization layer (e.g., 620B and 630B) and the dielectric layer covering the other metallization layer in the lateral direction are considered as the second build-up layer of the wafer structure 600. The number of build-up layers of the wafer structure 600 can be selected and specified based on requirements and design layout, and is not limited thereto.

[0170] Reference Fig. 9 In some embodiments, a redistribution wiring structure 700 electrically connected to the chip structure 600 is formed on the chip structure 600. In some embodiments, the redistribution wiring structure 700 includes one or more dielectric layers 710 (e.g., 710A, 710B, and 710C), one or more seed layers 720 (e.g., 720A, 720B, and 720C), one or more patterned conductive layers 730 (e.g., 730A, 730B, and 730C), and a passivation layer 740. In some embodiments, each patterned conductive layer 730 includes a line portion 730t extending along a horizontal direction (e.g., direction X or direction Y), a through-hole portion 730v extending along a vertical direction (e.g., direction Z), and / or a combination thereof. A seed layer 720 and a corresponding patterned conductive layer 730 overlying the seed layer 720 may be collectively referred to as a metallization layer or a redistribution layer for providing a wiring function. In some embodiments, in the redistribution wiring structure 700, the dielectric layer (e.g., 710) and the metallization layer (e.g., 720 and 730) are arranged alternately, and the passivation layer (e.g., 740) is disposed on the topmost layer (e.g., 710C) of the dielectric layer (e.g., 710). Fig. 9 As shown in FIG. 1 , for example, the passivation layer 740 includes a plurality of openings OP that penetrate through the passivation layer 740 and expose a surface S730t of some portions of the topmost layer (e.g., 730C) of the patterned conductive layer 730 for external connection. In the present disclosure, the number of layers of the dielectric layer 710, the number of layers of the seed layer 720, and the number of layers of the patterned conductive layer 730 are not limited to Fig. 9 The number shown in , and can be selected and specified based on requirements and design layout.

[0171] In some embodiments, the redistribution wiring structure 700 may be formed by, but not limited to, the following methods: forming a fourth dielectric material blanket layer on the chip structure 600; patterning the fourth dielectric material blanket layer to form a dielectric layer 710A, the dielectric layer 710A having a plurality of fourth openings (not labeled), the plurality of fourth openings penetrating the dielectric layer 710A and exposing portions of the topmost layer (e.g., 630B) of the wiring layer 630 of the chip structure 600 in an accessible manner; forming a fourth seed layer material blanket layer on the dielectric layer 710A, the fourth seed layer material blanket layer extending into the fourth openings to line the fourth openings and to contact the topmost layer (e.g., 630B) of the wiring layer 630 of the chip structure 600; ) of the dielectric layer 710A; forming a fourth conductive material blanket layer on the fourth seed layer material blanket layer; patterning the fourth conductive material blanket layer to form a patterned conductive layer 730A; using the patterned conductive layer 730A as an etching mask to pattern the fourth seed layer material blanket layer and form a seed layer 720A; forming a fifth dielectric material blanket layer on the patterned conductive layer 730A, the seed layer 720A and the dielectric layer 710A; patterning the fifth dielectric material blanket layer to form a dielectric layer 710B, the dielectric layer 710B having a plurality of fifth openings (not marked), the plurality of fifth openings penetrating the dielectric layer 710B and exposing the patterned conductive layer 730A in an accessible manner. The top surface is shown; forming a fifth blanket layer of seed layer material on the dielectric layer 710B, the fifth blanket layer of seed layer material extending into the fifth opening to line the fifth opening and contact the exposed patterned conductive layer 730A; forming a fifth blanket layer of conductive material on the fifth blanket layer of seed layer material; patterning the fifth blanket layer of conductive material to form a patterned conductive layer 730B; using the patterned conductive layer 730B as an etching mask to pattern the fifth blanket layer of seed layer material and form a seed layer 720B; forming a sixth blanket layer of dielectric material on the patterned conductive layer 730B, the seed layer 720B and the dielectric layer 710B; patterning the sixth blanket layer of dielectric material to form a dielectric layer 710 C, the dielectric layer 710C has a plurality of sixth openings (not labeled), the plurality of sixth openings penetrate through the dielectric layer 710C and expose the top surface of the patterned conductive layer 730B in an accessible manner; a sixth seed layer material blanket is formed on the dielectric layer 710C, the sixth seed layer material blanket extends into the sixth openings to line the sixth openings and contact the exposed patterned conductive layer 730B; a sixth conductive material blanket is formed on the sixth seed layer material blanket; the sixth conductive material blanket is patterned to form the patterned conductive layer 730C; the patterned conductive layer 730C is used as an etching mask to pattern the sixth seed layer material blanket and form the seed layer 720C;A seventh dielectric material blanket layer is formed on the patterned conductive layer 730C, the seed layer 720C and the dielectric layer 710C; and the seventh dielectric material blanket layer is patterned to form a passivation layer 740, the passivation layer 740 having a plurality of openings OP, the plurality of openings OP penetrating through the passivation layer 740 and exposing the top surface (surface S730t) of the patterned conductive layer 730C in a touchable manner. Thus, a redistribution wiring structure 700 is manufactured. The redistribution wiring structure 700 can be formed on the insulating package 500 by a single damascene process or a dual damascene process. The present disclosure is not limited thereto. ;

[0172] The material of each of the dielectric layers 710A, 710B, 710C and the passivation layer 740 may be PI, PBO, BCB, nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), PSG, BSG, BPSG, combinations thereof, or similar materials that can be patterned using photolithography and / or etching processes. The fourth dielectric material blanket layer, the fifth dielectric material blanket layer, the sixth dielectric material blanket layer, and / or the seventh dielectric material blanket layer may be formed by suitable fabrication techniques such as spin coating, CVD (e.g., PECVD), or similar processes. In one embodiment, the material of the dielectric layer 710A, the material of the dielectric layer 710B, the material of the dielectric layer 710C, and the material of the passivation layer 740 are the same as one another. Alternatively, the material of the dielectric layer 710A, the material of the dielectric layer 710B, the material of the dielectric layer 710C, and the material of the passivation layer 740 may be partially or entirely different from one another. In some embodiments, the material of dielectric layer 710A, the material of dielectric layer 710B, the material of dielectric layer 710C, and the material of passivation layer 740 are different from the material of dielectric layer 610A, the material of dielectric layer 610B, and the material of dielectric layer 610C.

[0173] Seed layers 720A, 720B, and 720C are each referred to as metal layers, and may be a single layer or a composite layer including a plurality of sublayers formed of different materials. For example, seed layers 720A, 720B, and 720C may each be or may include a titanium layer and a copper layer located on the titanium layer. The fourth seed layer material blanket layer, the fifth seed layer material blanket layer, and / or the sixth seed layer material blanket layer may be formed in the form of a blanket layer made of a metal or metal alloy material, but the present disclosure is not limited thereto. The material of each of the fourth seed layer material blanket layer, the fifth seed layer material blanket layer, and / or the sixth seed layer material blanket layer may include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like, which may be formed using, for example, sputtering, PVD, or the like. The fourth seed layer material blanket layer, the fifth seed layer material blanket layer, and / or the sixth seed layer material blanket layer may be patterned by etching (e.g., a dry etching process, a wet etching process, or a combination thereof); the present disclosure is not limited thereto. In one embodiment, the material of seed layer 720A, the material of seed layer 720B, and the material of seed layer 720C are the same as one another. Alternatively, the material of seed layer 720A, the material of seed layer 720B, and the material of seed layer 720C may be different from one another. In some embodiments, the material of seed layer 720A, the material of seed layer 720B, and the material of seed layer 720C are the same as the material of seed layer 620A and the material of seed layer 620B. Alternatively, the material of seed layer 720A, the material of seed layer 720B, and the material of seed layer 720C may be different from the material of seed layer 620A and the material of seed layer 620B.

[0174] The material of each of the fourth conductive material blanket layer for forming the patterned conductive layer 730A, the fifth conductive material blanket layer for forming the patterned conductive layer 730B, and / or the sixth conductive material blanket layer for forming the patterned conductive layer 730C may be made of a conductive material (e.g., copper, copper alloy, aluminum, aluminum alloy, or a combination thereof) formed by electroplating or deposition, which may be patterned using photolithography and etching processes to form a plurality of conductive patterns / conductive segments. In some embodiments, each of the conductive patterns / conductive segments includes a line portion 730t extending along a horizontal direction (e.g., direction X and / or direction Y) and / or includes a through-hole portion 730v connected to the line portion 730t and extending along a vertical direction (e.g., direction Z) in addition to the line portion 730t extending along the horizontal direction (e.g., direction X and / or direction Y). In one embodiment, the material of the patterned conductive layer 730A, the material of the patterned conductive layer 730B, and the material of the patterned conductive layer 730C are the same as each other. Alternatively, the material of the patterned conductive layer 730A, the material of the patterned conductive layer 730B, and the material of the patterned conductive layer 730C may be different from each other. In some embodiments, the material of the patterned conductive layer 730A, the material of the patterned conductive layer 730B, and the material of the patterned conductive layer 730C are the same as the material of the wiring layer 630A and the material of the wiring layer 630B. Alternatively, the material of the patterned conductive layer 730A, the material of the patterned conductive layer 730B, and the material of the patterned conductive layer 730C may be different from the material of the wiring layer 630A and the material of the wiring layer 630B.

[0175] like Fig. 9 As shown in , for example, the redistribution wiring structure 700 is electrically connected to the semiconductor die 100 and the DTC 300 via the wafer structure 600. In some embodiments, the redistribution wiring structure 700 is electrically connected to the semiconductor die 400 via the wafer structure 600 and the semiconductor die 100 electrically connected to the semiconductor die 400. In some embodiments, the redistribution wiring structure 700 is electrically isolated from the dummy die 200. In addition, one metallization layer (e.g., 720A and 730A) and a dielectric layer covering the one metallization layer in the lateral direction are considered to be a first buildup layer of the redistribution wiring structure 700, another metallization layer (e.g., 720B and 730B) and a dielectric layer covering the other metallization layer in the lateral direction are considered to be a second buildup layer of the redistribution wiring structure 700, and another metallization layer (e.g., 720C and 730C) and a dielectric layer covering the other metallization layer in the lateral direction are considered to be a third buildup layer of the redistribution wiring structure 700. The number of stacking layers of the redistribution wiring structure 700 may be selected and specified based on requirements and design layout, and is not limited thereto.

[0176] Reference Fig.10 In some embodiments, a plurality of under-ball metallurgy (UBM) patterns 800 and a plurality of conductive terminals 900 are sequentially formed on the redistribution wiring structure 700. In some embodiments, each of the UBM patterns 800 is located between a corresponding one of the conductive terminals 900 and the passivation layer 740 of the redistribution wiring structure 700. For example, the UBM pattern 800 is disposed on the passivation layer 740 and further extends into the opening OP formed in the passivation layer 740 to make (physical) contact with the patterned conductive layer 730C exposed from the opening OP, thereby being electrically connected to the patterned conductive layer 730C, and the conductive terminal 900 is disposed on the UBM pattern 800 (for example, makes physical contact with the UBM pattern 800) and is electrically connected to the UBM pattern 800. The bonding strength between the conductive terminal 900 and the passivation layer 740 of the redistribution wiring structure 700 is enhanced due to the UBM pattern 800.

[0177] In some embodiments, the UBM pattern 800 is physically and electrically connected to the redistribution wiring structure 700. In some embodiments, the conductive terminal 900 is electrically coupled to the redistribution wiring structure 700 via the UBM pattern 800. In some embodiments, the conductive terminal 900 is electrically coupled to the wafer structure 600 via the UBM pattern 800 and the redistribution wiring structure 700. In some embodiments, some of the conductive terminals 900 are electrically coupled to the semiconductor die 100 via some of the UBM patterns 800, the redistribution wiring structure 700, and the wafer structure 600. In addition, some of the conductive terminals 900 may be electrically coupled to the DTC 300 via some of the UBM patterns 800, the redistribution wiring structure 700, and the wafer structure 600. In some embodiments, the conductive terminal 900 is electrically isolated from the dummy die 200. In some embodiments, some of the conductive terminals 900 are electrically coupled to the semiconductor die 400 via some of the UBM patterns 800 , the redistribution wiring structure 700 , the wafer structure 600 , and the semiconductor die 100 electrically connected to the semiconductor die 400 .

[0178] In some embodiments, the UBM pattern 800 is made of a metal layer (including a single layer) or a metallization layer (including a composite layer having multiple sub-layers formed of different materials). In some embodiments, the UBM pattern 800 includes copper, nickel, molybdenum, titanium, tungsten, titanium nitride, titanium tungsten, a combination thereof, or a similar material. The UBM pattern 800 may include a titanium layer and a copper layer located on the titanium layer. The UBM pattern 800 may be formed using electroplating, sputtering, PVD, or a similar method. For example, the UBM pattern 800 is conformally formed on the passivation layer 740 by sputtering so that the UBM pattern 800 extends on the outermost surface of the passivation layer 740 and further extends into the opening OP formed in the passivation layer 740, and thus makes physical contact with the surface S730t of the patterned conductive layer 730C exposed by the opening OP formed in the passivation layer 740. The UBM patterns 800 are electrically isolated from each other. The number of the UBM patterns 800 may not be limited in the present disclosure, and may correspond to the number of portions of the patterned conductive layer 730C exposed by the openings OP formed in the passivation layer 740 .

[0179] In some embodiments, the conductive terminal 900 is physically and electrically connected to the UBM pattern 800, and is electrically coupled to the redistribution wiring structure 700 via the UBM pattern 800. In some embodiments, the conductive terminal 900 is disposed on the UBM pattern 800 by a ball implantation process or a reflow process. For example, the conductive terminal 900 includes a microbump, a metal column, a bump formed by electroless nickel palladium immersion gold (ENEPIG), a controlled collapse chip connection (C4) bump (e.g., it may have a size of but not limited to about 80 microns), a ball grid array (BGA) bump or a BGA ball (e.g., it may have a size of but not limited to about 400 microns), a solder ball, or a similar component. The present disclosure is not limited thereto. The number of conductive terminals 900 is not limited to the drawings of the embodiments, and may be selected and specified based on demand and design requirements. The number of conductive terminals 900 may be controlled by adjusting the number of UBM patterns 800. When solder is used, the solder may include eutectic solder or non-eutectic solder. The solder may contain lead or may not contain lead, and may contain Sn-Ag, Sn-Cu, Sn-Ag-Cu or similar materials. The conductive terminal 900 may not contain solder. The conductive terminal 900 may be referred to as a conductor, input / output (I / O) terminal, conductive connector or conductive I / O terminal of the semiconductor structure SP1 for electrically connecting to an external component or component (e.g., an additional semiconductor package / device, a circuit substrate, an interposer, a capacitor, a power supply or the like). At this point, the semiconductor structure SP1 is manufactured. Fig.10 The semiconductor structure SP1 shown in FIG. 1 may be referred to as a system-on-wafer (SoW).

[0180] However, the present disclosure is not limited thereto. In some alternative embodiments, the UBM pattern 800 may be omitted. In such alternative embodiments, the conductive terminal 900 may be directly connected to the redistribution wiring structure 700 (e.g., the portion of the patterned conductive layer 730C exposed by the opening OP) (e.g., in physical contact with the redistribution wiring structure 700). In some other alternative embodiments, the conductive terminal 900 may be omitted. In some other alternative embodiments, the UBM pattern 800 and the conductive terminal 900 may be omitted.

[0181] In some embodiments, Fig.10 and Fig.13 As shown in the figure, the semiconductor structure SP1 includes: a first tier T1 of a semiconductor die or device (for example, including a semiconductor die 100, a dummy die 200 and a DTC 300), a second tier T2 of a semiconductor die or device stacked on the first tier of the semiconductor die or device (for example, including a semiconductor die 400), an insulating encapsulation body 50 including a first portion 500a of the second tier T2 that laterally encapsulates the semiconductor die or device and a second portion 500b of the first tier T1 that laterally encapsulates the semiconductor die or device, a chip structure 600 disposed on the first tier T1 of the semiconductor die or device, a redistribution wiring structure 700 disposed on the chip structure 600, and a conductive terminal 900 disposed on the redistribution wiring structure 700 via a UBM pattern 800. In an embodiment, the first step T1 of the semiconductor die or device is disposed between the wafer structure 600 and the second step T2 of the semiconductor die or device, the wafer structure 600 is disposed between the first step T1 of the semiconductor die or device and the redistribution wiring structure 700, and the redistribution wiring structure 700 is disposed between the wafer structure 600 and the conductive terminal 900. For example, the carrier 101 remains on the semiconductor structure SP1, and the second step T2 of the semiconductor die or device is disposed between the carrier 101 and the first step T1 of the semiconductor die or device, wherein the carrier 101 is used as a mechanical support structure. The carrier 101 may sometimes be further used as a heat dissipation component (or heat sink).

[0182] However, the present disclosure is not limited thereto. Alternatively, the carrier 101 may be thinned to form a carrier 101', see Fig.11 For example, the carrier 101' remaining on the semiconductor structure SP1' has a thickness sufficient to serve as a mechanical support structure. The carrier 101' may sometimes be used as a heat dissipation component (or heat sink). The overall thickness of the semiconductor structure SP1' is reduced due to the configuration of the carrier 101'.

[0183] Alternatively, the carrier 101 may be omitted, see Fig.12The semiconductor structure SP1 in the carrier 101 is removed from the second step T2 of the semiconductor die or device and the first portion 500a of the insulating encapsulation 500. For example, the second step T2 of the semiconductor die or device and the first portion 500a of the insulating encapsulation 500 are easily separated from the carrier 101 due to the peeling layer 102. In some embodiments, the carrier 101 is detached from the second step T2 of the semiconductor die or device and the first portion 500a of the insulating encapsulation 500 by a removal process. In some embodiments, the second step T2 of the semiconductor die or device and the surface of the first portion 500a of the insulating encapsulation 500 (for example, S400b and S500b) is exposed. In this case, the semiconductor die 400 is exposed in an accessible manner. For a non-limiting example, the carrier 101 and the peeling layer 102 are peeled off and then the carrier 101 and the peeling layer 102 are removed. In one embodiment, the peeling process is a laser peeling process. For another non-limiting example, the carrier 101 and the peeling layer 102 are removed by a grinding process. In one embodiment, the grinding process is a mechanical grinding process, a CMP process, an etching process or a combination thereof. During the removal step, before removing the carrier 101 and the peeling layer 102, an additional holding device (not shown) is used to hold the conductive terminal 900 in place. Fig.10 In some embodiments, the holding device is or includes an adhesive tape, a carrier film or a suction pad supported by a frame. The overall thickness of the semiconductor structure SP1 ″ is further reduced due to the removal of the carrier 101 .

[0184] In some embodiments, Fig.10 and Fig.14 As shown in FIG. 4 , the second level T2 of the semiconductor die or device includes only the semiconductor die 400. However, the present disclosure is not limited thereto. As another option, Fig.16As shown in , one or more semiconductor dies 100 may be included in a second level T2 of semiconductor dies or devices at a device region DR, wherein each of the semiconductor dies 100 included in the second level T2 of the semiconductor dies or devices may overlap with and be electrically connected to only one of the semiconductor dies 100 included in the first level T1 of the semiconductor dies or devices. In this case, the stacked two semiconductor dies 100 (which may have the same or different shapes / sizes / types) are referred to as a die having a stacked structure (which may be considered as a SoIC die as a whole). Alternatively or additionally (not shown), one or more dummy dies 200 may be included in the second level T2 of the semiconductor die or device at the peripheral region PR, wherein each of the dummy dies 200 included in the second level T2 of the semiconductor die or device may overlap with the dummy die 200 and / or the DTC 300 included in the first level T1 of the semiconductor die or device, or may not overlap with the dummy die 200 and / or the DTC 300 included in the first level T1 of the semiconductor die or device. Alternatively or additionally (not shown), one or more DTCs 300 may be included in the second level T2 of the semiconductor die or device at the peripheral region PR, wherein each of the DTCs 300 included in the second level T2 of the semiconductor die or device may overlap with the dummy die 200 and / or the DTCs 300 included in the first level T1 of the semiconductor die or device, or may not overlap with the dummy die 200 and / or the DTCs 300 included in the first level T1 of the semiconductor die or device. In this case, the two dummy dies 200 and / or DTCs 300 (which may have the same or different shapes / sizes / types) stacked are referred to as a component having a stacked structure.

[0185] In some embodiments, both the dummy die 200 and the DTC 300 are disposed in the peripheral region PR. However, the present disclosure is not limited thereto; alternatively, only the dummy die 200 is disposed in the peripheral region PR. Alternatively, only the DTC 300 is disposed in the peripheral region PR.

[0186] In some embodiments, multiple pairs of dummy dies 200 are disposed in the peripheral region PR. However, the present disclosure is not limited thereto; alternatively, in the presence of a DTC 300 or in the absence of a DTC 300 (thus indicated by a dotted box), only one pair of dummy dies 200 may be disposed in the peripheral region PR, see Fig.17 Alternatively, in the presence of the dummy die 200 or in the absence of the dummy die 200 (not shown), only one pair of DTCs 300 may be provided in the peripheral region PR.

[0187] In an alternative embodiment, in the presence or absence of the DTC 300 (thus indicated by the dashed box), only two pairs of dummy dies 200 are provided in the peripheral region PR, wherein the first pair of dummy dies 200 are located at two opposite ends of a first diameter line (e.g., diameter line DL1) passing through the center CT of the semiconductor package, and the second pair of dummy dies 200 are located at two opposite ends of a second diameter line (e.g., diameter line DL3) passing through the center CT of the semiconductor package, see Fig.18 The first diameter line (eg, diameter line DL1 ) may be substantially perpendicular to the second diameter line (eg, diameter line DL3 ).

[0188] In some alternative embodiments, in the presence or absence of the DTC 300 (thus indicated by the dashed box), more than two pairs of dummy dies 200 are arranged in the peripheral region PR, wherein the first pair of dummy dies 200 are located at two opposite ends of a first diameter line (e.g., diameter line DL1) passing through the center CT of the semiconductor package, the second pair of dummy dies 200 are located at two opposite ends of a second diameter line (e.g., diameter line DL3) passing through the center CT of the semiconductor package, and the remaining pairs of dummy dies 200 are located at two opposite ends of a third diameter line (e.g., diameter line DL5) passing through the center CT of the semiconductor package and two opposite ends of a fourth diameter line (e.g., diameter line DL6), see Fig.19 . The first diameter line (e.g., diameter line DL1) may be substantially perpendicular to the second diameter line (e.g., diameter line DL3), wherein the third diameter line (e.g., diameter line DL5) and the fourth diameter line (e.g., diameter line DL6) are respectively disposed between the first diameter line (e.g., diameter line DL1) and the second diameter line (e.g., diameter line DL3), and the first diameter line (e.g., diameter line DL1) is located between the third diameter line (e.g., diameter line DL5) and the fourth diameter line (e.g., diameter line DL6).

[0189] In still other alternative embodiments, with or without the DTC 300 (thus indicated by the dashed box), more than two pairs of dummy dies 200 are disposed in the peripheral region PR, wherein the dummy dies 200 are disposed along the edge of the semiconductor structure and thus surround the device region DR, see Fig. 20 In this case, two dummy dies 200 (referred to as a pair of dummy dies 200) are always disposed at two opposite ends at any (diameter) line passing through the center CT of the semiconductor package. It should be understood that in the present disclosure, the arrangement of the dummy dies 200 and the arrangement of the DTC 300 may be partially or completely interchanged.

[0190] In some embodiments, the semiconductor structure does not undergo a sawing (or singulation) process, see Fig.13 and Figures 16 to 20 However, the present disclosure is not limited thereto, and as another option, the semiconductor structure may be cut into separate individual components (also referred to as cut SoW or cut SoW vehicle) along a scribe line SL, see Fig.21 and Fig. 22 . Fig.21 is a schematic plan view showing a semiconductor structure SP2 according to some embodiments of the present disclosure. Fig. 22 yes Fig.21 The schematic cross-sectional view of the semiconductor structure SP2 is shown, wherein Fig. 22 The cross-sectional view shown is along Fig.21 The line BB' shown in FIG. Fig.23 and Fig.24 Schematic plan views of semiconductor structures according to some alternative embodiments of the present disclosure are shown. Components similar or substantially the same as the above components will use the same reference numbers, and specific details or descriptions of the same components (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein.

[0191] In some embodiments, Fig.21 As shown in , the semiconductor structure SP2 includes four device regions DR and a peripheral region PR surrounding the four device regions DR, wherein the space between any two adjacent device regions DR (as a part of the peripheral region PR) is also considered to be a part of the edge of the final structure obtained after cutting (for example, a cut SoW or a cut SoW carrier). In this way, it should be understood that the dummy die 200 and / or DTC 300 will be arranged in the space between any two adjacent device regions DR and used as a mechanical support structure, thereby preventing the cutting (or singulation) process from causing any damage (for example, cracking or similar damage) to the semiconductor die 100 and 400, thereby enhancing the reliability of the semiconductor structure SP2. It should be understood that in some embodiments, such as Fig. 22 As shown in , for a diced SoW or a diced SoW carrier, the thickness of the wafer structure 600 at its diced edge ( SW2 c ) and the thickness at its center (CT) are smaller than the thickness of the wafer structure 600 at its edge ( SW2 ).

[0192] In a non-limiting example, Fig.21 As shown in FIG. 1 , only a dummy die 200 is placed in the peripheral region PR between two device regions DR adjacent in the vertical direction. In another non-limiting example, as Fig.23As shown in FIG. 1 , the dummy die 200 and the DTC 300 are placed in the peripheral region PR between two device regions DR adjacent in the vertical direction. In another non-limiting example, only the DTC 300 is placed in the peripheral region PR between two device regions DR adjacent in the vertical direction. In a non-limiting example, Fig.21 and Fig.23 As shown in FIG, only one dummy die 200 or only DTC 300 is disposed near the dicing edge of the final structure (e.g., diced SoW or diced SoW carrier). In another non-limiting example, one or more dummy dies 200, one or more DTC 300, and / or a combination thereof may be disposed near the dicing edge of the final structure (e.g., diced SoW or diced SoW carrier). Fig.24 As shown in FIG. 1 , one or more dummy dies 200, one or more DTCs 300, and / or a combination thereof may be placed in the peripheral region PR between the device regions DR adjacent in the vertical direction. Similar or the same configuration / placement of the dummy dies 200 and DTCs 300 discussed above may also be applied to the peripheral region PR between two device regions DR adjacent in the horizontal direction, or in addition to the peripheral region PR between the two device regions DR adjacent in the vertical direction, similar or the same configuration / placement of the dummy dies 200 and DTCs 300 discussed above may also be applied to the peripheral region PR between two device regions DR adjacent in the horizontal direction.

[0193] In the above embodiments, the positioning position of the dummy die 200 may be partially or completely replaced by the positioning position of the DTC 300 or exchanged with the positioning position of the DTC 300. The present disclosure is not limited thereto.

[0194] In the above embodiments (for example, semiconductor structures SP1, SP1', SP1", SP2 and their variations), the semiconductor die or device included in the first level T1 includes only the semiconductor die 100, the dummy die 200 and the DTC 300, and the semiconductor die or device included in the second level T2 includes only the semiconductor die 400, and in the above embodiments, the semiconductor die or device included in the first level T1 and the semiconductor die or device included in the second level T2 are arranged back-to-face, but the present disclosure is not limited to this. Alternatively, the semiconductor die or device included in the first level T1 may include one or more of the semiconductor die 100, the dummy die 200, the DTC 300 and the semiconductor die 400, and / or the semiconductor die or device included in the second level T2 may include the semiconductor die 100, the dummy die 200, the DTC 300 and the semiconductor die 400. 300 and one or more of the semiconductor die 400. In addition, the semiconductor die or device (100, 200, 300 and / or 400) included in the first level T1 and the semiconductor die or device (100, 200, 300 and / or 400) included in the second level T2 may be arranged in a back-to-face manner. As another option, the semiconductor die or device (100, 200 and / or 300) included in the first level T1 and the semiconductor die or device (100, 200, 300 and / or 400) included in the second level T2 may be arranged in a face-to-face manner. Or as another option, the semiconductor die or device (100, 200 and / or 300) included in the first level T1 and the semiconductor die or device (100, 200, 300 and / or 400) included in the second level T2 may be arranged in a face-to-back manner.

[0195] Figure 25 to Figure 28 Schematic cross-sectional views of various stages in a method for manufacturing a semiconductor structure SP3 according to some embodiments of the present disclosure. Fig.29 is a schematic cross-sectional view showing a semiconductor structure SP3 ′ according to an alternative embodiment of the present disclosure. Fig.30 and Fig.31 is an enlarged schematic cross-sectional view showing various embodiments of a bonding interface between a semiconductor die and a metallization layer overlapping the semiconductor die according to some embodiments of the present disclosure, wherein Fig.30 and Fig.31 The enlarged schematic cross-sectional view shown is Fig.25 The dashed box U2 shown in the figure is an outline. Components similar to or substantially the same as the above components will use the same reference numbers, and specific details or descriptions of the same components (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein.

[0196] Reference Fig.25 In some embodiments, a carrier 103 coated with a release layer 104 is provided. In some embodiments, a wafer structure (eg, Fig.28 600) shown in FIG. For example, the first stacking layer BL1 includes a dielectric layer 610A, a seed layer 620A, and a wiring layer 630A, wherein the wiring layer 630A stands upright on the seed layer 620A, and the dielectric layer 610A covers the seed layer 620A and the wiring layer 630A in the lateral direction (the seed layer 620A and the wiring layer 630A are collectively referred to as a metallization layer). Fig.25 As shown in , the bottom surface of the seed layer 620A is exposed by the bottom surface of the dielectric layer 610A for further electrical connection, and the top surface of the wiring layer 630A is exposed by the top surface of the dielectric layer 610A for further electrical connection. The details of the carrier 103 are similar or substantially the same as Figure 1 The details of the carrier 101 described in the embodiment of the present invention, the details of the peeling layer 104 are similar to or substantially the same as those of Figure 1 The details of the peeling layer 102 described in Figure 7 The formation and materials of the first accumulation layer BL1 are described in detail in FIG. 1 and thus are not described again herein for the sake of brevity.

[0197] In some embodiments, after forming the first buildup layer BL1, one or more semiconductor dies 100, one or more dummy dies 200, one or more DTCs 300, and one or more semiconductor dies 400 are placed on the first buildup layer BL1, and then the one or more semiconductor dies 100, the one or more dummy dies 200, the one or more DTCs 300, and the one or more semiconductor dies 400 are bonded to the first buildup layer BL1. For example, Fig.25 As shown in FIG. 3 , the semiconductor dies 100 and 400 are disposed in the device region DR of the semiconductor structure SP3, and the dummy die 200 and the DTC 300 are disposed in the peripheral region PR of the semiconductor structure SP3. In some embodiments, the semiconductor dies 100, 400, and the DTC 300 are bonded to the first buildup layer BL1 by a metal-to-metal bonding process and a dielectric-to-dielectric bonding process, and the dummy die 200 is bonded to the first buildup layer BL1 by a dielectric-to-dielectric bonding process. That is, the semiconductor dies 100, 400, and the DTC 300 are electrically connected to the first buildup layer BL1, and the dummy die 200 is electrically isolated from the first buildup layer BL1.

[0198] For example, Fig.25 and Fig.30As shown in , the surface S450t of the connecting via 450 in each of the semiconductor die 400 and the top surface of the wiring layer 630A abut against each other and are bonded together by direct metal-to-metal bonding (eg, copper-to-copper bonding). Fig.25 and Fig.30 As shown in , for example, the surface S460t of the protective layer 460 in each of the semiconductor die 400 and the shown top surface of the dielectric layer 610A of the first stacking layer BL1 are abutted against each other and bonded together by direct dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding, nitride-to-nitride bonding, or oxide-to-nitride bonding). It should be noted that the above-mentioned bonding methods are merely examples and are not intended to be limiting. In such an embodiment, the bonding interface IF2 between the semiconductor die 400 and the first stacking layer BL1 includes a dielectric-to-dielectric bonding interface (e.g., an oxide-to-oxide bonding interface, a nitride-to-nitride bonding interface, or an oxide-to-nitride bonding interface) and a metal-to-metal bonding interface (e.g., a copper-to-copper bonding interface). It should be noted that the above-mentioned bonding methods are merely examples and are not intended to be limiting. See. Fig.25 and Fig.30 , there may be an offset between the sidewalls of the connecting via 450 and the sidewalls of the wiring layer 630A located below the connecting via 450. Since one of the connecting via 450 and the wiring layer 630A may have a larger bonding surface than the other, direct metal-to-metal bonding can be achieved even in the event of misalignment, thereby ensuring the reliability of the electrical connection between the semiconductor die 400 and the wiring layer 630A. As such, for some embodiments, the protection layer 460 directly adjacent to the connecting via 450 is bonded to a portion of each of the wiring layers 630A (e.g., dielectric-to-metal bonding, see Fig.25 and Fig.30 ), or a portion of the dielectric layer 610A directly adjacent to the wiring layer 630A is bonded to each of the connecting vias 450 (eg, a dielectric-to-metal bond). Fig.25 and Fig.30 As shown in FIG. 1 , such a bonding method (eg, bonding interface IF2 ) is also applied to the semiconductor die 100 and the DTC 300 , and thus will not be described in detail for the sake of brevity.

[0199] However, the present disclosure is not limited thereto; alternatively, see Fig.31, the semiconductor die 400 can be bonded to the first buildup layer BL1 by flip chip bonding. In an alternative embodiment, there are multiple joints 50B between the connection through-holes 450 of the semiconductor die 400 and the wiring layer 630A of the first buildup layer BL1 for mechanically and electrically connecting the semiconductor die 400 and the first buildup layer BL1. The joints 50B include micro bumps, metal pillars, bumps formed by electroless nickel-palladium immersion gold (ENEPIG), controlled collapse chip connection (C4) bumps (for example, which may have a size of but not limited to about 80 microns), ball grid array (BGA) bumps or BGA balls (for example, which may have a size of but not limited to about 400 microns), solder balls or similar components. The present disclosure is not limited to this. When solder is used, the solder may include eutectic solder or non-eutectic solder. The solder may contain lead or not contain lead, and may contain Sn-Ag, Sn-Cu, Sn-Ag-Cu or similar materials. When solder is used, the joint 50B may be referred to as a solder joint or solder area. In such alternative embodiments, an underfill (not shown) may be applied as needed to surround the sidewalls of the joint 50B to ensure the bonding strength between the semiconductor die 400 and the first buildup layer BL1. This bonding method may also be applied to the semiconductor die 100 and the DTC 300, and therefore will not be described in detail for the sake of brevity.

[0200] On the other hand, Fig.25 As shown in , the dummy die 200 may be bonded to the first buildup layer BL1 by a bonding process (including both metal-to-dielectric bonding and dielectric-to-dielectric bonding). Alternatively, the dummy die 200 may be bonded to the first buildup layer BL1 by a fusion bonding process (e.g., only dielectric-to-dielectric bonding). Figure 1 , combined Fig.13 of Figure 4 and Figures 16 to 20 The formation, materials, and details of each of the semiconductor die 100, the dummy die 200, the DTC 300, and the semiconductor die 400 are described in detail in detail and thus are not repeated herein for the sake of brevity.

[0201] Continue to refer to Fig.25 In some embodiments, after the semiconductor dies 100, 400, the dummy die 200, and the DTC 300 are bonded to the first buildup layer BL1, the semiconductor dies 100, 400, the dummy die 200, and the DTC 300 are laterally encapsulated in an insulating encapsulation body 500a. Fig.25 As shown in FIG. 1 , for example, semiconductor dies 100, 400, dummy die 200, and DTC 300 are exposed through insulating encapsulation body 500a. Figures 2 to 6The formation and materials of the insulating enclosure 500a are described in detail in FIG. 1 and are therefore not repeated herein for the sake of brevity.

[0202] In some embodiments, the insulating encapsulation 500a has a top surface composed of a substantially inclined flat surface S500t1 at the peripheral region PR and a substantially flat surface S500t2 at the device region DR surrounded (or defined) by the substantially inclined flat surface S500t1, wherein the substantially inclined flat surface S500t1 is connected to the substantially flat surface S500t2 and the (substantially vertical) sidewalls of the insulating encapsulation 500a (the sidewalls are Fig.28 ). Fig.25 As shown in, for example, the substantially flat surface S500t2 is connected to the substantially inclined flat surface S500t1 and is surrounded by the substantially inclined flat surface S500t1. The substantially flat surface S500t2 can be considered as a substantially horizontal flat surface extending along the XY plane. In this case, the substantially flat surface S500t2 exposes the semiconductor die 100, 400 in a touchable manner. For example, the bottom side S100b of the semiconductor die 100 and the bottom side S400b of the semiconductor die 400 are substantially flush with the substantially flat surface S500t2 of the insulating encapsulation 500a. In other words, the end surface of the conductive column 170 of the semiconductor die 100 and the end surface of the conductive column 470 of the semiconductor die 400 are substantially coplanar with the substantially flat surface S500t2 of the insulating encapsulation 500a. In some cases, the substantially flat surface S500t2 further partially exposes the dummy die 200 and / or the DTC 300 in a touchable manner. For example, the bottom side S200b of the dummy die 200 and / or the bottom side S300b of the DTC 300 are partially substantially flush with the substantially flat surface S500t2 of the insulating encapsulation 500a. In other words, the bottom side S200b of the dummy die 200 and / or the end surface of the conductive pillar 380 of the DTC 300 are partially substantially coplanar with the substantially flat surface S500t2 of the insulating encapsulation 500a.

[0203] On the other hand, the substantially inclined flat surface S500t1 can be considered as a bevel edge, wherein the insulating encapsulation 500a has a thickness (not marked) that gradually decreases in the direction from the device region DR toward the sidewall SW3 of the semiconductor structure SP3 at the peripheral region PR. Such a bevel edge may be formed at or near the edge / sidewall of the object to be ground during the planarization process due to over-grinding / grinding or a lower metal (or pattern) density compared to the central region of the object to be ground (e.g., the semiconductor structure SP3). If it is considered that a semiconductor die (having an active device) is located at or near the edge / sidewall of the semiconductor structure SP3, such a semiconductor die will be damaged due to the presence of the bevel edge, which may result in abnormal functionality or loss of functionality. To avoid such damage, one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) may be employed at the peripheral region PR to serve as structural supports during the planarization (or thinning) process, whereby the resulting chamfered edge will terminate at / within the desired peripheral region PR without extending further into the device region DR. Therefore, since the presence of the dummy die 200 and / or the DTCs 300 improves the edge uniformity of the semiconductor structure SP3, the semiconductor die 100, 400 formed in the device region DR defined by the desired peripheral region PR (where one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) will be protected from damage caused by the planarization (or thinning) process. That is, due to at least one of the dummy die 200 and the DTC 300, the substantially inclined flat surface S500t1 of the insulating encapsulation body 500a will end at the peripheral region PR (e.g., at the dummy die 200 and / or the DTC 300), thereby enhancing the reliability of the semiconductor structure SP3. Fig.25 As shown in FIG. 5 , the substantially flat surface S500t2 of the insulating encapsulation 500a extends into the peripheral region PR. Alternatively, the substantially flat surface S500t2 of the insulating encapsulation 500a may reach and terminate at the edge of the peripheral region PR.

[0204] Reference Fig.26In some embodiments, one or more semiconductor dies 100, one or more dummy dies 200, and one or more DTCs 300 are placed on an insulating encapsulation 500a and encapsulated in an insulating encapsulation 500b. In some embodiments, before encapsulating the semiconductor die 100, the dummy die 200, and the DTCs 300 in the insulating encapsulation 500b, a bonding process is performed on the semiconductor die 100, the dummy die 200, and the DTCs 300. For example, the semiconductor die 100, the dummy die 200, and the DTCs 300 encapsulated in the insulating encapsulation 500b are respectively bonded to a corresponding one of the semiconductor devices (e.g., 100, 200, 300, or 400) encapsulated in the insulating encapsulation 500a located below the insulating encapsulation 500b. For example, the dummy die 200 encapsulated in the insulating encapsulation 500b is bonded to the dummy die 200 encapsulated in the insulating encapsulation 500a by a bonding process (including dielectric-to-metal bonding and dielectric-to-dielectric bonding) and the dummy die 200 encapsulated in the insulating encapsulation 500b is electrically isolated from the dummy die 200 encapsulated in the insulating encapsulation 500a. However, the present disclosure is not limited thereto, and as another option, the dummy die 200 encapsulated in the insulating encapsulation 500b can be bonded to the dummy die 200 encapsulated in the insulating encapsulation 500a by fusion bonding (e.g., only dielectric-to-dielectric bonding). For example, with or without dielectric-to-metal bonding, the semiconductor die 100B encapsulated in the insulating encapsulation 500b is bonded to the semiconductor die 100A encapsulated in the insulating encapsulation 500a by a bonding process (including metal-to-metal bonding and dielectric-to-dielectric bonding) and the semiconductor die 100B is electrically connected to the semiconductor die 100A. For example, with or without dielectric-to-metal bonding, the semiconductor die 100C encapsulated in the insulating encapsulation 500b is bonded to the semiconductor die 400 encapsulated in the insulating encapsulation 500a by a bonding process (including metal-to-metal bonding and dielectric-to-dielectric bonding) and the semiconductor die 100C is electrically connected to the semiconductor die 400. For example, with or without using dielectric-to-metal bonding, the semiconductor die 100D encapsulated in the insulating package 500b is bonded to the semiconductor die 400 encapsulated in the insulating package 500a through a bonding process (including metal-to-metal bonding and dielectric-to-dielectric bonding) and the semiconductor die 100D is electrically connected to the semiconductor die 400.For example, with or without dielectric-to-metal bonding, the DTC 300 encapsulated in the insulating encapsulation 500b is bonded to the DTC 300 encapsulated in the insulating encapsulation 500a by a bonding process (including metal-to-metal bonding and dielectric-to-dielectric bonding) and the DTC 300 encapsulated in the insulating encapsulation 500b is electrically connected to the DTC 300 encapsulated in the insulating encapsulation 500a. However, the present disclosure is not limited thereto, and as another option, the semiconductor die 100A and the semiconductor die 100B overlying the semiconductor die 100A, the semiconductor die 400 and the semiconductor die 100C overlying the semiconductor die 400, the semiconductor die 400 and the semiconductor die 100D overlying the semiconductor die 400, and the DTCs 300 overlapping each other may be bonded by FC bonding. The semiconductor die 400 is a bridge die (or a bridge chip) or a semiconductor bridge die (or a semiconductor bridge chip) for the semiconductor dies 100C and 100D.

[0205] In some embodiments, after bonding, the semiconductor die 100, the dummy die 200, and the DTC 300 are laterally encapsulated in an insulating encapsulation body 500b. Fig.26 As shown in FIG. 1 , for example, the semiconductor die 100, the dummy die 200, and the DTC 300 are exposed through the insulating package 500 b. Figures 2 to 6 The formation and materials of the insulating enclosure 500b are described in detail in the previous section and are therefore not described again for the sake of brevity herein. In some embodiments, the insulating enclosure 500a and the insulating enclosure 500b may be collectively referred to as the insulating enclosure 500.

[0206] Continue to refer to Fig.26 For example, the insulating encapsulation body 500b has a top surface composed of a substantially inclined flat surface S500t3 at the peripheral region PR and a substantially flat surface S500t4 at the device region DR surrounded (or defined) by the substantially inclined flat surface S500t3, wherein the substantially inclined flat surface S500t3 is connected to the substantially flat surface S500t4 and the (substantially vertical) sidewalls of the insulating encapsulation body 500b (the sidewalls are Fig.28 ). Fig.26As shown in, for example, the substantially flat surface S500t4 is connected to the substantially inclined flat surface S500t3 and is surrounded by the substantially inclined flat surface S500t3. The substantially flat surface S500t4 can be considered as a substantially horizontal flat surface extending along the XY plane. In this case, the substantially flat surface S500t4 exposes the semiconductor die 100 in a touchable manner. For example, the end surface of the conductive column 170 of each of the semiconductor die 100 is substantially flush with the substantially flat surface S500t4 of the insulating encapsulation 500b. In other words, the end surface of the conductive column 170 of the semiconductor die 100 is substantially coplanar with the substantially flat surface S500t4 of the insulating encapsulation 500b. In some cases, the substantially flat surface S500t4 further partially exposes the dummy die 200 and / or the DTC 300 in a touchable manner. For example, the bottom side S200b of each of the dummy dies 200 and / or the bottom side S300b of each of the DTCs 300 are partially substantially flush with the substantially flat surface S500t4 of the insulating encapsulation 500b. In other words, the bottom side S200b of each of the dummy dies 200 and / or the bottom side S300b of each of the DTCs 300 are partially substantially coplanar with the substantially flat surface S500t4 of the insulating encapsulation 500b.

[0207] On the other hand, the substantially inclined flat surface S500t3 can be considered as a bevel edge, wherein the insulating encapsulation body 500b has a thickness (not marked) that gradually decreases in the direction from the device region DR toward the sidewall SW3 of the semiconductor structure SP3 at the peripheral region PR. Such a bevel edge may be formed at or near the edge / sidewall of the object to be ground during the planarization process due to over-grinding / grinding or a lower metal (or pattern) density compared to the central region of the object to be ground (e.g., the semiconductor structure SP3). If it is considered that a semiconductor die (having an active device) is located at or near the edge / sidewall of the semiconductor structure SP3, such a semiconductor die will be damaged due to the presence of the bevel edge, which may result in abnormal functionality or loss of functionality. To avoid such damage, one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) may be employed at the peripheral region PR to serve as structural supports during the planarization (or thinning) process, whereby the resulting chamfered edge will terminate at / within the desired peripheral region PR without extending further into the device region DR. Therefore, since the presence of the dummy die 200 and / or the DTCs 300 improves the edge uniformity of the semiconductor structure SP3, the semiconductor die 100 formed in the device region DR defined by the desired peripheral region PR (where one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) will be protected from damage caused by the planarization (or thinning) process. That is, due to at least one of the dummy die 200 and the DTC 300, the substantially inclined flat surface S500t3 of the insulating encapsulation body 500b will end at the peripheral region PR (e.g., at the dummy die 200 and / or the DTC 300), thereby enhancing the reliability of the semiconductor structure SP3. Fig.26 As shown in , the substantially flat surface S500t4 of the insulating encapsulation 500b extends into the peripheral region PR. As an alternative, the substantially flat surface S500t4 of the insulating encapsulation 500b may reach the edge of the peripheral region PR and terminate at the edge of the peripheral region PR. In some embodiments, the thickness of the insulating encapsulation 500 at its edge is less than the thickness of the insulating encapsulation 500 at its center.

[0208] Refer to Fig.26 and Fig. 27 In some embodiments, the carrier 106 coated with the release layer 105 is bonded to the insulating package 500, and then the carrier 103 and the release layer 104 are removed. Fig. 27As shown in FIG. , the first buildup layer BL1 is exposed. The details of the carrier 106 are similar to or substantially the same as those of FIG. Figure 1 The details of the carrier 101 described in the embodiment of the present invention, the details of the peeling layer 105 are similar to or substantially the same as those of Figure 1 The details of the peeling layer 102, the carrier 103 and the peeling layer 104 described in the above are similar to or substantially the same as those in Fig.12 The removal process of the carrier 101 and the peeling layer 102 described in the prior art is not described in detail herein for the sake of brevity.

[0209] Reference Fig.28 In some embodiments, a second stacking layer BL2 of a chip structure 600 is provided and the second stacking layer BL2 is bonded to the first stacking layer BL1 to form a chip structure 600 on the insulating package 500. For example, the bonding between the second stacking layer BL2 and the first stacking layer BL1 is a wafer-on-wafer (WoW) bonding process, and the WoW bonding process includes both metal-to-metal bonding and dielectric-to-dielectric bonding performed at a bonding interface IF3. For example, the second stacking layer BL2 includes a dielectric layer 610B, a seed layer 620B, and a wiring layer 630B, wherein the wiring layer 630B is disposed on the seed layer 620B, and the dielectric layer 610B laterally covers the seed layer 620B and the wiring layer 630B (the seed layer 620B and the wiring layer 630B are collectively referred to as a metallization layer). As Fig.28 As shown in FIG, the top surface of the seed layer 620B is exposed by the top surface of the dielectric layer 610B for further electrical connection, and the bottom surface of the wiring layer 630B is exposed by the bottom surface of the dielectric layer 610B for further electrical connection. Figure 7 The formation and materials of the second stacking layer BL2 are described in detail in the previous section, and therefore will not be described in detail herein for the sake of brevity. Fig. 27 The structure shown in FIG. 1 is flipped (upside down). Fig.28 As shown in FIG. 6 , for example, the second buildup layer BL2 is electrically connected to the first buildup layer BL1 to form a wafer structure 600 , thereby providing a wiring function to the semiconductor dies 100 , 400 and the DTC 300 encapsulated in the insulating package 500 .

[0210] Continue to refer to Fig.28 After forming the wafer structure 600, the above steps are performed. Figures 8 to 108. The semiconductor structure SP3 is obtained by the process described in . In some embodiments, the redistribution wiring structure 700 is disposed on the wafer structure 600 and is electrically connected to the wafer structure 600, and the conductive terminal 900 is disposed on the redistribution wiring structure 700 and is electrically coupled to the redistribution wiring structure 700 via the UBM pattern 800. In some embodiments, the conductive terminal 900 is electrically coupled to the wafer structure 600 via the UBM pattern 800 and the redistribution wiring structure 700. In some embodiments, some of the conductive terminals 900 are electrically coupled to the semiconductor die 100 in the insulating encapsulation 500a via some of the UBM patterns 800, the redistribution wiring structure 700, and the wafer structure 600. In some embodiments, some of the conductive terminals 900 are electrically coupled to the semiconductor die 400 in the insulating encapsulation 500a via some of the UBM patterns 800, the redistribution wiring structure 700, and the wafer structure 600. In addition, some of the conductive terminals 900 are electrically coupled to the DTC 300 in the insulating package 500a via some of the UBM patterns 800, the redistribution wiring structure 700, and the wafer structure 600. In some embodiments, the conductive terminals 900 are electrically isolated from the dummy die 200 in the insulating packages 500a and 500b. In some embodiments, some of the conductive terminals 900 are electrically coupled to the semiconductor die 100 in the insulating package 500b via some of the UBM patterns 800, the redistribution wiring structure 700, the wafer structure 600, and the semiconductor die 400 (e.g., located in 500a) electrically connected to the semiconductor die 100 (e.g., located in 500b). In some embodiments, some of the conductive terminals 900 are electrically coupled to the semiconductor die 100 in the insulating encapsulation 500b via some of the UBM patterns 800, the redistribution wiring structure 700, the wafer structure 600, and the semiconductor die 100 (e.g., located in 500a) electrically connected to the semiconductor die 100 (e.g., located in 500b). In some embodiments, some of the conductive terminals 900 are electrically coupled to the DTC 300 in the insulating encapsulation 500b via some of the UBM patterns 800, the redistribution wiring structure 700, the wafer structure 600, and the DTC 300 (e.g., located in 500a) electrically connected to the DTC 300 (e.g., located in 500b).

[0211] In an alternative embodiment, the carrier 106 may be thinned to a sufficient thickness to still function as a mechanical support structure and / or a heat dissipation element (or heat sink). In this way, the overall thickness of the semiconductor structure SP3 may be reduced.

[0212] Alternatively, carrier 106 may be omitted, see Fig.29 The details of removing the carrier 106 may be similar to or substantially the same as Fig.12 The removal process of the carrier 101 described in , and therefore will not be repeated herein for the sake of brevity. The total thickness of the semiconductor structure SP3 ′ is further reduced due to the removal of the carrier 106 .

[0213] Fig.32 is a schematic cross-sectional view showing a semiconductor structure SP4 according to some embodiments of the present disclosure. Fig.33 is a schematic cross-sectional view of a semiconductor structure SP4' according to an alternative embodiment of the present disclosure. Components similar or substantially the same as the above components will use the same reference numbers, and specific details or descriptions of the same components (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein. For example, Fig.32 The semiconductor structure SP4 shown is Fig.28 The semiconductor structure SP3 shown is similar; and the difference is that in Fig.32 In the semiconductor structure SP4 shown in FIG. 8 , an intermediate layer 1000 is used to replace the redistribution wiring structure 700 , the UBM pattern 800 and the conductive terminal 900 .

[0214] Reference Fig.32 In some embodiments, in forming Fig.28 After the wafer structure 600 described in , a planarization process is performed on the wafer structure 600 to obtain a surface S600t, wherein the surface S600t is flattened and has a high degree of planarity to facilitate the formation of components formed later. In other words, the surface S600t of the wafer structure 600 can be referred to as a flat surface or a substantially horizontal flat surface. The planarization process may include a grinding process, a CMP process, an etching process, or a combination thereof. The etching process may include dry etching, wet etching, or a combination thereof. After the planarization process, a cleaning process may be performed as needed, for example, to clean and remove the residues generated by the planarization process. However, the present disclosure is not limited thereto, and the planarization process may be performed by any other suitable method.

[0215] In some embodiments, an interposer 1000 is provided and bonded to a surface S600t of a wafer structure 600. For example, the interposer 1000 is electrically connected to the wafer structure 600 by a bonding process (including both metal-to-metal bonding and dielectric-to-dielectric bonding) with or without dielectric-to-metal bonding. In some embodiments, the interposer 1000 includes a core portion 1010, a routing portion 1020, and a plurality of solder resist layers 1030A, 1030B, wherein the solder resist layer 1030A is disposed on a side S1 of the core portion 1010, the solder resist layer 1030B is disposed on a side S2 of the core portion 1010, and the routing portion 1020 is sandwiched between the solder resist layer 1030A and the core portion 1010. The side S1 may be opposite to the side S2 along the stacking direction Z.

[0216] In some embodiments, the core portion 1010 includes a core dielectric layer 1012, a plurality of through holes 1014, a plurality of core conductive layers 1016, and a plurality of conductive lids 1018. In some embodiments, the core dielectric layer 1012 includes a prepreg (containing epoxy, resin, silica filler, and / or glass fiber), ABF, resin coated copper foil (RCC), polyimide, photo imageable dielectric (PID), ceramic core, glass core, molding compound, combinations thereof, or the like. However, the present disclosure is not limited thereto, and other dielectric materials may also be used. The core dielectric layer 1012 may be formed by a lamination process, a coating process, or the like. In some embodiments, the core conductive layer 1016 is formed on opposite sides (e.g., S1 and S2) of the core dielectric layer 1012. In some embodiments, the core conductive layer 1016 comprises copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. Each conductive cover 1018 is located on the core conductive layer 1016. In some embodiments, the conductive cover 1018 comprises, for example, copper or other suitable conductive materials. In some embodiments, the core dielectric layer 1012 is referred to as a base substrate or a core substrate.

[0217] In some embodiments, the through-hole 1014 is disposed in the core dielectric layer 1012 and penetrates through the core dielectric layer 1012, and the through-hole 1014 provides an electrical connection between the core conductive layer 1016 at the two different sides (e.g., S1 and S2). In other words, the through-hole 1014 provides an electrical path between the circuits located on the two opposite sides (e.g., S1 and S2) of the core dielectric layer 1012. In some embodiments, the through-hole 1014 is lined with an insulating material, wherein a liner (not shown) separates the through-hole 1014 from the core dielectric layer 1012. The liner may be referred to as a barrier layer. In some embodiments, the method of forming the through-hole 1014 includes the following operations. First, a plurality of open holes (not shown) are formed at predetermined locations (of the through-hole 1014) by, for example, mechanical drilling or laser drilling, etching, or another suitable removal technique. A desmear treatment may be performed to remove residues remaining in the open holes formed in the core dielectric layer 1012. Subsequently, the open holes may be filled with one or more conductive materials to a predetermined thickness, thereby providing through-holes 1014. For example, the open holes may be filled with copper by electroplating or electroless plating, deposition processes, or the like. In some embodiments, through-holes 1014 are referred to as vias or conductive through-holes.

[0218] The present disclosure is not limited to this; alternatively, the perforation may include a plated perforation (not shown), wherein the open hole may be lined with a conductive material and filled with an insulating material. In some alternative embodiments, the method of forming the perforation includes the following operations. First, a plurality of open holes (not shown) are formed at predetermined locations by, for example, mechanical drilling or laser drilling, etching, or another suitable removal technique. A desmear treatment may be performed to remove residues remaining in the open holes. Subsequently, the open holes may be plated to a predetermined thickness using one or more conductive materials, thereby providing a plurality of plated perforations. For example, the open holes may be plated with copper by electroplating or electroless plating. The open holes may then be filled with any suitable insulating material.

[0219] In some embodiments, the core conductive layer 1016, the conductive cover 1018, and the through-hole 1014 may be formed by the following steps. First, a first conductive material (not shown) is formed on two opposite surfaces of the core dielectric layer 1012, respectively. Then, the through-hole 1014 is formed as described above, the through-hole 1014 penetrates the core dielectric layer 1012 and provides an electrical connection between the first conductive materials formed on two sides (e.g., S1 and S2) of the core dielectric layer 1012, respectively. Thereafter, a second conductive material is formed on the first conductive material located on opposite sides (e.g., S1 and S2) of the core dielectric layer 1012, respectively, wherein the second conductive material may be different from the first conductive material. In some embodiments, the first conductive material and the second conductive material may be formed by any suitable method (e.g., CVD, sputtering, printing, plating, or the like). Then, the first conductive material and the second conductive material may be patterned together to form the core conductive layer 1016 and the conductive cover 1018, respectively. In some embodiments, the first conductive material and the second conductive material may be partially removed using a photolithography and etching process or another suitable removal technique. Fig.32 As shown in FIG. 1 , the through hole 1014 further penetrates through the core conductive layer 1016 .

[0220] However, the present disclosure is not limited thereto; alternatively, the core conductive layer 1016, the conductive cover 1018, and the through-hole 1014 may be formed by the following steps: forming the through-hole 1014 penetrating the core dielectric layer 1012 as described above, sequentially forming the first conductive material and the second conductive material on opposite sides (e.g., S1 and S2) of the core dielectric layer 1012, and patterning the first conductive material and the second conductive material to form the core conductive layer 1016 and the conductive cover 1018; thereby, the through-hole 1014 provides electrical connection between the first conductive material and the second conductive material respectively formed on the two surfaces of the core dielectric layer 1012. For such alternative embodiments, the through-hole 1014 does not penetrate the core conductive layer 1016 (not shown).

[0221] like Fig.32 As shown in , in some embodiments, the wiring portion 1020 is disposed on the side S1 of the core portion 1010. For example, the wiring portion 1020 is formed on the conductive cover 1018 disposed at the side S1 of the core portion 1010. In some embodiments, forming the wiring portion 1020 may include sequentially forming a plurality of dielectric layers 1022 and a plurality of conductive layers 1024. For example, the dielectric layers 1022 and the conductive layers 1024 are alternately stacked on the side S1 of the core portion 1010, wherein the conductive layers 1024 provide a wiring function. In some embodiments, the wiring portion 1020 is referred to as a rewiring structure or a rewiring structure.

[0222] In some embodiments, the material of the dielectric layer 1022 may be ABF, prepreg, RCC, polyimide, PID, molding compound, a combination thereof, or the like. In some alternative embodiments, the core dielectric layer 1012 and the dielectric layer 1022 may be made of the same material. For example, the material of the core dielectric layer 1012 and the dielectric layer 1022 may be a molding compound, such as an epoxy molding compound (EMC). The dielectric layer 1022 may be formed by a lamination process, a coating process, or the like.

[0223] In some embodiments, the material of the conductive layer 1024 includes aluminum, titanium, copper, nickel, tungsten and / or alloys thereof. The conductive layer 1024 may be formed by forming a conductive material layer using a lamination process, a deposition process or the like and then performing a patterning process. The patterning process may include dry etching, wet etching or a combination thereof. In some embodiments, the formation and material of each layer of the conductive layer 1024 are the same as or similar to Figure 7 The processes and materials for forming the metallization layer are described in , and therefore will not be described in detail herein.

[0224] Despite Fig.32 1024 and three layers of dielectric layer 1022 are shown for each of the wiring portions 1020, but the present disclosure is not limited thereto. In some alternative embodiments, the number of dielectric layers 1022 and the number of conductive layers 1024 may be adjusted according to design requirements. In some embodiments, for each of the conductive layers and dielectric layers included in the wiring portions 1020, the total number of layers for each of the wiring portions 1020 may total from one layer to eight layers.

[0225] In some embodiments, the solder resist layer 1030A is formed on the outermost surface of the wiring portion 1020 facing away from the core portion 1010, and the solder resist layer 1030B is formed on the side S2 of the core portion 1010. For example, the outermost conductive layer 1024 of the wiring portion 1020 is exposed in a tangible manner through the outermost surface of the solder resist layer 1030A, and the conductive cover 1018 at the side S2 is exposed in a tangible manner through the outermost surface of the solder resist layer 1030B. For example, the outermost conductive layer 1024 of the wiring portion 1020 is substantially coplanar and substantially flush with the outermost surface of the solder resist layer 1030A.

[0226] However, the present disclosure is not limited to this. In alternative embodiments, in addition to the wiring portion 1020, there may be an additional wiring portion between the core portion 1010 and the solder mask 1030B. In some other alternative embodiments, the wiring portion 1020 may be omitted, and there may be an additional wiring portion between the core portion 1010 and the solder mask 1030B. In some other alternative embodiments, the wiring portion is not included in the interposer 1000. Alternatively, the core portion 1010 may be omitted, wherein the conductive terminal 3000 is directly connected to the wiring portion. In addition, as an alternative, the interposer 1000 may be pre-made on the second buildup layer BL2 before the second buildup layer BL2 is bonded to the first buildup layer BL1. The interposer 1000 may be referred to as a wafer-level circuit structure or a wafer circuit structure.

[0227] Continue to refer to Fig.32 In some embodiments, after the wafer structure 600 and the interposer 1000 are disposed on the insulating encapsulation 500 and electrically connected to the semiconductor dies 100, 400 and the DTC 300, a plurality of conductive terminals 3000 are provided and bonded to the interposer 1000, wherein the interposer 1000 is located between the conductive terminals 3000 and the wafer structure 600. For example, the conductive terminals 3000 are disposed on the outermost surface of the solder resist layer 1030B and further extend into a plurality of openings (not marked) formed in the solder resist layer 1030B to be electrically connected to the core portion 1010.

[0228] In some embodiments, the conductive terminals 3000 are electrically coupled to the wafer structure 600 via the interposer 1000. In some embodiments, some of the conductive terminals 3000 are electrically coupled to the semiconductor die 100A (located in 500a) via the interposer 1000 and the wafer structure 600. In addition, some of the conductive terminals 3000 may be electrically coupled to the DTC 300 (located in 500a) via the interposer 1000 and the wafer structure 600. In some embodiments, some of the conductive terminals 3000 are electrically coupled to the semiconductor die 400 via the interposer 1000 and the wafer structure 600. In some embodiments, the conductive terminals 3000 are electrically isolated from the dummy die 200 (located in 500a). In some embodiments, some of the conductive terminals 3000 are electrically coupled to the semiconductor die 100B (located in 500b) via the interposer 1000, the wafer structure 600, and the semiconductor die 100A (located in 500a). In some embodiments, some of the conductive terminals 3000 are electrically coupled to the semiconductor die 100C (located in 500b) via the interposer 1000, the wafer structure 600, and the semiconductor die 400 (located in 500a). In some embodiments, some of the conductive terminals 3000 are electrically coupled to the semiconductor die 100D (located in 500b) via the interposer 1000, the wafer structure 600, and the semiconductor die 400 (located in 500a). In addition, some of the conductive terminals 3000 may be electrically coupled to the DTC 300 (located in 500b) via the interposer 1000, the wafer structure 600, and the DTC 300 (located in 500a). In some embodiments, the conductive terminals 3000 are electrically isolated from the dummy die 200 (located in 500b).

[0229] In some embodiments, the conductive terminal 3000 is physically connected to the core portion 1010. In some embodiments, the conductive terminal 3000 is disposed on the conductive cover 1018 by a ball implantation process or a reflow process. For example, the conductive terminal 3000 includes a microbump, a metal column, a bump formed by electroless nickel palladium immersion gold (ENEPIG), a controlled collapse chip connection (C4) bump (e.g., it may have a size of but not limited to about 80 microns), a ball grid array (BGA) bump or a BGA ball (e.g., it may have a size of but not limited to about 400 microns), a solder ball, or a similar component. The present disclosure is not limited thereto. The number of conductive terminals 3000 is not limited to the drawings of the embodiments, and may be selected and specified based on demand and design requirements. The number of conductive terminals 3000 may be controlled by adjusting the number of openings formed in the solder resist layer 1030B. When solder is used, the solder may include eutectic solder or non-eutectic solder. The solder may contain lead or may not contain lead, and may contain Sn-Ag, Sn-Cu, Sn-Ag-Cu or similar materials. The conductive terminal 3000 may not contain solder. The conductive terminal 3000 may be referred to as a conductor, input / output (I / O) terminal, conductive connector or conductive I / O terminal of the semiconductor structure SP4 for electrical connection with an external component or component (e.g., an additional semiconductor package / device, a circuit substrate, an interposer, a capacitor, a power supply or the like).

[0230] In an alternative embodiment, the carrier 106 may be thinned to a sufficient thickness to still function as a mechanical support structure and / or a heat dissipation element (or heat sink). In this way, the overall thickness of the semiconductor structure SP4 may be reduced.

[0231] Alternatively, carrier 106 may be omitted, see Fig.33 The details of removing the carrier 106 may be similar to or substantially the same as Fig.12 The removal process of the carrier 106 is described in detail in the previous section and is therefore not described again for the sake of brevity. The total thickness of the semiconductor structure SP4′ is further reduced due to the removal of the carrier 106.

[0232] In the above embodiments (for example, semiconductor packages SP3, SP3', SP4, SP4' and their variations), the semiconductor die or device included in the first level T1 includes the semiconductor die 100, the dummy die 200, the DTC 300 and the semiconductor die 400, while the semiconductor die or device included in the second level T2 only includes the semiconductor die 100, the dummy die 200 and the DTC 300, and in the above embodiments, the semiconductor die or device included in the first level T1 and the semiconductor die or device included in the second level T2 are arranged back to face, however, the present disclosure is not limited to this. Alternatively, the semiconductor die or device included in the first level T1 may include one or more of the semiconductor die 100, the dummy die 200, the DTC 300, and the semiconductor die 400, and / or the semiconductor die or device included in the second level T2 may include one or more of the semiconductor die 100, the dummy die 200, the DTC 300, and the semiconductor die 400. In addition, the semiconductor die or device (100, 200, 300, and / or 400) included in the first level T1 and the semiconductor die or device (100, 200, 300, and / or 400) included in the second level T2 may be arranged in a back-to-face manner. Alternatively, the semiconductor die or device (100, 200 and / or 300) included in the first level T1 and the semiconductor die or device (100, 200, 300 and / or 400) included in the second level T2 may be arranged face to face. Alternatively, the semiconductor die or device (100, 200 and / or 300) included in the first level T1 and the semiconductor die or device (100, 200, 300 and / or 400) included in the second level T2 may be arranged face to back.

[0233] Figure 34 to Figure 35 Schematic cross-sectional views of various stages in a method for manufacturing a semiconductor structure SP5 according to some embodiments of the present disclosure. Fig.36 1 is a schematic cross-sectional view of a semiconductor structure SP6 according to an alternative embodiment of the present disclosure. Components similar or substantially the same as the above components will use the same reference numbers, and specific details or descriptions of the same components (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein.

[0234] Reference Fig.34In some embodiments, an interposer 1000 is provided, and one or more semiconductor dies 100, one or more dummy dies 200, and one or more DTCs 300 are bonded and electrically connected to the interposer 1000 via a plurality of connectors 50C. For example, the semiconductor die 100, the dummy die 200, and the DTCs 300 are bonded to the interposer 1000 by FC bonding. Fig.32 The details of the intermediate layer 1000 are described in detail in the previous Fig.13 of Figure 4 as well as Figures 16 to 20 The details of each of the semiconductor die 100, the dummy die 200 and the DTC 300 are described in detail in the previous Fig.15 and / or Fig.31 The details of the FC joint are described in the specification, and the formation and materials of the joint 50C are similar to or substantially the same as Fig.15 The formation and material of the connector 50A described in Fig.31 The formation and materials of the joint 50B described in , and therefore, are not repeated herein for the sake of brevity.

[0235] Thereafter, in some embodiments, an underfill 2000 is formed on the interposer 1000 as needed. Fig.34 As shown in , for example, the bottom fill 2000 fills at least the gap between the semiconductor die 100 and the interposer 1000, the gap between the dummy die 200 and the interposer 1000, and the gap between the DTC 300 and the interposer 1000 and surrounds the sidewalls of the joint 50C. In some alternative embodiments, the sidewalls of the semiconductor die 100, the sidewalls of the dummy die 200, and / or the sidewalls of the DTC 300 may be further covered by the bottom fill 2000, but the present disclosure is not limited thereto. For example, the bottom fill 2000 may be any acceptable material, such as a polymer, epoxy, molded bottom fill, or the like. In one embodiment, the bottom fill 2000 may be formed by bottom fill dispensing or any other suitable method. The bonding strength between the semiconductor die 100 and the interposer 1000 , the bonding strength between the dummy die 200 and the interposer 1000 , and the bonding strength between the DTC 300 and the interposer 1000 are enhanced due to the underfill 2000 , thereby improving the reliability of the semiconductor structure SP5 .

[0236] Reference Fig.35 In some embodiments, the semiconductor die 100, the dummy die 200, and the DTC 300 are laterally encapsulated in an insulating encapsulation 500 (including an insulating encapsulation 500a). Fig.35 As shown in FIG. 5 , for example, the semiconductor die 100, the dummy die 200, and the DTC 300 are exposed through the insulating package 500a. Figures 2 to 6 The formation and materials of the insulating enclosure 500a are described in detail in FIG. 1 and are therefore not repeated herein for the sake of brevity.

[0237] In some embodiments, the insulating encapsulation 500a has a top surface composed of a substantially inclined flat surface S500t1 at the peripheral region PR and a substantially flat surface S500t2 at the device region DR surrounded (or defined) by the substantially inclined flat surface S500t1, wherein the substantially inclined flat surface S500t1 is connected to the substantially flat surface S500t2 and the (substantially vertical) sidewall of the insulating encapsulation 500a (the sidewall is a part of the sidewall SW5 of the semiconductor structure SP5). Fig.35 As shown in, for example, the substantially flat surface S500t2 is connected to the substantially inclined flat surface S500t1 and is surrounded by the substantially inclined flat surface S500t1. The substantially flat surface S500t2 can be considered as a substantially horizontal flat surface extending along the XY plane. In this case, the substantially flat surface S500t2 exposes the semiconductor die 100 in a touchable manner. For example, the bottom side S100b of the semiconductor die 100 is substantially flush with the substantially flat surface S500t2 of the insulating encapsulation 500a. In other words, the end surface of the conductive column 170 of the semiconductor die 100 is substantially coplanar with the substantially flat surface S500t2 of the insulating encapsulation 500a.

[0238] In some cases, the substantially flat surface S500t2 further partially exposes the dummy die 200 and / or the DTC 300 in a touchable manner. For example, the bottom side S200b of the dummy die 200 and / or the bottom side S300b of the DTC 300 are partially substantially flush with the substantially flat surface S500t2 of the insulating encapsulation 500a. In other words, the bottom side S200b of the dummy die 200 and / or the end surface of the conductive pillar 380 of the DTC 300 are partially substantially coplanar with the substantially flat surface S500t2 of the insulating encapsulation 500a.

[0239] On the other hand, the substantially inclined flat surface S500t1 can be considered as a bevel edge, wherein the insulating encapsulation body 500a has a thickness (not marked) that gradually decreases in the direction from the device region DR toward the sidewall SW5 of the semiconductor structure SP5 at the peripheral region PR. Such a bevel edge may be formed at or near the edge / sidewall of the object to be ground during the planarization process due to over-grinding / grinding or a lower metal (or pattern) density compared to the central region of the object to be ground (e.g., the semiconductor structure SP5). If it is considered that a semiconductor die (having an active device) is located at or near the edge / sidewall of the semiconductor structure SP5, such a semiconductor die will be damaged due to the presence of the bevel edge, which may result in abnormal functionality or loss of functionality. To avoid such damage, one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) may be employed at the peripheral region PR to serve as structural supports during the planarization (or thinning) process, whereby the resulting chamfered edge will terminate at / within the desired peripheral region PR without extending further into the device region DR. Therefore, since the presence of the dummy die 200 and / or the DTCs 300 improves the edge uniformity of the semiconductor structure SP5, the semiconductor die 100 formed in the device region DR defined by the desired peripheral region PR (where one or more dummy dies (e.g., 200) and / or one or more deep trench capacitors (DTCs in which no active devices (e.g., transistors, diodes, memories, etc.) are formed) (e.g., 300) will be protected from damage caused by the planarization (or thinning) process. That is, due to at least one of the dummy die 200 and the DTC 300, the substantially inclined flat surface S500t1 of the insulating encapsulation body 500a will end at the peripheral region PR (e.g., at the dummy die 200 and / or the DTC 300), thereby enhancing the reliability of the semiconductor structure SP5. Fig.35 As shown in FIG. 5 , the substantially flat surface S500t2 of the insulating encapsulation 500a extends into the peripheral region PR. Alternatively, the substantially flat surface S500t2 of the insulating encapsulation 500a may reach and terminate at the edge of the peripheral region PR.

[0240] However, the present disclosure is not limited thereto. As an alternative, the metal bonding may be performed with or without dielectric bonding. Fig.14 and / or Fig.30One or more semiconductor dies 100, one or more dummy dies 200, and one or more DTCs 300 are bonded to the interposer 1000 using bonding processes similar to those described in , including metal-to-metal bonding and dielectric-to-dielectric bonding. Fig.36 As shown in the semiconductor structure SP6, the semiconductor die 100, the dummy die 200 and the DTC 300 are bonded and electrically connected to the interposer 1000 by direct contacts. In this case, the underfill 2000 may be omitted.

[0241] In some embodiments, where applicable, the concepts of the semiconductor structure (e.g., SP1, SP1', SP1", SP2, SP3, SP3', SP4, SP4', SP5, SP6, or variations thereof) may also be applied to another of the semiconductor structures (e.g., SP1, SP1', SP1", SP2, SP3, SP3', SP4, SP4', SP5, SP6, or variations thereof). For example, the diced SoW or diced SoW carrier and die arrangement discussed in the semiconductor structure SP2 may also be applied to other semiconductor structures in the present disclosure. In addition, the number of levels of the semiconductor structure (e.g., SP1, SP1', SP1", SP2, SP3, SP3', SP4, SP4', SP5, SP6 or their variations) may be one, two or more, and the present disclosure is not limited thereto. For example, if the number of the levels is one, the dies or devices included in the levels may be or may include SoIC dies (having a pre-fabricated stacked structure) or devices (having a pre-fabricated stacked structure). Alternatively, if the number of the levels is two or more, the dies or devices included in each level may be or may include dies (having or not having a pre-fabricated stacked structure) or devices (having or not having a pre-fabricated stacked structure). In addition, it should be understood that the dummy die 200 and the DTC 300 may be referred to as a (mechanical) support structure of the semiconductor structure (e.g., SP1, SP1', SP1", SP2, SP3, SP3', SP4, SP4', SP5, SP6 or their variations).

[0242] According to some embodiments, a semiconductor structure includes a wafer circuit structure, at least one first semiconductor die, at least one first support structure, and an encapsulant. The at least one first semiconductor die is disposed on the wafer circuit structure in a device region of the semiconductor structure and is electrically connected to the wafer circuit structure. The at least one first support structure is disposed on the wafer circuit structure in a peripheral region of the semiconductor structure. The encapsulant is disposed on the wafer circuit structure and encapsulates the at least one first semiconductor die and the at least one first support structure, wherein a thickness of the encapsulant at an edge of the semiconductor structure is less than a thickness of the encapsulant in the device region of the semiconductor structure.

[0243] In some embodiments, in the semiconductor structure, the thickness of the wafer circuit structure at the edge of the semiconductor structure is greater than the thickness of the wafer circuit structure in the device region of the semiconductor structure. In some embodiments, in the semiconductor structure, the encapsulant includes a first portion and a second portion stacked on the first portion, the first portion is sandwiched between the wafer circuit structure and the second portion, and the first portion encapsulates the at least one first semiconductor die, wherein the semiconductor structure further includes at least one of the following: at least one second semiconductor die, disposed on the wafer circuit structure in the device region of the semiconductor structure and electrically connected to the at least one first semiconductor die, wherein the at least one second semiconductor die is encapsulated in the second portion; or at least one second support structure, disposed on the wafer circuit structure in the peripheral region of the semiconductor structure, the at least one second support structure is encapsulated in the encapsulant and electrically connected to the wafer circuit structure, wherein the at least one first support structure is electrically isolated from the wafer circuit structure. In some embodiments, in the semiconductor structure, the at least one first semiconductor die includes a plurality of first semiconductor dies, and the at least one second semiconductor die is electrically connected to two first semiconductor dies among the plurality of first semiconductor dies, wherein the at least one second semiconductor die includes a bridge die that electrically connects the two first semiconductor dies among the plurality of first semiconductor dies. In some embodiments, in the semiconductor structure, the at least one second semiconductor die includes a plurality of second semiconductor dies, and the at least one first semiconductor die is electrically connected to two second semiconductor dies among the plurality of second semiconductor dies, wherein the at least one first semiconductor die includes a bridge die that electrically connects the two second semiconductor dies among the plurality of second semiconductor dies. In some embodiments, in the semiconductor structure, the at least one first support structure includes: a first plurality of first support structures enclosed in the first portion; a second plurality of first support structures enclosed in the second portion; or a first plurality of first support structures enclosed in the first portion and a second plurality of first support structures enclosed in the second portion, wherein the first plurality of first support structures and the second plurality of first support structures are electrically isolated from each other. In some embodiments, in the semiconductor structure, the at least one second support structure includes: a first plurality of second support structures enclosed in the first part; a second plurality of second support structures enclosed in the second part; or a first plurality of second support structures enclosed in the first part and a second plurality of second support structures enclosed in the second part.In some embodiments, the semiconductor structure further includes: a redistribution wiring structure disposed on the chip circuit structure and electrically connected to the chip circuit structure, wherein the chip circuit structure is located between the package and the redistribution wiring structure; and a plurality of conductive terminals disposed on the redistribution wiring structure and connected to the redistribution wiring structure, wherein the redistribution wiring structure is located between the plurality of conductive terminals and the chip circuit structure. In some embodiments, the semiconductor structure further includes: an interposer disposed on the chip circuit structure and electrically connected to the chip circuit structure, wherein the chip circuit structure is located between the package and the interposer; and a plurality of conductive terminals disposed on the interposer and connected to the interposer, wherein the interposer is located between the plurality of conductive terminals and the chip circuit structure. In some embodiments, the semiconductor structure further includes: a heat dissipation component disposed on the package, wherein the package is located between the heat dissipation component and the chip circuit structure.

[0244] According to some embodiments, a semiconductor structure includes a wafer circuit structure, at least one first semiconductor die, a plurality of support structures, and an insulating encapsulation. The at least one first semiconductor die is disposed on the wafer circuit structure in a device region of the semiconductor structure and is electrically connected to the wafer circuit structure. The plurality of support structures are disposed on the wafer circuit structure in a peripheral region of the semiconductor structure, wherein the plurality of support structures are arranged in a point-symmetrical manner relative to a center of the semiconductor structure. The insulating encapsulation is disposed on the wafer circuit structure and encapsulates the at least one first semiconductor die and the plurality of support structures.

[0245] In some embodiments, in the semiconductor structure, the plurality of support structures are grouped into a plurality of pairs of support structures, wherein one support structure in each pair of the plurality of pairs of support structures and the other support structure in a corresponding pair of the plurality of pairs of support structures are arranged in a position passed by a single line passing through the center of the semiconductor structure within the peripheral region of the semiconductor structure. In some embodiments, in the semiconductor structure, the plurality of support structures include a plurality of dummy dies, wherein the plurality of dummy dies are electrically isolated from the wafer circuit structure. In some embodiments, in the semiconductor structure, the plurality of support structures include a plurality of deep trench capacitors, wherein the plurality of deep trench capacitors are electrically connected to the wafer circuit structure. In some embodiments, in the semiconductor structure, the plurality of support structures include: one or more dummy dies, wherein the one or more dummy dies are electrically isolated from the wafer circuit structure; and one or more deep trench capacitors, wherein the one or more deep trench capacitors are electrically connected to the wafer circuit structure.

[0246] According to some embodiments, a method for manufacturing a semiconductor structure includes the following steps: setting at least one first semiconductor die in a device area of ​​the semiconductor structure; setting at least one first support structure in a peripheral area of ​​the semiconductor structure, the peripheral area surrounding the device area; laterally encapsulating the at least one first semiconductor die and the at least one first support structure in an encapsulation body, wherein the thickness of the encapsulation body at the edge of the semiconductor structure is less than the thickness of the encapsulation body in the device area of ​​the semiconductor structure; and forming a chip circuit structure on the at least one first semiconductor die and the at least one first support structure encapsulated in the encapsulation body, the chip circuit structure electrically connecting the at least one first semiconductor die.

[0247] In some embodiments, the method further comprises: providing at least one second semiconductor die, wherein: providing the at least one first semiconductor die comprises providing a plurality of first semiconductor die, and laterally encapsulating the at least one first semiconductor die and the at least one first support structure in the encapsulation body comprises laterally encapsulating the plurality of first semiconductor die, the at least one first support structure and the at least one second semiconductor die in the encapsulation body by: forming a first insulating material on the at least one second semiconductor die, wherein the at least one second semiconductor die is not exposed due to the first insulating material; performing a first planarization process on the first insulating material to remove a portion of the first insulating material, thereby forming a first portion of the encapsulation body that exposes the at least one second semiconductor die; and A second insulating material is formed on the first part of the body to cover the multiple first semiconductor dies and the at least one first supporting structure, wherein the multiple first semiconductor dies and the at least one first supporting structure are not exposed due to the second insulating material; and a second planarization process is performed on the second insulating material to remove a portion of the second insulating material, thereby forming a second portion of the encapsulation body that exposes the multiple first semiconductor dies and the at least one first supporting structure, wherein a portion of the at least one first supporting structure is also removed in the second planarization process, wherein the second portion of the encapsulation body is located between the first portion of the encapsulation body and the chip circuit structure, and two first semiconductor dies among the multiple first semiconductor dies are electrically connected to each other and electrically connected to each other via the at least one second semiconductor die. In some embodiments, the method further comprises: providing at least one second support structure, wherein: forming the second insulating material over the first portion of the encapsulation to cover the plurality of first semiconductor dies and the at least one first support structure comprises forming the second insulating material over the first portion of the encapsulation to cover the plurality of first semiconductor dies, the at least one first support structure, and the at least one second support structure, such that the plurality of first semiconductor dies, the at least one first support structure, and the at least one second support structure are not exposed due to the second insulating material;And performing the second planarization process on the second insulating material to remove the portion of the second insulating material, thereby forming the second portion of the encapsulation body that exposes the multiple first semiconductor dies and the at least one first support structure includes performing the second planarization process on the second insulating material to remove the portion of the second insulating material, thereby forming the second portion of the encapsulation body that exposes the multiple first semiconductor dies, the at least one first support structure and the at least one second support structure, wherein one of the at least one first support structure and the at least one second support structure is electrically isolated from the chip circuit structure, and the other of the at least one first support structure and the at least one second support structure is electrically connected to the chip circuit structure. In some embodiments, the method further includes: providing at least one second semiconductor die; and providing a first set of second support structures and a second set of second support structures, wherein: providing the at least one first semiconductor die includes providing a first set of first semiconductor die and a second set of first semiconductor die; providing the at least one first support structure includes providing a first set of first support structures and a second set of first support structures; and laterally encapsulating the at least one first semiconductor die and the at least one first support structure in the encapsulation body includes laterally encapsulating the first set of first semiconductor die, the second set of first semiconductor die, the first set of first support structures, the second set of first support structures, the first set of second support structures, and the at least one second semiconductor die by: forming a first insulating material over the first set of first semiconductor die, the first set of first support structures, the first set of second support structures, and the at least one second semiconductor die, wherein the first set of first semiconductor die a first insulating material is formed on the first portion of the encapsulation body, wherein the first group of first support structures, the first group of second support structures and the at least one second semiconductor die are not exposed due to the first insulating material; a first planarization process is performed on the first insulating material to remove a portion of the first insulating material, thereby forming a first portion of the encapsulation body, which exposes the first group of first semiconductor die, the first group of first support structures, the first group of second support structures and the at least one second semiconductor die, wherein at least one of a portion of at least one first support structure in the first group of first support structures or a portion of at least one second support structure in the first group of second support structures is also removed in the first planarization process; a second insulating material is formed on the first portion of the encapsulation body, to cover the second group of first semiconductor die, the second group of first support structures and the second group of second support structures, wherein the second group of first semiconductor die, the second group of first support structures and the second group of second support structures are not exposed due to the second insulating material;and performing a second planarization process on the second insulating material to remove a portion of the second insulating material, thereby forming a second portion of the encapsulation that exposes the second group of first semiconductor dies, the second group of first support structures, and the second group of second support structures, wherein at least one of a portion of at least one first support structure in the second group of first support structures or a portion of at least one second support structure in the second group of second support structures is also removed in the second planarization process, wherein the first portion of the encapsulation is located between the second portion of the encapsulation and the chip circuit structure, and two first semiconductor dies in the second group of first semiconductor dies are electrically connected to each other and electrically connected to each other via the at least one second semiconductor die, wherein the first group of first support structures and the second group of first support structures overlap with each other, respectively, and the first group of second support structures and the second group of second support structures overlap with each other, respectively, and wherein the first group of second support structures and the second group of second support structures are electrically connected to the chip circuit structure. In some embodiments, in the method, encapsulating the at least one first semiconductor die and the at least one first support structure in the encapsulation body in the lateral direction includes: forming an insulating material over the at least one first semiconductor die and the at least one first support structure, so that the at least one first semiconductor die and the at least one first support structure are not exposed due to the insulating material; and performing a planarization process on the insulating material to remove a portion of the insulating material, thereby forming the encapsulation body that exposes the at least one first semiconductor die and the at least one first support structure, wherein a portion of the at least one first support structure is also removed in the planarization process. ;

[0248] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A semiconductor structure, characterized in that: include: Chip circuit structure; at least one first semiconductor die disposed over and electrically connected to the wafer circuit structure in a device region of the semiconductor structure; at least one first support structure disposed above the wafer circuit structure in a peripheral region of the semiconductor structure; as well as An encapsulant is disposed on the wafer circuit structure and encapsulates the at least one first semiconductor die and the at least one first support structure, wherein a thickness of the encapsulant at an edge of the semiconductor structure is smaller than a thickness of the encapsulant in the device region of the semiconductor structure.

2. The semiconductor structure according to claim 1, characterized in that: The thickness of the wafer circuit structure at the edge of the semiconductor structure is greater than the thickness of the wafer circuit structure in the device region of the semiconductor structure.

3. The semiconductor structure according to claim 1, characterized in that: wherein the encapsulation body comprises a first portion and a second portion stacked on the first portion, the first portion is sandwiched between the wafer circuit structure and the second portion, and the first portion encapsulates the at least one first semiconductor die, The semiconductor structure further comprises at least one of the following: at least one second semiconductor die disposed over the wafer circuit structure in the device region of the semiconductor structure and electrically connected to the at least one first semiconductor die, wherein the at least one second semiconductor die is encapsulated in the second portion; or At least one second support structure is arranged on the chip circuit structure in the peripheral area of ​​the semiconductor structure, and the at least one second support structure is encapsulated in the encapsulation body and electrically connected to the chip circuit structure, wherein the at least one first support structure is electrically isolated from the chip circuit structure.

4. The semiconductor structure according to claim 3, characterized in that: wherein the at least one first semiconductor die comprises a plurality of first semiconductor dies, and the at least one second semiconductor die is electrically connected to two first semiconductor dies of the plurality of first semiconductor dies, The at least one second semiconductor die includes a bridge die for electrically connecting the two first semiconductor dies among the plurality of first semiconductor dies.

5. The semiconductor structure according to claim 3, characterized in that: wherein the at least one second semiconductor die comprises a plurality of second semiconductor dies, and the at least one first semiconductor die is electrically connected to two second semiconductor dies of the plurality of second semiconductor dies, The at least one first semiconductor die includes a bridge die for electrically connecting the two second semiconductor dies in the plurality of second semiconductor dies.

6. The semiconductor structure according to claim 3, characterized in that: wherein the at least one first support structure comprises: a first plurality of first support structures enclosed in said first portion; a second plurality of first support structures enclosed in the second portion; or A first plurality of first support structures are enclosed in the first portion and a second plurality of first support structures are enclosed in the second portion, wherein the first plurality of first support structures and the second plurality of first support structures are electrically isolated from each other.

7. The semiconductor structure according to claim 3, characterized in that: wherein the at least one second support structure comprises: a first plurality of second support structures enclosed in the first portion; a second plurality of second support structures enclosed in said second portion; or A first plurality of second support structures are enclosed in the first portion and a second plurality of second support structures are enclosed in the second portion.

8. A semiconductor structure, characterized in that: include: Chip circuit structure; at least one first semiconductor die disposed above and electrically connected to the wafer circuit structure in a device region of the semiconductor structure; a plurality of support structures disposed above the wafer circuit structure in a peripheral region of the semiconductor structure, wherein the plurality of support structures are arranged in a point-symmetrical manner relative to a center of the semiconductor structure; as well as The insulating encapsulation body is disposed on the wafer circuit structure and encapsulates the at least one first semiconductor die and the plurality of supporting structures.

9. The semiconductor structure according to claim 8, characterized in that: The plurality of support structures include a plurality of dummy dies, wherein the plurality of dummy dies are electrically isolated from the wafer circuit structure.

10. The semiconductor structure according to claim 8, characterized in that The plurality of support structures include a plurality of deep trench capacitors, wherein the plurality of deep trench capacitors are electrically connected to the wafer circuit structure.

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