A digital IO compatible with multiple logic levels
By adding logic level converters and power clamps to digital IO, the problem of output errors in traditional digital IO under different supply voltage conditions is solved, achieving wider compatibility and lower leakage risk.
Patent Information
- Application Number
- CN202420955791.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-06
- Publication Date
- 2025-04-08
- Estimated Expiration
- 2034-05-06
AI Technical Summary
Traditional digital IO can easily lead to leakage and logic function abnormality when processing signals of different logic level, especially when the power supply voltages inside and outside the chip do not match.
Add a logic level converter to the digital IO to convert the logic level from the PAD signal to the logic level voltage value of the in-chip power supply, and combine the power clamp and the ESD protection unit to provide protection across the in-chip power supply.
It effectively avoids leakage and logic error problems caused by outputting intermediate or high levels under different power supply voltage conditions, increasing the use scenarios of chips and reducing external constraints.
Smart Images
Figure CN222736145U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of digital IO, in particular to a digital IO compatible with multiple logic levels. Background Art
[0002] The traditional digital IO structure requires the logic level of the PAD input signal to reach the IO voltage level, otherwise it will cause unnecessary leakage in the subsequent circuit and even cause abnormal logic function.
[0003] like Figure 1 When the high-level voltage value from the PAD signal is lower than the voltage value of VDD_IO, the digital PMOS tube PM1 in the circuit cannot be completely turned off, and leakage current from VDD_IO to GND_IO will be generated. When the high-level voltage value from the PAD signal is lower, the output signal of the inverter constructed by PM1 and NM1 may be an intermediate level or a high level, resulting in serious leakage and output of incorrect logic levels.
[0004] Therefore, a chip that needs to be compatible with multiple input logic levels is expected to meet the chip's demand for compatibility with multiple input logic levels.
[0005] Based on this technical background, the utility model studies a digital IO compatible with multiple logic levels. Utility Model Content
[0006] In view of the shortcomings of the prior art, the utility model proposes a digital IO compatible with multiple logic levels. The digital IO adds a logic level converter before the digital module inside the chip, converts the logic level from the PAD signal into the logic level voltage value of the power supply inside the chip, and then inputs it into the digital module, avoiding the problem that when the logic level of the PAD signal is between the power supply inside and outside the chip, the traditional digital IO may output an intermediate level or a high level, resulting in serious leakage and outputting an erroneous logic level.
[0007] In order to achieve the above object, the utility model provides a digital IO compatible with multiple logic levels, including:
[0008] A logic level converter, whose output end is electrically connected to the input of a digital module inside the chip, and is used to convert the logic level from the signal PAD into the logic level of the digital module;
[0009] Power clamps, used to provide ESD protection across the chip's internal and external power traces and the chip's power PADs;
[0010] The ESD protection unit is electrically connected to the signal PAD input and electrically connected to the input end of the logic level converter output, and is used to perform ESD protection on the digital IO.
[0011] The beneficial effects of the utility model include:
[0012] (1) The digital IO compatible with multiple logic levels proposed by the present invention adds a logic level converter before the digital module inside the chip, converts the logic level from the PAD signal into the logic level voltage value of the power supply inside the chip, and then inputs it into the digital module, thereby avoiding the problem that when the logic level from the PAD signal is between the power supply inside and outside the chip, the traditional digital IO may output an intermediate level or a high level, resulting in serious leakage and outputting an erroneous logic level.
[0013] (2) The digital IO compatible with multiple logic levels proposed by the present invention allows the logic level voltage value of the input signal from the PAD to be lower than the voltage value of the power supply in the chip, thereby increasing the usage scenarios of the chip and reducing external constraints.
[0014] Other features and advantages of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present invention.
[0016] Figure 1 It is a schematic diagram of the circuit structure of the existing digital IO.
[0017] Figure 2 This is a schematic diagram of the overall structure of a specific implementation of a digital IO compatible with multiple logic levels proposed by the present invention.
[0018] Figure 3 This is a schematic diagram of the structure of a logic level converter in a specific implementation of a digital IO compatible with multiple logic levels proposed by the present invention.
[0019] Figure 4 This is a schematic structural diagram of a power clamp in a specific implementation of a digital IO compatible with multiple logic levels proposed by the utility model.
[0020] Figure 5 This is a structural schematic diagram of a first protection unit in a specific implementation of a digital IO compatible with multiple logic levels proposed by the present invention.
[0021] Figure 6 This is a structural schematic diagram of a second protection unit in a specific implementation of a digital IO compatible with multiple logic levels proposed by the present invention.
[0022] Description of reference numerals:
[0023] Primary ESD PROTECT-first protection unit, Secondary ESD PROTECT-second protection unit, Power Clamp-power clamp, Logic Level Shifter-logic level converter, IO Logic-digital module, INV1-input inverter, INV2-output inverter;
[0024] D1-first protection diode, D2-second protection diode, D3-third protection diode, D4-fourth protection diode, D5-clamping diode, R1-protection resistor, R2-clamping resistor, C1-clamping capacitor, PM1-digital PMOS tube, PM2-first PMOS feedback tube, PM3-second PMOS feedback tube, NM1-digital NMOS tube, NM2-clamping NMOS tube, NM3-first NMOS input tube, NM4-second NMOS input tube;
[0025] VDD_IO-power supply inside the chip, GND_IO-power supply inside the chip, VDD2-power supply outside the chip. DETAILED DESCRIPTION
[0026] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein.
[0027] In the present utility model, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present utility model, "multiple" means two or more, unless otherwise clearly and specifically defined.
[0028] The utility model provides a digital IO compatible with multiple logic levels, as shown in FIG. Figure 2 As shown, including:
[0029] A logic level converter Logic Level Shifter, whose output end is electrically connected to the input of the digital module IO Logic inside the chip, is used to convert the logic level from the signal PAD into the logic level of the digital module IO Logic;
[0030] Power Clamp, used to provide ESD protection across the chip's internal and external power lines and the chip's power PAD;
[0031] Preferably, it also includes:
[0032] The ESD protection unit is electrically connected to the input signal PAD, and the output is electrically connected to the input end of the logic level converter Logic Level Shifter, and is used to perform ESD protection on the digital IO.
[0033] In the utility model, a logic level converter Logic Level Shifter is added before the digital module IO Logic inside the chip, and the logic level from the PAD signal is converted into the logic level voltage value of the power supply VDD_IO inside the chip and then input into the digital module IO Logic, thereby avoiding the problem that when the logic level from the PAD signal is between the power supplies inside and outside the chip, the traditional digital IO may output an intermediate level or a high level, resulting in serious leakage and outputting an erroneous logic level.
[0034] According to the utility model, the logic level converter Logic Level Shifter includes a pair of PMOS feedback tubes, a pair of NMOS input tubes, an input inverter INV1 and an output inverter INV2.
[0035] According to the utility model, the sources of the two PMOS feedback tubes in a pair of PMOS feedback tubes are electrically connected to the power supply VDD_IO in the chip, the gate of the first PMOS feedback tube PM2 is electrically connected to the drain of the second PMOS feedback tube PM3, and the gate of the second PMOS feedback tube PM3 is electrically connected to the drain of the first PMOS feedback tube PM2;
[0036] The sources of the two NMOS tubes in a pair of NMOS input tubes are electrically connected to the GND_IO potential in the chip, the drain of the first NMOS input tube NM3 is electrically connected to the drain of the first PMOS feedback tube PM2, and the drain of the second NMOS input tube NM4 is electrically connected to the drain of the second PMOS feedback tube PM3;
[0037] The input inverter INV1 is powered by an off-chip power supply VDD2, an input end of which is electrically connected to the gate of the first NMOS input tube NM3 and serves as an input end of a logic level converter Logic Level Shifter, and an output end of which is electrically connected to the gate of the second NMOS input tube NM4;
[0038] The output inverter INV2 is powered by the power supply VDD_IO in the chip, an input end of the inverter INV2 is electrically connected to the drain of the first NMOS input tube NM3, and an output end of the inverter INV2 serves as an output end of the logic level converter Logic Level Shifter.
[0039] According to the utility model, the power clamp Power Clamp comprises a clamp diode D5, a clamp NMOS tube NM2, a clamp resistor R2 and a clamp capacitor C1.
[0040] Preferably, the input of the clamping diode D5 is electrically connected to the off-chip power supply VDD2, and the output is electrically connected to the on-chip power supply VDD_IO;
[0041] The drain of the clamping NMOS tube NM2 is electrically connected to the power supply VDD2 outside the chip, and the source is electrically connected to the GND_IO potential inside the chip;
[0042] One end of the clamp resistor R2 is electrically connected to the off-chip power supply VDD2, and the other end is electrically connected to the gate of the clamp NMOS tube NM2;
[0043] One end of the clamp capacitor C1 is electrically connected to the gate of the clamp NMOS transistor NM2, and the other end is electrically connected to the GND_IO potential in the chip.
[0044] According to the utility model, the ESD protection unit comprises a first protection unit Primary ESDPROTECT and a second protection unit Secondary ESD PROTECT which are sequentially connected in series.
[0045] Preferably, the first protection unit Primary ESD PROTECT comprises a first protection diode D1 and a second protection diode D2;
[0046] The input of the first protection diode D1 and the output of the second protection diode D2 are electrically connected to the signal PAD at the same time;
[0047] The output of the first protection diode D1 is electrically connected to the power supply VDD_IO in the chip;
[0048] The input of the second protection diode D2 is electrically connected to the GND_IO potential within the chip.
[0049] Preferably, the second protection unit Secondary ESD PROTECT includes a third protection diode D3, a fourth protection diode D4 and a protection resistor R1.
[0050] According to the utility model, the input of the third protection diode D3 and the output of the fourth protection diode D4 are electrically connected to one end of the protection resistor R1 at the same time, and the electrical connection end serves as the output of the ESD protection unit;
[0051] The other end of the protection resistor R1 is electrically connected to the signal PAD;
[0052] The output of the third protection diode D3 is electrically connected to the chip internal power supply VDD_IO;
[0053] The input of the fourth protection diode D4 is electrically connected to the GND_IO potential within the chip.
[0054] The digital IO in the utility model allows the logic level voltage value of the input signal from the PAD to be lower than the voltage value of the power supply VDD_IO in the chip, thereby increasing the use scenarios of the chip and reducing external constraints.
[0055] In the utility model, when the chip does not provide an external power supply, a voltage generator can be used to convert the internal power supply voltage of the chip into an external power supply voltage. The voltage generator can be formed by a bandgap reference source, an operational amplifier, a feedback PMOS tube 4, and a voltage divider resistor connected into a feedback loop.
[0056] The present invention is described in more detail below through specific embodiments.
[0057] Example 1
[0058] like Figure 2 As shown, this embodiment provides a digital IO compatible with multiple logic levels, including:
[0059] A logic level converter Logic Level Shifter, whose output end is electrically connected to the input of the digital module IO Logic inside the chip, is used to convert the logic level from the signal PAD into the logic level of the digital module IO Logic;
[0060] Power Clamp, used to provide ESD protection across the chip's internal and external power lines and the chip's power PAD;
[0061] An ESD protection unit, the input signal PAD is electrically connected, and the output is electrically connected to the input end of the logic level converter Logic Level Shifter, and is used for performing ESD protection on the digital IO;
[0062] like Figure 3 As shown, the logic level converter Logic Level Shifter includes a pair of PMOS feedback tubes, a pair of NMOS input tubes, an input inverter INV1 and an output inverter INV2;
[0063] The sources of the two PMOS feedback tubes in the pair of PMOS feedback tubes are electrically connected to the power supply VDD_IO in the chip, the gate of the first PMOS feedback tube PM2 is electrically connected to the drain of the second PMOS feedback tube PM3, and the gate of the second PMOS feedback tube PM3 is electrically connected to the drain of the first PMOS feedback tube PM2;
[0064] The sources of the two NMOS tubes in a pair of NMOS input tubes are electrically connected to the GND_IO potential in the chip, the drain of the first NMOS input tube NM3 is electrically connected to the drain of the first PMOS feedback tube PM2, and the drain of the second NMOS input tube NM4 is electrically connected to the drain of the second PMOS feedback tube PM3;
[0065] The input inverter INV1 is powered by an off-chip power supply VDD2, an input end of which is electrically connected to the gate of the first NMOS input tube NM3 and serves as an input end of a logic level converter Logic Level Shifter, and an output end of which is electrically connected to the gate of the second NMOS input tube NM4;
[0066] The output inverter INV2 is powered by the power supply VDD_IO in the chip, the input end of the inverter INV2 is electrically connected to the drain of the first NMOS input tube NM3, and the output end of the inverter INV2 serves as the output end of the logic level converter Logic Level Shifter;
[0067] like Figure 4 As shown, the power clamp Power Clamp includes a clamp diode D5, a clamp NMOS tube NM2, a clamp resistor R2 and a clamp capacitor C1;
[0068] The input of the clamping diode D5 is electrically connected to the off-chip power supply VDD2, and the output is electrically connected to the on-chip power supply VDD_IO;
[0069] The drain of the clamping NMOS tube NM2 is electrically connected to the power supply VDD2 outside the chip, and the source is electrically connected to the GND_IO potential inside the chip;
[0070] One end of the clamp resistor R2 is electrically connected to the off-chip power supply VDD2, and the other end is electrically connected to the gate of the clamp NMOS tube NM2;
[0071] One end of the clamp capacitor C1 is electrically connected to the gate of the clamp NMOS transistor NM2, and the other end is electrically connected to the GND_IO potential in the chip;
[0072] The ESD protection unit includes a first protection unit Primary ESD PROTECT and a second protection unit Secondary ESD PROTECT which are connected in series in sequence;
[0073] like Figure 5 As shown, the first protection unit Primary ESD PROTECT includes a first protection diode D1 and a second protection diode D2;
[0074] The input of the first protection diode D1 and the output of the second protection diode D2 are electrically connected to the signal PAD at the same time;
[0075] The output of the first protection diode D1 is electrically connected to the power supply VDD_IO in the chip;
[0076] The input of the second protection diode D2 is electrically connected to the GND_IO potential in the chip;
[0077] like Figure 6 As shown, the second protection unit Secondary ESD PROTECT includes a third protection diode D3, a fourth protection diode D4 and a protection resistor R1;
[0078] The input of the third protection diode D3 and the output of the fourth protection diode D4 are electrically connected to one end of the protection resistor R1 at the same time, and the electrical connection end serves as the output of the ESD protection unit;
[0079] The other end of the protection resistor R1 is electrically connected to the signal PAD;
[0080] The output of the third protection diode D3 is electrically connected to the chip internal power supply VDD_IO;
[0081] The input of the fourth protection diode D4 is electrically connected to the GND_IO potential within the chip.
[0082] The embodiment of the utility model proposes a digital IO compatible with multiple logic levels, and adds a logic level converter before the digital module inside the chip, converts the logic level from the PAD signal into the logic level voltage value of the power supply inside the chip, and then inputs it into the digital module, thereby avoiding the problem that when the logic level of the PAD signal is between the power supply inside and outside the chip, the traditional digital IO may output an intermediate level or a high level, resulting in serious leakage and outputting an erroneous logic level.
[0083] The various embodiments of the utility model have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.
Claims
1. A digital IO compatible with multiple logic levels, characterized in that: include: A logic level converter, whose output end is electrically connected to the input of a digital module inside the chip, and is used to convert the logic level from the signal PAD into the logic level of the digital module; Power clamps are used to provide ESD protection across the chip's internal and external power traces and the chip's power PADs.
2. The digital IO according to claim 1, characterized in that Also includes: The ESD protection unit is electrically connected to the signal PAD input and electrically connected to the input end of the logic level converter output, and is used to perform ESD protection on the digital IO.
3. The digital IO according to claim 1, characterized in that The logic level converter includes a pair of PMOS feedback tubes, a pair of NMOS input tubes, an input inverter and an output inverter.
4. The digital IO according to claim 3, characterized in that The sources of the two PMOS feedback tubes in the pair of PMOS feedback tubes are both electrically connected to the power supply in the chip, the gate of the first PMOS feedback tube is electrically connected to the drain of the second PMOS feedback tube, and the gate of the second PMOS feedback tube is electrically connected to the drain of the first PMOS feedback tube; The sources of the two NMOS tubes in the pair of NMOS input tubes are electrically connected to the internal potential of the chip, the drain of the first NMOS input tube is electrically connected to the drain of the first PMOS feedback tube, and the drain of the second NMOS input tube is electrically connected to the drain of the second PMOS feedback tube; The input inverter is powered by the off-chip power supply, the input end of which is electrically connected to the gate of the first NMOS input tube and serves as the input end of the logic level converter, and the output end of which is electrically connected to the gate of the second NMOS input tube; The output inverter is powered by the power supply within the chip, an input end of the output inverter is electrically connected to the drain of the first NMOS input tube, and an output end of the output inverter serves as an output end of the logic level converter.
5. The digital IO according to claim 1, characterized in that The power clamp comprises a clamp diode, a clamp NMOS tube, a clamp resistor and a clamp capacitor.
6. The digital IO according to claim 5, characterized in that The input of the clamping diode is electrically connected to the off-chip power supply, and the output is electrically connected to the on-chip power supply; The drain of the clamped NMOS tube is electrically connected to the power supply outside the chip, and the source is electrically connected to the potential inside the chip; One end of the clamp resistor is electrically connected to the off-chip power supply, and the other end is electrically connected to the gate of the clamp NMOS tube; One end of the clamp capacitor is electrically connected to the gate of the clamp NMOS tube, and the other end is electrically connected to the internal potential of the chip.
7. The digital IO according to claim 2, characterized in that The ESD protection unit includes a first protection unit and a second protection unit connected in series.
8. The digital IO according to claim 7, characterized in that The first protection unit includes a first protection diode and a second protection diode; The input of the first protection diode and the output of the second protection diode are electrically connected to the signal PAD at the same time; The output of the first protection diode is electrically connected to the power supply within the chip; An input of the second protection diode is electrically connected to the internal potential of the chip.
9. The digital IO according to claim 8, characterized in that The second protection unit includes a third protection diode, a fourth protection diode and a protection resistor.
10. The digital IO according to claim 9, characterized in that The input of the third protection diode and the output of the fourth protection diode are electrically connected to one end of the protection resistor at the same time, and the electrical connection end serves as the output of the ESD protection unit; The other end of the protection resistor is electrically connected to the signal PAD; The output of the third protection diode is electrically connected to the power supply within the chip; An input of the fourth protection diode is electrically connected to the internal potential of the chip.