High-performance solid relay circuit and packaging structure thereof

Abstract

The utility model provides a high performance solid state relay circuit and a packaging structure thereof, the circuit comprises a voltage stabilization input circuit, the output end of the voltage stabilization input circuit is connected with the input end of an isolation drive circuit, the output end of the isolation drive circuit is connected with the input end of a shunt current sharing output circuit, and the output end of the shunt current sharing output circuit is connected with the output end of the isolation drive circuit. The input end of the voltage stabilization input circuit is connected with the power supply input end, and the output end of the shunt and current sharing output circuit is connected with a load; the relay has the advantages of strong load capacity, high insulation and voltage resistance, strong heat dissipation capability, small volume and high reliability, and high performance of the solid relay is realized.

Description

Technical Field

[0001] The utility model belongs to the technical field of relays, and in particular relates to a high-performance solid relay circuit and a packaging structure thereof. Background Art

[0002] Solid-state relays are generally used in circuits for electrical control or enhanced isolation driving. As an isolating switch in a circuit, small size, high performance, high load, and high insulation withstand voltage are the top priorities of solid-state relays, and are also technical challenges for relays. To achieve high performance, high load, and high insulation withstand voltage, it is necessary to increase the size of the package and increase the diameter of the lead-out terminal and insulator, which greatly increases the size of the solid-state relay. Utility Model Content

[0003] In order to solve the above technical problems, the utility model provides a high-performance solid-state relay circuit and a packaging structure thereof.

[0004] The utility model is realized through the following technical solutions.

[0005] The high-performance solid-state relay circuit provided by the utility model comprises a voltage-stabilizing input circuit, the output end of the voltage-stabilizing input circuit is connected to the input end of the isolation drive circuit, the output end of the isolation drive circuit is connected to the input end of the current-splitting and current-sharing output circuit, the input end of the voltage-stabilizing input circuit is connected to the power supply input end, and the output end of the current-splitting and current-sharing output circuit is connected to a load.

[0006] The voltage stabilizing input circuit includes voltage stabilizing diodes D2 and D3, transistor Q1, resistors R1 and R2, and diode D1;

[0007] The base of the transistor Q1 is connected to the cathode of the Zener diode D2 and one end of the resistor R1, the collector is connected to the other end of the resistor R1 and the cathode of the diode D1, and the emitter is connected to the cathode of the Zener diode D3; the anode of the Zener diode D3 is connected to one end of the resistor R2; the anode of the diode D1 is connected to the positive terminal IN+ of the power supply, and the anode of the Zener diode D2 is connected to the negative terminal IN- of the power supply.

[0008] The isolation driving circuit includes a transformer U1, transistors Q4, Q6, capacitors C1, C2, C3, C4, resistors R5, R6, and diodes D4, D5;

[0009] The base of the transistor Q6 is connected to the capacitor C1, the capacitor C2 and one end of the resistor R5, the collector is connected to the pin 2 of the transformer U1 and one end of the capacitor C3, the emitter is connected to the capacitor C4 and the other end of the capacitor C3, and the other end of the capacitor C4 is also connected to the anode of the Zener diode D2; the pin 1 of the transformer U1 is connected to the resistor R2, the resistor R5 and the other end of the capacitor C1, the pin 3 is connected to the capacitor C2 and one end of the resistor R6, and the collector of the transistor Q4, and the pin 4 is connected to the anode of the diode D4; the cathode of the diode D4 is connected to the other end of the capacitor C2 and the resistor R6, the anode of the diode D5, and the base of the transistor Q4; the emitter of the transistor Q4 is connected to the cathode of the diode D5.

[0010] The current splitting and equalizing output circuit includes N-type field effect transistors Q2, Q3, Q5, Q7, Q8, Q9, and resistors R3, R4, R7, R8, R9, and R10;

[0011] The gates of the N-type field effect transistors Q2, Q3 and Q5 are respectively connected to one end of the resistor R3, R4 and R7, and the sources are all connected to the collector of the transistor Q4; the gates of the N-type field effect transistors Q7, Q8 and Q9 are respectively connected to one end of the resistor R8, R9 and R10, and the sources are all connected to the collector of the transistor Q4; the other ends of the resistors R3, R4, R7, R8 and R9 are connected to the emitter of the transistor Q4; the drains of the N-type field effect transistors Q2, Q3, Q5, Q7, Q8 and Q9 serve as the output ends of the current shunting and current sharing output circuit.

[0012] A packaging structure of a high-performance solid relay circuit includes a high-performance solid relay circuit, and also includes a metal shell, a cover plate, a connecting column I, a connecting column II, a connecting column III, a printed circuit board, a thermal layer, an insulator I, and an insulator II;

[0013] The high-performance solid relay circuit, connecting column I, connecting column II, connecting column III printed circuit board and thermal layer are arranged inside the metal shell, and the cover plate is fixed on the metal shell; the high-performance solid relay circuit includes a circuit board A of an isolation drive circuit and a circuit board B of an input voltage stabilization circuit arranged in sequence on the printed board, and also includes a circuit board C of a current shunting and current sharing output circuit arranged on the thermal layer; the left and right ends of the printed board and the thermal layer are connected through connecting column III and connecting column II respectively; a lead pin I is arranged at the left end of the metal shell, and an insulator I is arranged between the lead pin I and the left end metal shell; a lead pin II is arranged at the right end of the metal shell, and an insulator II is arranged between the lead pin II and the right end metal shell; the right end of the lead pin I is connected to the connecting column I through the left end metal shell; the lower end of the connecting column I is connected to the thermal layer; the left end of the lead pin II is connected to the printed board through the right end metal shell.

[0014] The lead pin I, connecting column I, connecting column II and connecting column III are all made of oxygen-free copper.

[0015] The insulator I and the insulator II are both made of ceramic materials.

[0016] The left end metal shell and insulator I, the insulator I and lead pin I, the right end metal shell and insulator II, and the insulator II and lead pin II are all connected by sintering.

[0017] The right side of the lead pin I and the upper end of the connecting column I, the lower end of the connecting column II and the right end of the thermal layer, the left side of the lead pin II and the right end of the printed circuit board, and the upper end of the connecting column II and the right end of the printed circuit board are all connected by sintering.

[0018] The circuit board C and the heat layer are connected by eutectic sintering.

[0019] The beneficial effects of the utility model are: 1) by using lead pin I made of oxygen-free copper material as the output lead, the output impedance of the high-performance relay is reduced, the output power consumption is reduced, and thus the load capacity of the high-performance relay is improved;

[0020] 2) Ceramic material is used as insulator I or insulator II between lead pin I or lead pin II and the metal shell, thereby improving the insulation withstand voltage performance of the high-performance relay;

[0021] 3) Multiple N-type field effect transistors are connected in parallel in the current splitting and current sharing output circuit, thereby improving the load capacity of the high-performance relay;

[0022] 4) By adding a resistor in series with the gate of each N-type field effect tube, the oscillation caused by the parasitic capacitance of the field effect tube is suppressed, and the resonance problem caused by connecting multiple N-type field effect tubes in parallel is solved;

[0023] 5) By sintering the N-type field effect transistor in the current-sharing output circuit onto the thermal layer in a eutectic manner, the heat dissipation and load capacity of the high-performance relay are improved;

[0024] 6) Through the voltage-stabilizing input circuit, the input current of the high-performance relay is reduced to ensure that the on-voltage and off-voltage can meet the use requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a circuit schematic diagram of the high performance relay circuit of the utility model;

[0026] Figure 2 This is a packaging structure diagram of the high-performance solid-state relay circuit of the utility model;

[0027] In the figure: 1-metal shell, 2-cover plate, 3-lead pin I, 4-lead pin II, 5-insulator I, 6-insulator II, 7-connecting column I, 8-connecting column II, 9-printed circuit board, 10-thermal layer, 11-circuit board A, 12-circuit board B, 13-circuit board C, 14-connecting column III. DETAILED DESCRIPTION

[0028] The technical solution of the utility model is further described below, but the scope of protection required is not limited to the description.

[0029] like Figure 1 Shown is a circuit schematic diagram of a high-performance relay circuit of the utility model; the high-performance solid-state relay circuit includes a voltage-stabilizing input circuit, the output end of the voltage-stabilizing input circuit is connected to the input end of the isolation drive circuit, the output end of the isolation drive circuit is connected to the input end of the current-dividing and current-sharing output circuit, the input end of the voltage-stabilizing input circuit is connected to the power supply input end, and the output end of the current-dividing and current-sharing output circuit is connected to the load.

[0030] The voltage stabilizing input circuit includes voltage stabilizing diodes D2 and D3, transistor Q1, resistors R1 and R2, and diode D1;

[0031] The base of the transistor Q1 is connected to the cathode of the Zener diode D2 and one end of the resistor R1, the collector is connected to the other end of the resistor R1 and the cathode of the diode D1, and the emitter is connected to the cathode of the Zener diode D3; the anode of the Zener diode D3 is connected to one end of the resistor R2; the anode of the diode D1 is connected to the positive terminal IN+ of the power supply, and the anode of the Zener diode D2 is connected to the negative terminal IN- of the power supply;

[0032] Specifically, when voltage is applied to the input end, the voltage is stabilized by the voltage stabilizing diode D2 at the primary level, and then stabilized by the voltage stabilizing diode D3 at the secondary level, and provided as input for the isolation drive circuit through the current limiting resistor R2. The transformer U1 of the isolation drive circuit is coupled, and then the AC signal coupled from the transformer U1 is converted into a DC signal through the filtering circuit, and the gate of the field effect transistor of the subsequent current shunting and equalizing output circuit is provided with an operating voltage, so that the field effect transistor is turned on; the voltage stabilizing input circuit is connected to the power input end, which reduces the input current of the relay and ensures that the on-voltage and off-voltage can meet the use requirements.

[0033] The isolation driving circuit includes a transformer U1, transistors Q4, Q6, capacitors C1, C2, C3, C4, resistors R5, R6, and diodes D4, D5;

[0034] The base of the transistor Q6 is connected to the capacitor C1, the capacitor C2 and one end of the resistor R5, the collector is connected to the pin 2 of the transformer U1 and one end of the capacitor C3, the emitter is connected to the capacitor C4 and the other end of the capacitor C3, and the other end of the capacitor C4 is also connected to the anode of the Zener diode D2; the pin 1 of the transformer U1 is connected to the resistor R2, the resistor R5 and the other end of the capacitor C1, the pin 3 is connected to the capacitor C2 and one end of the resistor R6, and the collector of the transistor Q4, and the pin 4 is connected to the anode of the diode D4; the cathode of the diode D4 is connected to the other end of the capacitor C2 and the resistor R6, the anode of the diode D5, and the base of the transistor Q4; the emitter of the transistor Q4 is connected to the cathode of the diode D5.

[0035] The current splitting and equalizing output circuit includes N-type field effect transistors Q2, Q3, Q5, Q7, Q8, Q9, and resistors R3, R4, R7, R8, R9, and R10;

[0036] The gates of the N-type field effect transistors Q2, Q3 and Q5 are respectively connected to one end of the resistor R3, R4 and R7, and the sources are all connected to the collector of the transistor Q4; the gates of the N-type field effect transistors Q7, Q8 and Q9 are respectively connected to one end of the resistor R8, R9 and R10, and the sources are all connected to the collector of the transistor Q4; the other ends of the resistors R3, R4, R7, R8 and R9 are connected to the emitter of the transistor Q4; the drains of the N-type field effect transistors Q2, Q3, Q5, Q7, Q8 and Q9 serve as the output ends of the current shunting and current sharing output circuit;

[0037] Specifically, the load capacity of the high-performance relay is improved by connecting N-type field effect transistors Q2, Q3 and Q5 in parallel, and the bidirectional structure of the high-performance relay is realized by connecting N-type field effect transistors Q2, Q3 and Q5 in reverse series with N-type field effect transistors Q7, Q8 and Q9; the oscillation caused by the parasitic capacitance of the field effect transistors is suppressed by connecting gate series resistances of N-type field effect transistors Q2, Q3, Q5, Q7, Q8 and Q9, thereby solving the problem of resonance phenomenon occurring after multiple N-type field effect transistors are connected in parallel.

[0038] like Figure 2 The figure shows the packaging structure of the high-performance solid relay circuit of the utility model; a packaging structure of a high-performance solid relay circuit, comprising a high-performance solid relay circuit, and also comprising a metal shell 1, a cover plate (2), a connecting column I 7, a connecting column II 8, a connecting column III 14, a printed circuit board 9, a thermal layer 10, an insulator I 5, and an insulator II 6;

[0039] The high-performance solid relay circuit, the connection column I7, the connection column II8, the connection column III14 printed board 9 and the thermal layer 10 are arranged inside the metal shell 1, and the cover plate 2 is fixed on the metal shell 1; the high-performance solid relay circuit includes a circuit board A12 of an isolation drive circuit and a circuit board B11 of an input voltage stabilization circuit arranged on the printed board 9 in sequence, and also includes a circuit board C13 of a current shunting and current balancing output circuit arranged on the thermal layer 10; the left and right ends of the printed board 9 and the thermal layer 10 are connected by connecting The connecting column III14 is connected to the connecting column II8; a lead pin I3 is provided at the left end of the metal shell 1, and an insulator I5 is provided between the lead pin I3 and the left end metal shell 1; a lead pin II4 is provided at the right end of the metal shell 1, and an insulator II6 is provided between the lead pin II4 and the right end metal shell 1; the right end of the lead pin I3 is connected to the connecting column I7 through the left end metal shell 1; the lower end of the connecting column I7 is connected to the thermal layer 10; the left end of the lead pin II4 is connected to the printed circuit board 9 through the right end metal shell 1.

[0040] Specifically, the lead pin II4 is made of copper core calenderable material;

[0041] Specifically, the lead pin Ⅰ3, the connecting pillar Ⅰ7, the connecting pillar Ⅱ8 and the connecting pillar Ⅲ14 are all made of oxygen-free copper;

[0042] Specifically, by using lead pin Ⅰ3 made of oxygen-free copper material as the output lead, the output impedance of the high-performance relay is reduced, the output power consumption is reduced, and thus the load capacity of the high-performance relay is improved;

[0043] The insulator I5 and the insulator II6 are both made of ceramic materials;

[0044] Specifically, ceramic material is used as insulator I or insulator II between lead pin I or lead pin II and the metal shell, thereby improving the insulation withstand voltage performance of the high-performance relay.

[0045] The left end metal shell 1 and insulator Ⅰ5, the insulator Ⅰ5 and lead pin Ⅰ3, the right end metal shell 1 and insulator Ⅱ6, and the insulator Ⅱ6 and lead pin Ⅱ4 are all connected by sintering;

[0046] Specifically, the connection performed by sintering improves the performance of high insulation resistance between the lead pin I3 or the lead pin II4 and the metal housing 1;

[0047] The right side of the lead pin Ⅰ3 and the upper end of the connecting column Ⅰ7, the lower end of the connecting column Ⅱ8 and the right end of the thermal layer 10, the left side of the lead pin Ⅱ4 and the right end of the printed circuit board 9, and the upper end of the connecting column Ⅱ8 and the right end of the printed circuit board 9 are all connected by sintering;

[0048] Specifically, the effective connection by sintering reduces the power consumption of the metal housing 1 due to its own resistance.

[0049] The circuit board C13 and the thermal layer 10 are connected by eutectic sintering;

[0050] Specifically, the N-type field effect transistor on the high-performance relay circuit structure is eutecticized onto the thermal layer 10 using high-temperature solder, and then the thermal layer 10 is eutecticized into the metal housing 1 using high-temperature solder, thereby improving the load capacity of the high-performance relay. The thermal layer 10 is made of molybdenum-copper material, thereby improving the heat dissipation capacity of the high-performance relay.

[0051] The utility model has the beneficial effects of strong load capacity, high insulation pressure resistance, strong heat dissipation capacity, small size and high reliability, thus realizing the high performance of the solid-state relay.

Claims

1. A high performance solid state relay circuit, characterized in that: It includes a voltage-stabilizing input circuit, the output end of the voltage-stabilizing input circuit is connected to the input end of the isolation drive circuit, the output end of the isolation drive circuit is connected to the input end of the current shunting and current sharing output circuit, the input end of the voltage-stabilizing input circuit is connected to the power supply input end, and the output end of the current shunting and current sharing output circuit is connected to the load.

2. A high performance solid state relay circuit as claimed in claim 1, characterized in that: The voltage stabilizing input circuit includes voltage stabilizing diodes D2 and D3, transistor Q1, resistors R1 and R2, and diode D1; The base of the transistor Q1 is connected to the cathode of the Zener diode D2 and one end of the resistor R1, the collector is connected to the other end of the resistor R1 and the cathode of the diode D1, and the emitter is connected to the cathode of the Zener diode D3; the anode of the Zener diode D3 is connected to one end of the resistor R2; the anode of the diode D1 is connected to the positive terminal IN+ of the power supply, and the anode of the Zener diode D2 is connected to the negative terminal IN- of the power supply.

3. A high performance solid state relay circuit as claimed in claim 1, characterized in that: The isolation driving circuit includes a transformer U1, transistors Q4, Q6, capacitors C1, C2, C3, C4, resistors R5, R6, and diodes D4, D5; The base of the transistor Q6 is connected to the capacitor C1, the capacitor C2 and one end of the resistor R5, the collector is connected to the pin 2 of the transformer U1 and one end of the capacitor C3, the emitter is connected to the capacitor C4 and the other end of the capacitor C3, and the other end of the capacitor C4 is also connected to the anode of the Zener diode D2; the pin 1 of the transformer U1 is connected to the resistor R2, the resistor R5 and the other end of the capacitor C1, the pin 3 is connected to the capacitor C2 and one end of the resistor R6, and the collector of the transistor Q4, and the pin 4 is connected to the anode of the diode D4; the cathode of the diode D4 is connected to the other end of the capacitor C2 and the resistor R6, the anode of the diode D5, and the base of the transistor Q4; the emitter of the transistor Q4 is connected to the cathode of the diode D5.

4. A high performance solid state relay circuit as claimed in claim 1, characterized in that: The current splitting and equalizing output circuit includes N-type field effect transistors Q2, Q3, Q5, Q7, Q8, Q9, and resistors R3, R4, R7, R8, R9, and R10; The gates of the N-type field effect transistors Q2, Q3 and Q5 are respectively connected to one end of the resistor R3, R4 and R7, and the sources are all connected to the collector of the transistor Q4; the gates of the N-type field effect transistors Q7, Q8 and Q9 are respectively connected to one end of the resistor R8, R9 and R10, and the sources are all connected to the collector of the transistor Q4; the other ends of the resistors R3, R4, R7, R8 and R9 are connected to the emitter of the transistor Q4; the drains of the N-type field effect transistors Q2, Q3, Q5, Q7, Q8 and Q9 serve as the output ends of the current shunting and current sharing output circuit.

5. A packaging structure of a high-performance solid-state relay circuit, characterized in that: A high performance solid state relay circuit according to any one of claims 1 to 4, further comprising a metal housing (1), a cover plate (2), a connecting column I (7), a connecting column II (8), a connecting column III (14), a printed circuit board (9), a thermal layer (10), an insulator I (5), and an insulator II (6); The high-performance solid relay circuit, the connection column I (7), the connection column II (8), the connection column III (14), the printed board (9) and the thermal layer (10) are arranged inside the metal shell (1), and the cover plate (2) is fixed on the metal shell (1); the high-performance solid relay circuit includes a circuit board A (12) of an isolation drive circuit and a circuit board B (11) of an input voltage stabilization circuit arranged in sequence on the printed board (9), and also includes a circuit board C (13) of a current shunting and current balancing output circuit arranged on the thermal layer (10); the left and right ends of the printed board (9) and the thermal layer (10) are respectively connected through the connection column III (14). 4) and a connecting column II (8); a lead pin I (3) is provided at the left end of the metal shell (1), and an insulator I (5) is provided between the lead pin I (3) and the left end metal shell (1); a lead pin II (4) is provided at the right end of the metal shell (1), and an insulator II (6) is provided between the lead pin II (4) and the right end metal shell (1); the right end of the lead pin I (3) is connected to the connecting column I (7) through the left end metal shell (1); the lower end of the connecting column I (7) is connected to the thermal layer (10); the left end of the lead pin II (4) is connected to the printed circuit board (9) through the right end metal shell (1).

6. A packaging structure of a high performance solid state relay circuit as claimed in claim 5, characterized in that: The lead pin I (3), connecting column I (7), connecting column II (8) and connecting column III (14) are all made of oxygen-free copper material.

7. The packaging structure of a high performance solid state relay circuit as claimed in claim 5, characterized in that: The insulator I (5) and the insulator II (6) are both made of ceramic materials.

8. The packaging structure of a high performance solid state relay circuit as claimed in claim 5, characterized in that: The left-end metal shell (1) and insulator I (5), the insulator I (5) and lead pin I (3), the right-end metal shell (1) and insulator II (6), and the insulator II (6) and lead pin II (4) are all connected by sintering.

9. The packaging structure of a high performance solid state relay circuit as claimed in claim 5, characterized in that: The right side of the lead pin I (3) and the upper end of the connecting column I (7), the lower end of the connecting column II (8) and the right end of the thermal layer (10), the left side of the lead pin II (4) and the right end of the printed circuit board (9), and the upper end of the connecting column II (8) and the right end of the printed circuit board (9) are all connected by sintering.

10. The packaging structure of a high performance solid state relay circuit as claimed in claim 5, characterized in that: The circuit board C (13) and the thermal layer (10) are connected by eutectic sintering.

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