Chip structure

Abstract

The utility model relates to the technical field of LED chips, and discloses a chip structure, which comprises a bonding pad, a substrate, a first semiconductor layer, a second semiconductor layer and an active layer, the first semiconductor layer, the active layer and the second semiconductor layer are sequentially grown on the substrate, and the active layer is located between the first semiconductor layer and the second semiconductor layer. According to the utility model, the double-laminated electrical material design is introduced, and through structural separation, electromigration between electrodes is reduced, the working voltage of the device is reduced, and the stability of the device is further improved.

Description

Technical Field

[0001] The utility model relates to the field of LED chips, and more specifically, to a chip structure. Background Art

[0002] The LED chip structure is currently known, as shown in the figure, in which the following problems exist between the first semiconductor layer and the second semiconductor layer:

[0003] Due to moisture absorption and condensation between the electrodes, water is adsorbed on the surface of the metal electrode. Under the action of an external electric field, metal ions migrate from one electrode to the other. This process involves electrochemical reactions such as metal dissolution, ion diffusion, electrophoresis and precipitation.

[0004] Ion migration is caused by electrochemical phenomena related to solutions and potentials. It is related to the movement and precipitation reactions of metal ions generated from metal dissolution reactions, diffusion, and electrophoresis. The metal on the electrode surface is dissolved and precipitated, changing the electrode structure and composition. The formation of deposits may cause electrode short circuits or insulation failures. In high-density assembled electronic devices, changes in the distance between electrodes will affect the electrical properties of the device, thereby reducing device performance and, in severe cases, causing complete device failure. Utility Model Content

[0005] The utility model provides a chip structure to solve the technical problem in related technologies that ion migration causes the metal on the electrode surface to be dissolved and precipitated, thus changing the electrode structure and composition. The change in the distance between electrodes affects the electrical characteristics of the device, thereby reducing the device performance and causing complete failure of the device in severe cases.

[0006] The utility model provides a chip structure, comprising a pad, a substrate, a first semiconductor layer, a second semiconductor layer and an active layer;

[0007] A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially grown on a substrate, and the active layer is located between the first semiconductor layer and the second semiconductor layer;

[0008] A first conductive layer is formed on the second semiconductor layer through an ohmic contact, the first conductive layer is electrically connected to a reflective layer, the reflective layer is electrically connected to a second conductive layer, and the second conductive layer is electrically connected to a pad;

[0009] The first conductive layer, the reflective layer, the second conductive layer and the pad together constitute a first electrical connection layer;

[0010] A groove is formed through the second semiconductor layer and the active layer, and the groove extends into the first semiconductor layer;

[0011] A first insulating layer is covered on a part of the surface of the second semiconductor layer and a part of the surface of the first conductive layer, and a second insulating layer is covered on a side wall of the recess, a part of the surface of the first insulating layer and one side of the first electrical connection layer;

[0012] A third conductive layer is electrically connected on the surface of the second insulating layer and the surface of the first semiconductor layer, and the third conductive layer is a double-layer electrical material structure;

[0013] The third conductive layer and the pad together form a second electrical connection layer;

[0014] A third insulating layer is provided on the surface of the third conductive layer to prevent direct conduction between the first electrical connection layer and the second electrical connection layer.

[0015] Furthermore, the third conductive layer includes a first material and a second material, wherein the first material susceptible to electromigration is connected to the first semiconductor layer, and the second material less susceptible to electromigration is connected to a side of the first material away from the first semiconductor layer.

[0016] Furthermore, the first material and the second material have different electric potentials, and the electric potential of the second material is higher than that of the first material.

[0017] Furthermore, the first material is a multi-metal structure material with high reflectivity and high activity, and the second material is a multi-metal structure material with low activity.

[0018] Further, in the top view, the area of ​​the depression is larger than the area occupied by the first material in the depression, and the area occupied by the first material in the depression is larger than the area occupied by the second material in the depression.

[0019] Furthermore, the first conductive layer is an ohmic contact layer.

[0020] Furthermore, the reflective layer and the second conductive layer are made of multi-metal conductive materials.

[0021] Furthermore, the insulating layer is formed by a process such as vapor deposition or atomic deposition.

[0022] The beneficial effects of the utility model are:

[0023] The utility model introduces a double-stacked electrical material design, and through structural separation, reduces electrical migration between electrodes, reduces the operating voltage of the device, and further improves the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the vertical cross-section structure of the chip structure of the utility model;

[0025] Figure 2 It is a front view of the third conductive layer of the utility model;

[0026] In the figure: 100, first electrical connection layer; 110, first conductive layer; 120, reflective layer; 130, second conductive layer; 200, second electrical connection layer; 210, solder pad; 220, third conductive layer; 300, substrate; 400, insulating layer group; 410, first insulating layer; 420, second insulating layer; 430, third insulating layer; 500, active layer; 600, first material; 700, second material; 800, recess; 900, semiconductor layer group; 910, first semiconductor layer; 920, second semiconductor layer. DETAILED DESCRIPTION

[0027] The subject matter described herein will now be discussed with reference to example embodiments. It should be understood that the discussion of these embodiments is only to enable those skilled in the art to better understand and implement the subject matter described herein, and the functions and arrangements of the elements discussed may be changed without departing from the scope of protection of the contents of this specification. Each example may omit, replace or add various processes or components as needed. In addition, the features described relative to some examples may also be combined in other examples.

[0028] See also Figure 1-2 As shown, a chip structure includes a pad 210, a substrate 300, a first semiconductor layer 910, a second semiconductor layer 920 and an active layer 500;

[0029] The first semiconductor layer 910, the active layer 500 and the second semiconductor layer 920 are sequentially grown on the substrate 300, and the active layer 500 is located between the first semiconductor layer 910 and the second semiconductor layer 920;

[0030] A first conductive layer 110 is formed on the second semiconductor layer 920 through an ohmic contact, the first conductive layer 110 is electrically connected to a reflective layer 120, the reflective layer 120 is electrically connected to a second conductive layer 130, and the second conductive layer 130 is electrically connected to a pad 210;

[0031] The first conductive layer 110 , the reflective layer 120 , the second conductive layer 130 and the pad 210 together constitute a first electrical connection layer 100 ;

[0032] A groove is formed through the second semiconductor layer 920 and the active layer, and the groove extends to the inside of the first semiconductor layer 910;

[0033] A first insulating layer 410 is covered on a part of the surface of the second semiconductor layer 920 and a part of the surface of the first conductive layer 110, and a second insulating layer 420 is covered on the side wall of the recess 800, a part of the surface of the first insulating layer 410 and one side of the first electrical connection layer 100;

[0034] A third conductive layer 220 is electrically connected on the surface of the second insulating layer 420 and the surface of the first semiconductor layer 910, and the third conductive layer 220 is a double-layer electrical material structure;

[0035] The third conductive layer 220 and the pad 210 together form the second electrical connection layer 200;

[0036] A third insulating layer 430 is formed on the surface of the third conductive layer 220 and covers the surface of the third conductive layer 220 to prevent direct conduction between the first electrical connection layer 100 and the second electrical connection layer 200;

[0037] The first insulating layer 410, the second insulating layer 420 and the third insulating layer 430 constitute an insulating layer group 400;

[0038] The first insulating layer 410, the second insulating layer 420 and the third insulating layer 430 each include a stacked structure of a silicon oxide layer, a silicon nitride layer, a titanium oxide layer and an aluminum oxide layer;

[0039] The first semiconductor layer 910 and the second semiconductor layer 920 form a semiconductor layer group 900 .

[0040] It should be noted that the third conductive layer 220 includes a first material 600 and a second material 700 , wherein the first material 600 which is susceptible to electromigration is connected to the first semiconductor layer 910 , and the second material 700 which is not susceptible to electromigration is connected to a side of the first material 600 away from the first semiconductor layer 910 .

[0041] The area of ​​the recess 800 is greater than the area occupied by the first material 600 in the recess, and the area occupied by the first material 600 in the recess 800 is greater than the area occupied by the second material 700 in the recess 800;

[0042] The ratio of the area occupied by the first material 600 in the recess 800 to the area occupied by the second material 700 in the recess 800 is 1.4-3.2, and the ratio of the area of ​​the recess 800 to the area occupied by the first material 600 in the recess 800 is 1.2-2.8;

[0043] The first material 600 and the second material 700 have different electric potentials. The electric potential of the second material 700 is higher than that of the first material 600. The first material 600 is a multi-metal structure material with high reflectivity and high activity, and the second material 700 is a multi-metal structure material with low activity.

[0044] The first conductive layer 110 is an ohmic contact layer, and the first conductive layer 110 is a material selected from the group consisting of nickel, gold, palladium, indium oxide and tin oxide;

[0045] The reflective layer 120 and the second conductive layer 130 are made of a multi-metal conductive material, and the reflective layer 120 and the second conductive layer 130 are made of a material selected from the group consisting of silver, titanium, titanium tungsten, platinum, gold and cadmium;

[0046] In summary, in addition to the optimization proposed in this application, highly hydrophobic insulating materials are used to reduce moisture absorption, and protective coatings are applied to key components to block ion migration pathways;

[0047] It can also be combined with other optimization directions in chip preparation, such as selecting corrosion-resistant metal electrode materials with low ion mobility; designing a well-sealed packaging structure to prevent moisture from entering; optimizing circuit wiring, reducing the electric field strength and slowing down the ion migration rate; taking measures such as heating and baking to remove potential moisture sources; and taking effective measures from multiple aspects such as material selection and structural design to effectively inhibit ion migration, thereby improving the reliability and service life of LED devices.

[0048] The above describes an embodiment of the present embodiment, but the present embodiment is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present embodiment, ordinary technicians in this field can also make many forms, all of which are within the protection of the present embodiment.

Claims

1. A chip structure, characterized in that: It comprises a pad (210), a substrate (300), a first semiconductor layer (910), a second semiconductor layer (920) and an active layer (500); A first semiconductor layer (910), an active layer (500) and a second semiconductor layer (920) are sequentially grown on a substrate (300), and the active layer (500) is located between the first semiconductor layer (910) and the second semiconductor layer (920); A first conductive layer (110) is formed on the second semiconductor layer (920) through an ohmic contact, a reflective layer (120) is electrically connected to the first conductive layer (110), the reflective layer (120) is electrically connected to a second conductive layer (130), and the second conductive layer (130) is electrically connected to a pad (210); The first conductive layer (110), the reflective layer (120), the second conductive layer (130) and the pad (210) together form a first electrical connection layer (100); A groove is formed through the second semiconductor layer (920) and the active layer, and the groove extends into the first semiconductor layer (910); A first insulating layer (410) is covered on a portion of the surface of the second semiconductor layer (920) and a portion of the surface of the first conductive layer (110), and a second insulating layer (420) is covered on a side wall of the recess (800), a portion of the surface of the first insulating layer (410) and one side of the first electrical connection layer (100); A third conductive layer (220) is electrically connected on the surface of the second insulating layer (420) and the surface of the first semiconductor layer (910), and the third conductive layer (220) is a double-layer electrical material structure; The third conductive layer (220) and the pad (210) together form a second electrical connection layer (200); A third insulating layer (430) is provided on the surface of the third conductive layer (220) to prevent direct conduction between the first electrical connection layer (100) and the second electrical connection layer (200).

2. A chip structure according to claim 1, characterized in that: The third conductive layer (220) includes a first material (600) and a second material (700), wherein the first material (600) that is susceptible to electromigration is connected to the first semiconductor layer (910), and the second material (700) that is not susceptible to electromigration is connected to a side of the first material (600) that is away from the first semiconductor layer (910).

3. A chip structure according to claim 2, characterized in that: The first material (600) and the second material (700) have different electric potentials, and the electric potential of the second material (700) is higher than that of the first material (600).

4. A chip structure according to claim 3, characterized in that: The first material (600) is a multi-metal structure material with high reflectivity and high activity, and the second material (700) is a multi-metal structure material with low activity.

5. A chip structure according to claim 4, characterized in that: The area of ​​the depression (800) is greater than the area occupied by the first material (600) in the depression, and the area occupied by the first material (600) in the depression (800) is greater than the area occupied by the second material (700) in the depression (800).

6. A chip structure according to claim 5, characterized in that: The ratio of the area occupied by the first material (600) in the recess (800) to the area occupied by the second material (700) in the recess (800) is 1.4-3.2, and the ratio of the area of ​​the recess (800) to the area occupied by the first material (600) in the recess (800) is 1.2-2.

8.

7. A chip structure according to claim 1, characterized in that: The first conductive layer (110) is an ohmic contact layer, and the first conductive layer (110) is a material selected from the group consisting of nickel, gold, palladium, indium oxide and tin oxide.

8. A chip structure according to claim 1, characterized in that: The reflective layer (120) and the second conductive layer (130) are made of multi-metal conductive materials, and both the reflective layer (120) and the second conductive layer (130) are made of a material selected from the group consisting of silver, titanium, titanium tungsten, platinum, gold and cadmium.

9. A chip structure according to claim 1, characterized in that: The first insulating layer (410), the second insulating layer (420) and the third insulating layer (430) each include a stacked structure of a silicon oxide layer, a silicon nitride layer, a titanium oxide layer and an aluminum oxide layer.

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