High-temperature reverse bias aging protection circuit for gallium nitride radio frequency power amplifier tube

Abstract

The utility model provides a gallium nitride radio frequency power amplifier tube high-temperature reverse bias aging protection circuit, which belongs to the technical field of protection circuits, and comprises a gallium nitride radio frequency power amplifier tube, a grid voltage Vg, a reference voltage Vrfe1, a reference voltage Vrfe2, a drain voltage Vd, an LDO (Low Dropout Regulator) chip sub-circuit, a field effect tube circuit and an operational amplifier sub-circuit, the field effect transistor circuit is respectively connected with a reference voltage Vrfe1, the LDO chip sub-circuit, a drain voltage Vd, the operational amplifier sub-circuit and the gallium nitride radio frequency power amplifier tube; the operational amplifier sub-circuit is respectively connected with a grid voltage Vg, a reference voltage Vrfe2 and a gallium nitride radio frequency power amplifier tube; and the reference voltage Vrfe1 is connected with the LDO chip sub-circuit. According to the utility model, the problems that the power amplifier tubes are easy to damage due to manual operation and the chain reaction is easy to occur when the power amplifier tubes are damaged due to parallel use are solved, the fool-proof power-on sequence is realized, and the power amplifier tubes to be aged are effectively protected.

Description

Technical Field

[0001] The utility model belongs to the technical field of protection circuits, and in particular relates to a high-temperature reverse bias aging protection circuit for a gallium nitride radio frequency power amplifier tube. Background Art

[0002] In the high temperature reverse bias aging test of GaN RF power amplifier tubes, early failure products can be effectively screened out by applying electrical stress and temperature to the power amplifier tubes, thereby ensuring the long-term reliability of the delivered products. The general test conditions for high temperature reverse bias aging are about 100-150℃ in a high temperature environment, applying a negative voltage to the gate of the power amplifier tube to ensure that the power amplifier tube is turned off, and applying a positive voltage to the drain of the power amplifier tube.

[0003] At present, most of the GaN RF power amplifiers are normally open and must follow a certain switching sequence:

[0004] Power-on sequence: turn on gate voltage (negative voltage), turn on drain voltage (positive voltage);

[0005] Power-off sequence: turn off the drain voltage, turn off the gate voltage;

[0006] The existing method is to use two power supplies to supply power to the power amplifier tube, and manually control the power supply to supply power to the power amplifier tube. Without fool-proof measures, it is very easy to cause the wrong switching sequence and cause the power amplifier tube to burn out.

[0007] The reverse bias aging of power amplifier tubes is carried out in batches, with the number ranging from dozens to hundreds. The current practice is that all power amplifier tubes share the same gate power supply and drain power supply. If a power amplifier tube is short-circuited or open-circuited during the aging process, resulting in abnormal gate power supply or drain power supply, the entire batch of products will be affected. At the least, the aging process will be interrupted, and at the worst, all of them will be burned out. Utility Model Content

[0008] In view of the above-mentioned deficiencies in the prior art, the utility model provides a high-temperature reverse bias aging protection circuit for a gallium nitride radio frequency power amplifier tube, which solves the problem that the gallium nitride radio frequency power amplifier tube is easily damaged by human operation and the chain reaction that easily occurs when the gallium nitride radio frequency power amplifier tube is damaged when used in parallel.

[0009] In order to achieve the above purpose, the technical solution adopted by the utility model is: the utility model provides a high temperature reverse bias aging protection circuit of a gallium nitride radio frequency power amplifier tube, comprising: a gallium nitride radio frequency power amplifier tube, a gate voltage V g , reference voltage V rfe1 , reference voltage V rfe2 , drain voltage V d , LDO chip sub-circuit, field effect tube sub-circuit and operational amplifier sub-circuit;

[0010] The field effect tube circuit is respectively connected to the reference voltage V rfe1, LDO chip sub-circuit, drain voltage V d , an operational amplifier sub-circuit and a gallium nitride radio frequency power amplifier tube; the operational amplifier sub-circuit is respectively connected to the gate voltage V g , reference voltage V rfe2 and a gallium nitride radio frequency power amplifier tube; the reference voltage V rfe1 Connected to the LDO chip sub-circuit.

[0011] The beneficial effects of the utility model are as follows: the utility model adopts an operational amplifier subcircuit and a field effect tube subcircuit to control the power-on sequence in the protection circuit, and when the switching power is switched erroneously by humans, the gallium nitride radio frequency power amplifier tube will not be damaged, thereby realizing fool-proofing of the switching power sequence.

[0012] Furthermore, the LDO chip subcircuit includes: an LDO chip, a grounding capacitor C6, a grounding capacitor C7 and a reference voltage V rfe3 ;

[0013] The reference voltage V rfe1 The OUT pin of the LDO chip is connected to the ground capacitor C7 and the reference voltage V rfe3 connection; the GND pin of the LDO chip is grounded; the ERR pin of the LDO chip and the NR pin of the LDO chip are suspended; the reference voltage V rfe3 Connected to the field effect tube circuit.

[0014] The beneficial effect of the above further solution is that the utility model uses an LDO chip to generate a reference voltage V rfe3 , so that the protection circuit reduces an external power supply.

[0015] Furthermore, the field effect tube circuit includes: a P-MOS tube U1, an N-MOS tube Q1, an N-MOS tube Q2, a port P1, a voltage regulator diode D1, a grounding capacitor C1, a grounding capacitor C2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a grounding resistor R6, a grounding resistor R7 and a voltage V dout ;

[0016] The source of the P-MOS tube U1 is connected to the ground capacitor C1, one end of the resistor R2 and the drain voltage V d The drain of the P-MOS tube U1 is connected to the grounding resistor R7 and the second pin of the port P1 respectively; the gate of the P-MOS tube U1 is connected to the other end of the resistor R2 and one end of the resistor R1 respectively;

[0017] The drain of the N-MOS tube Q1 is connected to the other end of the resistor R1; the source of the N-MOS tube Q1 is grounded; the gate of the N-MOS tube Q1 is respectively connected to the grounding capacitor C2, the grounding resistor R6, one end of the resistor R3 and the drain of the N-MOS tube Q1; the other end of the resistor R3 is connected to the reference voltage V rfe3 connect;

[0018] The source of the N-MOS transistor Q2 is grounded; the gate of the N-MOS transistor Q2 is connected to the cathode of the voltage stabilizing diode D1, one end of the resistor R4 and one end of the resistor R5 respectively; the anode of the voltage stabilizing diode D1 is grounded; the voltage V dout The first pin of the port P1 is connected to the drain of the GaN RF power amplifier tube; the other end of the resistor R4 is connected to the reference voltage V rfe1 and operational amplifier subcircuits.

[0019] Furthermore, the operational amplifier subcircuit includes: an operational amplifier U2, a port P2, a voltage regulator diode D2, a voltage regulator diode D7, a voltage regulator diode D3, a grounded light emitting diode LED1, a capacitor C 13 , grounding capacitor C3, grounding capacitor C4, grounding capacitor C5, resistor R8, resistor R9 and voltage V gout ;

[0020] The grounding capacitor C3 is respectively connected to the other end of the resistor R4 and the reference voltage V rfe1 and the 8th pin of the operational amplifier U2; the 1st pin of the operational amplifier U2 is connected to the cathode of the voltage stabilizing diode D2; the 2nd pin of the operational amplifier U2 is connected to one end of the resistor R8; the 3rd pin of the operational amplifier U2 is respectively connected to the anode of the voltage stabilizing diode D7, the capacitor C 13 One end and the gate voltage V g The 4th pin of the operational amplifier U2 is connected to the ground capacitor C5 and the reference voltage V rfe2 connect;

[0021] The positive electrode of the voltage zener diode D2 is respectively connected to the other end of the resistor R8, one end of the resistor R9, the other end of the resistor R5, the grounded capacitor C4 and the first pin of the port P2; the other end of the resistor R9 is respectively connected to the positive electrode of the voltage zener diode D3 and the negative electrode of the grounded light emitting diode LED1; the negative electrode of the voltage zener diode D3 is grounded; the negative electrode of the voltage zener diode D7 is connected to the capacitor C 13 The other end is connected to ground; the voltage V gout The second pin of port P2 is connected to the gate of the gallium nitride radio frequency power amplifier tube.

[0022] The beneficial effect of the above further scheme is: the utility model connects a separate protection circuit to each separate GaN RF power amplifier tube to achieve non-interference between GaN RF power amplifier tubes. A light-emitting diode is used to display the power-on status. A grounding capacitor is connected to the gate of each GaN RF power amplifier tube to improve the stability of the GaN RF power amplifier tube, avoid the GaN RF power amplifier tube from oscillating and self-exciting, and avoid the influence of the surrounding high-power equipment switches to avoid burning. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a protection circuit diagram of the utility model.

[0024] Figure 2 This is a sub-circuit diagram of the LDO chip in this embodiment.

[0025] Figure 3 FIG. 1 is a circuit diagram of a field effect tube circuit in this embodiment including a P-MOS tube U1 and an N-MOS tube Q1.

[0026] Figure 4 FIG. 1 is a circuit diagram of a part of the field effect tube circuit including the N-MOS tube Q2 in this embodiment.

[0027] Figure 5 Schematic diagram of the operational amplifier subcircuit in this embodiment.

[0028] Figure 6 This is a PCB board diagram after the protection circuit in this embodiment is laid out.

[0029] Figure 7 This is the aging board placed in the aging box in this embodiment. DETAILED DESCRIPTION

[0030] The specific implementation methods of the utility model are described below to facilitate technical personnel in this technical field to understand the utility model, but it should be clear that the utility model is not limited to the scope of the specific implementation methods. For ordinary technical personnel in this technical field, as long as various changes are within the spirit and scope of the utility model defined and determined by the attached claims, these changes are obvious, and all utility model creations using the concept of the utility model are protected.

[0031] Before describing this embodiment, the following terms are explained:

[0032] LDO chip: low dropout linear regulator;

[0033] P-MOS tube: P-channel field effect tube;

[0034] N-MOS tube: N-channel field effect tube;

[0035] PCB diagram: printed circuit board diagram;

[0036] Example

[0037] like Figure 1 As shown, the utility model provides a high temperature reverse bias aging protection circuit of a gallium nitride radio frequency power amplifier tube, comprising: a gallium nitride radio frequency power amplifier tube, a gate voltage V g , reference voltage V rfe1 , reference voltage V rfe2 , drain voltage V d , LDO chip sub-circuit, field effect tube sub-circuit and operational amplifier sub-circuit;

[0038] The field effect tube circuit is respectively connected to the reference voltage V rfe1 , LDO chip sub-circuit, drain voltage V d , an operational amplifier sub-circuit and a gallium nitride radio frequency power amplifier tube; the operational amplifier sub-circuit is respectively connected to the gate voltage V g , reference voltage V rfe2 and a gallium nitride radio frequency power amplifier tube; the reference voltage V rfe1 Connected to the LDO chip sub-circuit.

[0039] In this embodiment, the high temperature reverse bias aging protection circuit of the GaN RF power amplifier tube is connected to four power supplies, and the four power supplies respectively generate a gate voltage V g is -10V, reference voltage V rfe1 +12V, reference voltage V rfe2 is -12V and the drain voltage V d is +150V.

[0040] like Figure 2 As shown, the LDO chip sub-circuit includes: an LDO chip, a grounding capacitor C6, a grounding capacitor C7, and a reference voltage V rfe3 ;

[0041] The reference voltage V rfe1 The OUT pin of the LDO chip is connected to the ground capacitor C7 and the reference voltage V rfe3 connection; the GND pin of the LDO chip is grounded; the ERR pin of the LDO chip and the NR pin of the LDO chip are suspended; the reference voltage V rfe3 Connected to the field effect tube circuit.

[0042] In this embodiment, the +12V reference voltage V rfe1 Generate +5V reference voltage V through LDO chip rfe3 , 4 power supplies are connected to the protection circuit to generate output voltage Vdout +150V and the output voltage V gout is -10V.

[0043] The field effect tube circuit includes: a P-MOS tube U1, an N-MOS tube Q1, an N-MOS tube Q2, a port P1, a voltage regulator diode D1, a grounding capacitor C1, a grounding capacitor C2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a grounding resistor R6, a grounding resistor R7 and a voltage V dout ;

[0044] like Figure 3 As shown, the source of the P-MOS tube U1 is respectively connected to the ground capacitor C1, one end of the resistor R2 and the drain voltage V d The drain of the P-MOS tube U1 is connected to the grounding resistor R7 and the second pin of the port P1 respectively; the gate of the P-MOS tube U1 is connected to the other end of the resistor R2 and one end of the resistor R1 respectively;

[0045] The drain of the N-MOS tube Q1 is connected to the other end of the resistor R1; the source of the N-MOS tube Q1 is grounded; the gate of the N-MOS tube Q1 is respectively connected to the grounding capacitor C2, the grounding resistor R6, one end of the resistor R3 and the drain of the N-MOS tube Q1; the other end of the resistor R3 is connected to the reference voltage V rfe3 connect;

[0046] In this embodiment, since the drain voltage V d It is very high, so the withstand voltage characteristics of the P-MOS tube U1 must be considered, so a resistor R1 with a resistance of 2MΩ and a resistor R2 with a resistance of 110KΩ are selected for voltage division. When the N-MOS tube Q1 is turned on, the gate voltage V gU1 The voltage is divided by two resistors to obtain a voltage of 142V. At this time, the P-MOS tube U1 is turned on, and the gate voltage of the P-MOS tube U1 is V gU1 and source voltage V sU1 The difference of 8V will not break down the transistor, which plays a role in protecting the transistor. When the P-MOS tube U1 is turned off, the drain-source voltage V ds For 150V, the drain-source voltage V ds MOS tube with a withstand voltage greater than 150V. Drain voltage V d According to the different needs of the product, the resistance values ​​of resistors R1 and R2 also need to be adjusted according to the voltage division formula to calculate the gate voltage V of the P-MOS tube U1. gU1 and source voltage V sU1 The voltage difference is adjusted to ensure that the voltage difference does not exceed the specified value.

[0047] The gate voltage V gU1The voltage division formula is: V gU1 =V d *R1 / (R1+R2).

[0048] like Figure 4 As shown, the source of the N-MOS tube Q2 is grounded; the gate of the N-MOS tube Q2 is respectively connected to the cathode of the voltage zener diode D1, one end of the resistor R4 and one end of the resistor R5; the anode of the voltage zener diode D1 is grounded; the voltage V dout The first pin of the port P1 is connected to the drain of the GaN RF power amplifier tube; the other end of the resistor R4 is connected to the reference voltage V rfe1 and operational amplifier subcircuits.

[0049] In this embodiment, the drain-source voltage V ds The withstand voltage is greater than the drain voltage V during aging d .

[0050] like Figure 5 As shown, the operational amplifier subcircuit includes: an operational amplifier U2, a port P2, a voltage regulator diode D2, a voltage regulator diode D7, a voltage regulator diode D3, a grounded light emitting diode LED1, a capacitor C 13 , grounding capacitor C3, grounding capacitor C4, grounding capacitor C5, resistor R8, resistor R9 and voltage V gout ;

[0051] The grounding capacitor C3 is respectively connected to the other end of the resistor R4 and the reference voltage V rfe1 and the 8th pin of the operational amplifier U2; the 1st pin of the operational amplifier U2 is connected to the cathode of the voltage stabilizing diode D2; the 2nd pin of the operational amplifier U2 is connected to one end of the resistor R8; the 3rd pin of the operational amplifier U2 is respectively connected to the anode of the voltage stabilizing diode D7, the capacitor C 13 One end and the gate voltage V g The 4th pin of the operational amplifier U2 is connected to the ground capacitor C5 and the reference voltage V rfe2 connect;

[0052] The positive electrode of the voltage zener diode D2 is respectively connected to the other end of the resistor R8, one end of the resistor R9, the other end of the resistor R5, the grounded capacitor C4 and the first pin of the port P2; the other end of the resistor R9 is respectively connected to the positive electrode of the voltage zener diode D3 and the negative electrode of the grounded light emitting diode LED1; the negative electrode of the voltage zener diode D3 is grounded; the negative electrode of the voltage zener diode D7 is connected to the capacitor C 13 The other end is connected to ground; the voltage V gout The second pin of port P2 is connected to the gate of the gallium nitride radio frequency power amplifier tube.

[0053] In this embodiment, a grounded light emitting diode LED1 is used to generate a gate voltage V g As an indication of whether it is normal, if the grounded light-emitting diode LED1 is always on, it is normal; if the grounded light-emitting diode LED1 is not on, it is abnormal when the power is turned on or the gate voltage of the GaN RF power amplifier tube is abnormal during the aging process; a high-temperature resistant chip capacitor is connected to the gate of each GaN RF power amplifier tube.

[0054] In this embodiment, the utility model controls the power-on sequence through an operational amplifier U2, two N-MOS tubes Q1 and Q2, and a P-MOS tube U1 to achieve switch sequence foolproofing. g Greater than the drain voltage V d When it is turned on, and the P-MOS tube gate voltage V g Less than the drain voltage V d When conduction is achieved.

[0055] In this embodiment, each GaN RF power amplifier tube is provided with an independent protection circuit, so that even if a single GaN RF power amplifier tube is abnormal, it will not affect other GaN RF power amplifier tubes, will not cause batch damage, and will not interrupt the aging process.

[0056] In this embodiment, Figure 1 As shown, the production quantity of each electronic component is as follows: the capacitance of grounding capacitor C1, grounding capacitor C2, grounding capacitor C3, grounding capacitor C4, grounding capacitor C5, grounding capacitor C6 and grounding capacitor C7 are all 4.7μF; 13 The capacitance is 0.1μF; the resistance value of resistor R1 is 2MΩ, the resistance value of resistor R2 is 110kΩ, the resistance value of resistor R3 is 1kΩ, the resistance value of resistor R4 is 11kΩ, the resistance value of resistor R5 is 9.1kΩ, the resistance value of grounding resistor R6 is 2kΩ, the resistance value of grounding resistor R7 is 2MΩ, the resistance value of resistor R8 is 1kΩ, and the resistance value of resistor R9 is 10kΩ.

[0057] In this embodiment, when the gate voltage V is -10V g When the other power supplies are turned on, the voltage of the first pin of the operational amplifier U2 is 0, and the gate voltage of the N-MOS tube Q2 is regulated by the reference voltage V rfe1 , the resistor R4 with a resistance of 11kΩ and the resistor R5 with a resistance of 9.1kΩ divide the voltage. The gate voltage of the N-MOS tube Q2 is obtained according to the voltage division formula V gQ2 =5.7V, N-MOS tube Q2 is turned on, making the gate voltage of N-MOS tube Q1 V gQ1 Pull down to 0V, at this time, the N-MOS tube Q1 is turned off, and the gate voltage V gU1is 150V. At this time, the gate voltage of P-MOS tube U1 and the drain voltage V dU1 Similarly, the P-MOS tube U1 is turned off. At this time, the voltage of the first pin of the port P1 is 0, and the drain voltage of the GaN RF power amplifier tube is 0, and the GaN RF power amplifier tube will not be damaged.

[0058] The gate voltage of the N-MOS tube Q2 is V gQ2 The voltage division formula is: V gQ2 =V rfe1 *R5 / (R4+R5).

[0059] In this embodiment, when the drain voltage V d When it is not turned on and other power supplies are turned on, the first pin of the operational amplifier U2 has an output voltage of -10V, the gate voltage of the GaN RF power amplifier tube -10V is in the cut-off state, and the drain voltage of the GaN RF power amplifier tube is 0. At this time, the GaN RF power amplifier tube will not be damaged.

[0060] In this embodiment, when the +12V reference voltage V rfe1 When not turned on, the gate voltage of N-MOS tube Q1 is V gQ1 is 0, the N-MOS tube Q1 is turned off, and the gate voltage V gU1 is 150V, the P-MOS tube U1 is cut off, and the drain voltage of the GaN RF power amplifier tube is 0. At this time, the GaN RF power amplifier tube will not be damaged.

[0061] In this embodiment, when the -12V reference voltage V rfe2 When not turned on, the gate voltage of N-MOS tube Q2 is rfe1 , resistors R4, R5 and R9 divide the voltage, and the gate voltage of N-MOS tube Q2 is obtained according to the voltage division formula V gQ2 =6.7V, N-MOS tube Q2 is turned on so that the gate voltage of N-MOS tube Q2 is V gQ2 Pull it down to 0, and then the N-MOS tube Q1 is turned off. The N-MOS tube Q1 is turned off, making the gate voltage V gU1 is 150V, at this time the gate voltage of P-MOS tube U1 is V gU1 With drain voltage V dU1 Similarly, the P-MOS tube U1 is turned off. At this time, the voltage of the first pin of the port P1 is 0, and the drain voltage of the GaN RF power amplifier tube is 0, and the GaN RF power amplifier tube will not be damaged.

[0062] In this embodiment, Figure 6 As shown, Figure 1The PCB layout is obtained after the circuit diagram is laid out. Each block in the figure contains an independent protection circuit module, and there are a total of 10 protection modules on a PCB. This PCB is placed outside the aging box. The PCB board can be ordinary FR4 board, and the components on the board can be conventional temperature-resistant components.

[0063] In this embodiment, Figure 7 As shown, Figure 6 For the aging board placed in the aging box, there are 28 independent positions for installing test sockets on the aging board. The aging board is connected to the PCB layout through high temperature resistant wires. The components on the board use high temperature resistant capacitors with a temperature range of -55℃ to 150℃.

[0064] In this embodiment, Figure 7 As shown in the figure, capacitor ABC3, capacitor ABC4, capacitor ABC5, and capacitor ABC6, the typical capacitance of capacitor ABC3 and capacitor ABC4 is 1nF, and the capacitance of capacitor ABC5 and capacitor ABC6 is 4.7μF.

[0065] In this embodiment, Table 1 is a main connection table of the gallium nitride radio frequency power amplifier tube and the protection circuit.

[0066] Table 1

[0067]

Claims

1. A high temperature reverse bias aging protection circuit for a gallium nitride radio frequency power amplifier tube, characterized in that: include: GaN RF power amplifier tube, gate voltage V g , reference voltage V rfe1 , reference voltage V rfe2 , drain voltage V d , LDO chip sub-circuit, field effect tube sub-circuit and operational amplifier sub-circuit; The field effect tube circuit is respectively connected to the reference voltage V rfe1 , LDO chip sub-circuit, drain voltage V d , an operational amplifier sub-circuit and a gallium nitride radio frequency power amplifier tube; the operational amplifier sub-circuit is respectively connected to the gate voltage V g , reference voltage V rfe2 and a gallium nitride radio frequency power amplifier tube; the reference voltage V rfe1 Connected to the LDO chip sub-circuit.

2. The high temperature reverse bias aging protection circuit of gallium nitride radio frequency power amplifier tube according to claim 1, characterized in that: The LDO chip subcircuit includes: an LDO chip, a grounding capacitor C6, a grounding capacitor C7, and a reference voltage V rfe3 ; The reference voltage V rfe1 The OUT pin of the LDO chip is connected to the ground capacitor C7 and the reference voltage V rfe3 connection; the GND pin of the LDO chip is grounded; the ERR pin of the LDO chip and the NR pin of the LDO chip are suspended; the reference voltage V rfe3 Connected to the field effect tube circuit.

3. The high temperature reverse bias aging protection circuit of gallium nitride radio frequency power amplifier tube according to claim 2, characterized in that: The field effect tube circuit includes: a P-MOS tube U1, an N-MOS tube Q1, an N-MOS tube Q2, a port P1, a voltage regulator diode D1, a grounding capacitor C1, a grounding capacitor C2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a grounding resistor R6, a grounding resistor R7 and a voltage V dout ; The source of the P-MOS tube U1 is connected to the ground capacitor C1, one end of the resistor R2 and the drain voltage V d The drain of the P-MOS tube U1 is connected to the grounding resistor R7 and the second pin of the port P1 respectively; the gate of the P-MOS tube U1 is connected to the other end of the resistor R2 and one end of the resistor R1 respectively; The drain of the N-MOS tube Q1 is connected to the other end of the resistor R1; the source of the N-MOS tube Q1 is grounded; the gate of the N-MOS tube Q1 is respectively connected to the grounding capacitor C2, the grounding resistor R6, one end of the resistor R3 and the drain of the N-MOS tube Q1; the other end of the resistor R3 is connected to the reference voltage V rfe3 connect; The source of the N-MOS transistor Q2 is grounded; the gate of the N-MOS transistor Q2 is connected to the cathode of the voltage stabilizing diode D1, one end of the resistor R4 and one end of the resistor R5 respectively; the anode of the voltage stabilizing diode D1 is grounded; the voltage V dout The first pin of the port P1 is connected to the drain of the GaN RF power amplifier tube; the other end of the resistor R4 is connected to the reference voltage V rfe1 and operational amplifier subcircuits.

4. The high temperature reverse bias aging protection circuit of gallium nitride radio frequency power amplifier tube according to claim 3, characterized in that: The operational amplifier subcircuit includes: an operational amplifier U2, a port P2, a voltage regulator diode D2, a voltage regulator diode D7, a voltage regulator diode D3, a grounded light emitting diode LED1, a capacitor C 13 , grounding capacitor C3, grounding capacitor C4, grounding capacitor C5, resistor R8, resistor R9 and voltage V gout ; The grounding capacitor C3 is respectively connected to the other end of the resistor R4 and the reference voltage V rfe1 and the 8th pin of the operational amplifier U2; the 1st pin of the operational amplifier U2 is connected to the cathode of the voltage stabilizing diode D2; the 2nd pin of the operational amplifier U2 is connected to one end of the resistor R8; the 3rd pin of the operational amplifier U2 is respectively connected to the anode of the voltage stabilizing diode D7, the capacitor C 13 One end and the gate voltage V g The 4th pin of the operational amplifier U2 is connected to the ground capacitor C5 and the reference voltage V rfe2 connect; The positive electrode of the voltage zener diode D2 is respectively connected to the other end of the resistor R8, one end of the resistor R9, the other end of the resistor R5, the grounded capacitor C4 and the first pin of the port P2; the other end of the resistor R9 is respectively connected to the positive electrode of the voltage zener diode D3 and the negative electrode of the grounded light emitting diode LED1; the negative electrode of the voltage zener diode D3 is grounded; the negative electrode of the voltage zener diode D7 is connected to the capacitor C 13 The other end is connected to ground; the voltage V gout The second pin of port P2 is connected to the gate of the gallium nitride radio frequency power amplifier tube.

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