Photoelectric device based on alignment bonding

Abstract

The utility model relates to a photoelectric device based on alignment bonding, which comprises a driving wafer and a pixel unit, a second insulating layer is arranged on the driving wafer, and the outer edge wall body of the pixel unit comprises a first wall body layer attached to the side wall of a pixel main body. The N-type semiconductor layer and the P-type semiconductor layer in the pixel unit are insulated through a first wall body layer; a first insulating layer is arranged between the second insulating layer and the P-type semiconductor layer, the first insulating layer and the second insulating layer are respectively provided with a through hole filled with an anode metal piece, the through holes of the first insulating layer and the second insulating layer are in one-to-one correspondence, the anode metal pieces in the through holes are mutually bonded to form a bonding main body, and the P-type semiconductor layer is electrically connected with the driving wafer through the bonding main body. According to the utility model, the anode connection effect can be effectively ensured, and arrangement and processing are more convenient; the phenomenon of electric leakage of the pixel units can be better avoided, and the reliability of the photoelectric device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a photoelectric device based on alignment bonding. Background Art

[0002] The pixel unit 40 of the existing LED optoelectronic device generally includes a P-type semiconductor layer 4013 and an N-type semiconductor layer 4011. Figure 1 As shown, the P-type semiconductor layer 4013 needs to be electrically connected to the anode contact 101 of the driving wafer 50. The existing pixel unit 40 is usually bonded to the driving wafer 50 by bonding the bonding metal layer 10 to achieve anode connection. However, when there is an insulating dielectric layer 20 between the P-type semiconductor layer 4013 and the bonding metal layer 10, it is necessary to set a conductive anode connector 30 outside the pixel unit 40 to achieve anode connection, which makes the optoelectronic device structure more complicated and difficult to process. Once the anode connector is deformed or installed incorrectly, it is easy to cause a short circuit leakage between the P-type semiconductor layer 4013 and the N-type semiconductor layer 4011, thereby causing the LED optoelectronic device to fail.

[0003] Therefore, the existing LED optoelectronic device anode connection structure is complex and difficult to process, and cannot effectively ensure the convenience of anode connection. It is also prone to short circuit leakage, thereby failing to ensure the reliability of the LED optoelectronic device. Utility Model Content

[0004] Therefore, the technical problem to be solved by the utility model is to overcome the defects of the LED optoelectronic device in the prior art that the convenience of anode connection cannot be effectively guaranteed and short circuit leakage easily occurs, so as to improve the reliability of the LED optoelectronic device.

[0005] In order to solve the above technical problems, the utility model provides an optoelectronic device based on alignment bonding, comprising:

[0006] A driving wafer, wherein a second insulating layer is disposed on the driving wafer, the second insulating layer is provided with a through hole, and the through hole is filled with an anode metal piece;

[0007] A pixel unit, wherein the pixel unit comprises a pixel body and an outer edge wall body, wherein the outer edge wall body is arranged on a side wall of the pixel body, wherein the outer edge wall body comprises a first wall body layer, wherein the first wall body layer is an insulator, and the first wall body layer is in contact with the side wall of the pixel body;

[0008] The pixel body comprises a P-type semiconductor layer, an active layer and an N-type semiconductor layer which are sequentially arranged in a direction away from the driving wafer; the N-type semiconductor layer and the P-type semiconductor layer in each pixel unit are insulated by the first wall layer;

[0009] A first insulating layer is further provided between the second insulating layer and the P-type semiconductor layer of the pixel unit, a through hole is also provided on the first insulating layer, an anode metal piece is filled in the through hole, the through hole of the first insulating layer corresponds to the through hole of the second insulating layer one by one, the anode metal piece in the through hole of the first insulating layer and the corresponding anode metal piece in the through hole of the second insulating layer are bonded to each other to form a bonding body, and the P-type semiconductor layer is electrically connected to the driving wafer through the bonding body;

[0010] Wherein, the N-type semiconductor layers in all the pixel units are connected via a common cathode.

[0011] In one embodiment of the utility model, the anode metal part of the first insulating layer and / or the second insulating layer includes a main body end, the main body end is located in the through hole, an extended end is formed on the main body end, and the length of the extended end is greater than the length of the main body end.

[0012] In one embodiment of the present invention, the extended end of the anode metal piece in the bonding body is located between the first insulating layer and the second insulating layer.

[0013] In one embodiment of the present invention, a third insulating layer is provided between the first insulating layer and the second insulating layer, and the extended end is located in the third insulating layer.

[0014] In one embodiment of the present invention, the length of the extended end is not less than 0.5 times the length of the pixel body.

[0015] In one embodiment of the present invention, the length of the through hole is 0.1 to 0.5 times the length of the pixel body.

[0016] In one embodiment of the present invention, the outer edge wall body further includes a second wall body layer, and the second wall body layer is in contact with the outer wall of the first wall body layer.

[0017] In one embodiment of the present invention, the second wall layer is a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer.

[0018] In one embodiment of the present invention, a step portion is formed on one end of the first wall layer close to the driving wafer, and the second wall layer is located on the step portion.

[0019] In one embodiment of the present invention, metal grids are further provided on both sides of each pixel unit, and the metal grids are electrically connected to the common cathode.

[0020] In one embodiment of the present invention, the metal grid is located between the common cathode and the first insulating layer.

[0021] The above technical solution of the utility model has the following advantages compared with the prior art:

[0022] In the optoelectronic device based on alignment bonding described in the utility model, the through holes of the first insulating layer and the through holes of the second insulating layer are aligned one by one, so that the anode metal parts in the through holes of the first insulating layer and the corresponding anode metal parts in the through holes of the second insulating layer are bonded to each other to form a conductive bonding body, which can not only effectively ensure the anode current enhancement effect, but also be more convenient for layout and processing, and also help to avoid leakage inside the pixel unit; in addition, the N-type semiconductor layer and the P-type semiconductor layer are insulated by the first wall layer, which can also better avoid short-circuit leakage in the pixel unit, and can effectively improve the reliability of the optoelectronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the content of the utility model more clearly understood, the utility model is further described in detail below based on specific embodiments of the utility model in combination with the accompanying drawings.

[0024] Figure 1 It is a structural schematic diagram of an LED optoelectronic device in the prior art;

[0025] Figure 2 It is a structural schematic diagram of a first embodiment of the optoelectronic device of the utility model;

[0026] Figure 3 It is a structural schematic diagram of a second embodiment of the optoelectronic device of the utility model;

[0027] Figure 4 It is a structural schematic diagram of a third embodiment of the optoelectronic device of the utility model;

[0028] Figure 5 It is a structural schematic diagram of a fourth embodiment of the optoelectronic device of the utility model;

[0029] Figure 6 It is a structural schematic diagram of the driving light circle of the utility model;

[0030] Figure 7 It is a schematic structural diagram of an implementation method of the compound semiconductor of the utility model;

[0031] Figure 8 It is a structural schematic diagram of another embodiment of the compound semiconductor of the utility model;

[0032] Fig. 9 The utility model adopts Figure 7The flow chart of preparing optoelectronic devices using compound semiconductors shown;

[0033] Fig.10 The utility model adopts Figure 8 The flow chart of preparing optoelectronic devices using compound semiconductors shown;

[0034] Fig.11 This is a preparation flow chart of an embodiment of the optoelectronic device of the utility model (with a metal grid);

[0035] Description of the Figures in the Specification:

[0036] 10. bonding metal layer; 101. anode contact; 20. insulating dielectric layer; 30. anode connector;

[0037] 40, pixel unit; 401, pixel body; 4011, N-type semiconductor layer; 4012, active layer; 4013, P-type semiconductor layer; 4014, P-type ohmic contact layer; 402, outer edge wall; 4021, first wall layer; 40211, step portion; 4022, second wall layer;

[0038] 50. Driving wafer;

[0039] 60, first insulating layer; 601, through hole; 602, anode metal piece; 6021, body end; 6022, extension end;

[0040] 70. Second insulating layer; 80. Bonding body; 90. Third insulating layer; 100. Common cathode; 110. Metal grid; 120. Compound semiconductor; 1201. Substrate. DETAILED DESCRIPTION

[0041] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present disclosure and its application or use.

[0042] In the description of the present utility model, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more.

[0043] This embodiment provides an optoelectronic device based on alignment bonding, which can conveniently and effectively realize the anode connection of the LED optoelectronic device and avoid short circuit leakage, thereby improving the reliability of the LED optoelectronic device.

[0044] The following will be combined with the attached Figure 2-Figure 11 , the structure of this embodiment is further described.

[0045] Embodiment 1

[0046] Reference Figure 2 As shown, this embodiment discloses an optoelectronic device based on alignment bonding, including a driving wafer 50 and a pixel unit 40;

[0047] A second insulating layer 70 is disposed on the driving wafer 50 , and a through hole 601 is disposed on the second insulating layer 70 . The through hole 601 is filled with an anode metal piece 602 .

[0048] The pixel unit 40 includes a pixel body 401 and an outer wall 402. The outer wall 402 is disposed on the side wall of the pixel body 401. The outer wall 402 includes a first wall layer 4021. The first wall layer 4021 is an insulator. The first wall layer 4021 is attached to the side wall of the pixel body 401.

[0049] The pixel body 401 includes a P-type semiconductor layer 4013, an active layer 4012 and an N-type semiconductor layer 4011 which are sequentially arranged in a direction away from the driving wafer 50; wherein the active layer 4012 is used to emit light; the N-type semiconductor layer 4011 and the P-type semiconductor layer 4013 in each pixel unit 40 are insulated by a first wall layer 4021;

[0050] A first insulating layer 60 is further provided between the second insulating layer 70 and the P-type semiconductor layer 4013 of the pixel unit 40. A through hole 601 is also provided on the first insulating layer 60. The through hole 601 is filled with an anode metal piece 602. The through hole 601 of the first insulating layer 60 corresponds to the through hole 601 of the second insulating layer 70. The anode metal piece 602 in the through hole 601 of the first insulating layer 60 and the corresponding anode metal piece 602 in the through hole 601 of the second insulating layer 70 are bonded to each other to form a bonding body 80. The P-type semiconductor layer 4013 is electrically connected to the driving wafer 50 through the bonding body 80.

[0051] The N-type semiconductor layers 4011 in all pixel units 40 are connected via a common cathode 100 , and the common cathode 100 is deposited outside the N-type semiconductor layers 4011 .

[0052] In the above structure, by respectively setting the first insulating layer 60 and the second insulating layer 70, the through hole 601 of the first insulating layer 60 and the through hole 601 of the second insulating layer 70 are aligned one by one, so that the anode metal member 602 in the through hole 601 of the first insulating layer 60 and the corresponding anode metal member 602 in the through hole 601 of the second insulating layer 70 are bonded to each other to form a bonding body 80, and the bonding body 80 is used to realize the electrical connection between the P-type semiconductor and the driving wafer 50, avoiding the need to set the anode connection structure outside the pixel unit 40, and the structure is more The device is simple and can not only effectively ensure the anode current enhancement effect, but also is easier to arrange and process, and is also beneficial to avoid leakage inside the pixel unit 40; in addition, by setting an outer edge wall 402 at the side wall of the pixel body 401 of the optical element, the N-type semiconductor layer 4011 and the P-type semiconductor layer 4013 are insulated by the first wall layer 4021, which can better avoid short circuit leakage between the N-type semiconductor layer 4011 and the P-type semiconductor layer 4013, thereby effectively ensuring the reliability of the optoelectronic device.

[0053] In one embodiment, the length M1 of the through hole 601 is 0.1 to 0.5 times the length L2 of the pixel body 401 , so as to better ensure the connection area of ​​the anode metal member 602 .

[0054] In one embodiment, if Figure 3-Figure 4 As shown, the outer edge wall 402 further includes a second wall layer 4022 , and the second wall layer 4022 fits with the outer wall of the first wall layer 4021 so that there is no gap therebetween.

[0055] Furthermore, the second wall layer 4022 is a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer, so as to enhance the optical and electrical functions.

[0056] By providing a reflective layer in the second wall layer 4022, the effect of side reflection can be achieved, which is more conducive to the realization of omnidirectional reflection, greatly improving the brightness of the pixel unit 40 and the collimation of light, and obtaining better performance and a smaller divergence angle.

[0057] By providing a conductive layer in the second wall layer 4022 , it is easier to electrically connect the pixel unit with other components.

[0058] The reflective layer may be formed by depositing a high reflectivity metal such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh) or platinum (Pt);

[0059] The conductive layer can be formed by depositing highly conductive metals such as aluminum (Al), copper (Cu), tungsten (W), and titanium (Ti).

[0060] The second wall layer 4022 may also be a laminate of a transparent conductive layer and a metal layer, such as a silver or titanium tungsten film layer laminated on zinc oxide.

[0061] In one embodiment, if Figure 3 As shown, a step portion 40211 is formed at one end of the first wall layer 4021 close to the driving wafer 50 , and the second wall layer 4022 is located on the step portion 40211 .

[0062] In another embodiment, if Figure 4 As shown, the end of the first wall layer 4021 close to the driving wafer 50 may also adopt a structure without a step portion 40211 .

[0063] In one embodiment, a P-type ohmic contact layer 4014 is further disposed between the P-type semiconductor layer 4013 and the first insulating layer 60 .

[0064] The material of the above-mentioned P-type ohmic contact layer 4014 includes a single layer or a stack of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or a single layer or a stack of metals such as Ni, Cr, Au, Ag, Zn, Be, Al (nickel, chromium, gold, silver, zinc, beryllium, aluminum), or an alloy, or a stack of transparent metal oxides and metals.

[0065] In one embodiment, the angle θ between the pixel body 401 and the first insulating layer 60 is about 90°, specifically 60° to 120°, preferably 75° to 105°.

[0066] In one embodiment, the length L2 of the pixel body 401 is 0.5 um to 50 um.

[0067] The length direction is the direction perpendicular to the "direction away from the drive unit", such as Figure 1shown.

[0068] In one embodiment, the thickness L1 of the first wall layer 4021 is 50 nm to 1500 nm. The selection of this thickness range can maximize the thickness requirements of the dielectric layer of the omnidirectional reflection structure required for different wavelengths while achieving ideal insulation packaging.

[0069] In one embodiment, metal grids 110 are further disposed on both sides of each pixel unit 40 , and the metal grids 110 are electrically connected to the common cathode 100 , so that the cathode current is enhanced through the metal grids 110 .

[0070] Furthermore, the common cathode 100 can be a combination of one or more of ITO (tin-doped indium oxide) film, AZO (aluminum-doped zinc oxide) film, ATO (antimony-doped tin oxide) film, FTO (fluorine-doped tin dioxide) film, or a metal stack formed by annealing after thin film coating of Al, Au, and Ag on the surface of ITO to enhance the current transmission capacity of the common cathode layer.

[0071] This embodiment also discloses a method for preparing an optoelectronic device based on alignment bonding, comprising:

[0072] 1) Prepare the driving wafer 50, such as Figure 6 As shown, a second insulating layer 70 is provided on the driving wafer 50, and the second insulating layer 70 is provided with a through hole 601, and the through hole 601 is filled with metal to form an anode metal part 602; this process can be prepared by a Damascus process;

[0073] and preparing a compound semiconductor 120, such as Figure 7 As shown, the compound semiconductor 120 includes a substrate 1201, and an N-type semiconductor layer 4011, an active layer 4012, a P-type semiconductor layer 4013 and a first insulating layer 60 which are sequentially formed in a direction away from the substrate 1201;

[0074] A through hole 601 is provided on the first insulating layer 60, and metal is filled in the through hole 601 to form an anode metal member 602, and the through hole 601 of the second insulating layer 70 corresponds to the through hole 601 of the first insulating layer 60 one by one; this process can be prepared by a Damascene process;

[0075] The material of the anode metal member 602 may include one or more of TiN (titanium nitride), Al (aluminum), TaN (tantalum nitride) and Cu (copper).

[0076] 2) If Fig. 9In the middle a stage, the anode metal piece 602 in the through hole 601 of the first insulating layer 60 and the corresponding anode metal piece 602 in the through hole 601 of the second insulating layer 70 are bonded to each other to form a bonding body 80, so that the P-type semiconductor layer 4013 is electrically connected to the driving wafer 50 through the bonding body 80;

[0077] 3) If Fig. 9 In the middle b stage, the compound semiconductor 120 is processed to form a pixel unit 40 corresponding to the bonding body 80;

[0078] The pixel unit 40 includes a pixel body 401 and an outer wall 402, the outer wall 402 is arranged on the side wall of the pixel body 401, and the outer wall 402 includes a first wall layer 4021, the first wall layer 4021 is an insulator, and the first wall layer 4021 is in contact with the side wall of the pixel body 401; each pixel body 401 includes a P-type semiconductor layer 4013, an active layer 4012 and an N-type semiconductor layer 4011 arranged in sequence in a direction away from the driving wafer 50; the N-type semiconductor layer 4011 and the P-type semiconductor layer 4013 in each pixel unit 40 are insulated by the first wall layer 4021;

[0079] 4) If Fig. 9 In the middle e stage, the N-type semiconductor layer 4011 in the pixel unit 40 is connected to the common cathode 100 to achieve cathode interconnection and connect to the outside world through the common cathode 100.

[0080] Specifically, the common cathode 100 may be formed by depositing a transparent conductive film on the N-type semiconductor side of all pixel units 40 by sputtering, evaporation, or the like.

[0081] The pixel unit 40 and the bonding body 80 may correspond one to one, or a plurality of bonding bodies 80 may correspond to one pixel unit 40 .

[0082] The compound semiconductor 120 generally refers to a compound formed by two or more elements. For example, the compound semiconductor 120 here is mainly a light-emitting diode epitaxial material, such as an InGaN ternary material system or an AlGaInP quaternary material system, and its luminous wavelength can cover the entire band from ultraviolet light, visible light and infrared light.

[0083] Taking the Micro-LED field as an example, some compound materials involved in this embodiment are shown in Table 1 below. In some practical applications, the film layer of the compound will be more complicated, or there will be cross-use of materials, mainly including P-type semiconductor layer materials, N-type semiconductor layer materials and an active layer (MQW quantum well) sandwiched between the two:

[0084] Table 1. Materials of various compound films

[0085] Layer Name Material Material Material Material Material Material Material P-type semiconductor layer GaP GaAs GaAs GaAs AlGaN GaN GaN MQW Active Quantum Well AlGaInP AlGaInP InGaAs AlGaAs InGaN InGaN InGaN N-type semiconductor layer GaAs AlGaAs AlGaAs GaAs GaN GaN GaN Substrate GaAs GaAs GaAs GaAs GaN Si Sapphire

[0086] In one embodiment, a method of processing a compound semiconductor 120 to form a pixel unit 40 corresponding to a bonding body 80 includes the following steps:

[0087] Step S1), removing the substrate 1201 of the compound semiconductor 120;

[0088] In one embodiment, after removing the substrate 1201 , the compound semiconductor 120 may be further thinned to expose the N-type semiconductor layer 4011 , so as to prepare a patterned etching mask on the N-type semiconductor layer 4011 .

[0089] Step S2), as Fig. 9 In the middle b stage, the compound semiconductor 120 is etched by a first etching method, and the first insulating layer 60 is used as an etching stop layer during etching, and a pixel body 401 corresponding to the bonding body 80 is obtained after etching;

[0090] The first etching method is a dry etching method or a wet etching method.

[0091] Step S3), as Fig. 9 In the middle stage c, a first wall layer 4021 is deposited outside the pixel body 401, and the first wall layer 4021 is etched by dry etching, such as Fig. 9 In stage d, only the first wall layer 4021 located at the side wall of the pixel body 401 is retained after etching.

[0092] In one embodiment, there is a second wall layer 4022 outside the first wall layer 4021. In step S3), the second wall layer 4022 can be prepared in the following two ways: one is an overall etching method, and the other is a layered etching method;

[0093] The overall etching method is as follows: in step S3), after the first wall layer 4021 is deposited on the outside of the pixel body 401, the second wall layer 4022 needs to be deposited. After all the deposition is completed, the overall structure composed of the first wall layer 4021 and the second wall layer 4022 is etched overall by dry etching. After etching, only the first wall layer 4021 and the second wall layer 4022 located at the side wall of the pixel body 401 are retained;

[0094] In the pixel unit 40 structure obtained by the above-mentioned preparation method, a step portion 40211 is formed at one end of the first wall layer 4021 close to the driving unit, and the second wall layer 4022 is located on the step portion 40211. Figure 3 .

[0095] For example, Fig.10 The overall etching method is used in the middle ce stage.

[0096] The layered etching method is as follows: in step S3), after the first wall layer 4021 is deposited on the outside of the pixel body 401, the first wall layer 4021 is first etched by dry etching, and only the first wall layer 4021 located at the side wall of the pixel body 401 is retained after etching, and then the second wall layer 4022 is deposited on the outside of the first wall layer 4021. After the deposition is completed, the second wall layer 4022 is etched by dry etching, and only the second wall layer 4022 located at the side wall of the pixel body 401 is retained after etching.

[0097] In the pixel unit 40 structure obtained by the above-mentioned preparation method, there is no step portion 40211 between the first wall layer 4021 and the second wall layer 40223. Figure 4 .

[0098] The preparation method of the outer edge wall 402 of the above-mentioned pixel unit does not require a photolithography machine during preparation, but is implemented by dry etching, which can get rid of the need for more advanced photolithography machines and does not require an exposure process. It avoids the defects of graphic failure, large overlay offset, and high production cost caused by the use of photolithography machines for graphic etching in the prior art. At the same time, it can also effectively ensure the preparation accuracy, achieve in-situ or self-alignment type accuracy, and achieve sub-micron accuracy using micron-level equipment technology.

[0099] In one embodiment, after the pixel unit 40 is prepared, a metal grid 110 needs to be formed on both sides of each pixel unit 40. The metal grid 110 can be prepared before or after the common cathode 100 is prepared.

[0100] In one embodiment, the first insulating layer 60 and the second insulating layer 70 both include one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide or niobium oxide.

[0101] In one embodiment, the first wall layer 4021 includes one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide or niobium oxide.

[0102] Embodiment 2

[0103] like Figure 5As shown, the main difference between this embodiment and the first embodiment is that the anode metal piece 602 of one of the first insulating layer 60 or the second insulating layer 70 includes a body end 6021 and an extension end 6022, the body end 6021 is located in the through hole 601, the body end 6021 is formed with the extension end 6022, and the length of the extension end 6022 is greater than the length of the body end 6021. Alternatively, the anode metal piece 602 of the first insulating layer 60 and the second insulating layer 70 both include a body end 6021 and an extension end 6022.

[0104] The length direction is the direction perpendicular to the "direction away from the drive unit", such as Figure 5 shown.

[0105] The above structure increases the contact area of ​​the anode metal member 602 by setting the extension end 6022, reduces the precision requirement for alignment and bonding, and is easier to implement. It is also beneficial to enhance the anode connection strength and the anode current.

[0106] Preferably, the method of forming the through hole 601 on the first insulating layer 60 and / or the second insulating layer 70 and filling the through hole 601 with metal material to form the anode metal member 602 may be a dual damascene process.

[0107] In one embodiment, the extended end 6022 of the anode metal member 602 in the bonding body 80 is located between the first insulating layer 60 and the second insulating layer 70 to better ensure connection reliability.

[0108] Furthermore, a third insulating layer 90 is disposed between the first insulating layer 60 and the second insulating layer 70 , and the extended end 6022 is located in the third insulating layer 90 .

[0109] In one embodiment, the third insulating layer 90 includes one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide or niobium oxide.

[0110] The extended end 6022 can be used as a metal reflective layer to ensure that the bottom surface reflection function is achieved on the basis of the anode connection, thereby enhancing the reflection effect of the pixel unit 40 and improving the light output intensity and brightness of the pixel unit 40 .

[0111] In one embodiment, the length of the extension end 6022 is M2, and the length of the pixel body 401 is L2, then M2≥0.5*L2, thereby better ensuring the anode connection strength and increasing the anode current.

[0112] Further, the length M1 of the through hole 601 is 0.1 to 0.5 times the length L2 of the pixel body 401 , that is, M1=(0.1 to 0.5)*L2.

[0113] like Fig.10As shown, this embodiment also discloses a method for preparing an optoelectronic device based on alignment bonding. The preparation method is basically the same as that of the first embodiment, except that when preparing the compound semiconductor 120 and / or the driver wafer 50, an anode metal member 602 including a body end 6021 and an extension end 6022 needs to be prepared. The structure of the compound semiconductor 120 is shown in FIG. Figure 8 The preparation method of the optoelectronic device will not be described in detail here.

[0114] Embodiment 3

[0115] like Fig.11 As shown, the main difference between this embodiment and the first embodiment is that metal grids 110 are also provided on both sides of each pixel unit 40, the metal grids 110 are electrically connected to the common cathode 100, and the metal grids 110 are located between the common cathode 100 and the first insulating layer 60, so as to facilitate preparation and ensure the reliability of the connection.

[0116] Furthermore, there is a gap between the metal grid 110 and the adjacent pixel units 40 .

[0117] like Fig.11 In stage a, the second wall layer 4022 can be used when preparing the metal grid 110. If the second wall layer 4022 is a conductive layer, when etching the second wall layer 4022, in addition to retaining the second wall layer 4022 at the side wall of the pixel body, part of the second wall layer 4022 located on the upper part of the first insulating layer 60 and away from the pixel unit 40 can also be retained and used as the metal grid 110, that is, the metal grid 110 is formed on both sides of each pixel unit 40, and there is a gap between the metal grid 110 and the adjacent pixel unit 40; this method can make the deposited second wall layer 4022 be utilized to the greatest extent, and it is also conducive to simplifying the preparation process of the metal grid 110.

[0118] After the metal grid 110 is prepared, Fig.11 In stage b, a common cathode 100 is deposited outside the second wall layer 4022 so that the metal grid 110 is located between the common cathode 100 and the bonding body 80 to enhance the electrical connection of the cathode.

[0119] It is understandable that the metal grid 110 may be prepared in other ways, or the common cathode 100 may be prepared first and then the metal grid 110 may be prepared.

[0120] The above-mentioned embodiments are based on an aligned and bonded optoelectronic device and a preparation method thereof, so that the through holes of the first insulating layer and the through holes of the second insulating layer are aligned one by one, so that the anode metal parts in the through holes of the first insulating layer and the corresponding anode metal parts in the through holes of the second insulating layer are bonded to each other to form a conductive bonding body, which can not only effectively ensure the anode current enhancement effect, but also facilitate layout and processing; in addition, the N-type semiconductor layer and the P-type semiconductor layer are insulated by the first wall layer, which can better avoid short circuit leakage in the pixel unit, and can effectively improve the reliability of the optoelectronic device.

[0121] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the protection scope of this application and will not be described one by one here.

[0122] It should be noted that the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the scope of protection of the invention.

Claims

1. An optoelectronic device based on alignment bonding, characterized in that: include, A driving wafer, wherein a second insulating layer is disposed on the driving wafer, the second insulating layer is provided with a through hole, and the through hole is filled with an anode metal piece; A pixel unit, wherein the pixel unit comprises a pixel body and an outer edge wall body, wherein the outer edge wall body is arranged on a side wall of the pixel body, wherein the outer edge wall body comprises a first wall body layer, wherein the first wall body layer is an insulator, and the first wall body layer is in contact with the side wall of the pixel body; The pixel body comprises a P-type semiconductor layer, an active layer and an N-type semiconductor layer which are sequentially arranged in a direction away from the driving wafer; the N-type semiconductor layer and the P-type semiconductor layer in each pixel unit are insulated by the first wall layer; A first insulating layer is further provided between the second insulating layer and the P-type semiconductor layer of the pixel unit, a through hole is also provided on the first insulating layer, an anode metal piece is filled in the through hole, the through hole of the first insulating layer corresponds to the through hole of the second insulating layer one by one, the anode metal piece in the through hole of the first insulating layer and the corresponding anode metal piece in the through hole of the second insulating layer are bonded to each other to form a bonding body, and the P-type semiconductor layer is electrically connected to the driving wafer through the bonding body; Wherein, the N-type semiconductor layers in all the pixel units are connected via a common cathode.

2. The optoelectronic device based on alignment bonding according to claim 1, characterized in that: The anode metal piece of the first insulating layer and / or the second insulating layer comprises a body end, the body end is located in the through hole, an extension end is formed on the body end, and the length of the extension end is greater than the length of the body end.

3. The optoelectronic device based on alignment bonding according to claim 2, characterized in that: The extended end of the anode metal piece in the bonding body is located between the first insulating layer and the second insulating layer.

4. The aligned bonded optoelectronic device according to claim 2, characterized in that: A third insulating layer is disposed between the first insulating layer and the second insulating layer, and the extended end is located in the third insulating layer.

5. The optoelectronic device based on alignment bonding according to claim 2, characterized in that: The length of the extended end is not less than 0.5 times the length of the pixel body.

6. The optoelectronic device based on alignment bonding according to claim 1, characterized in that: The length of the through hole is 0.1 to 0.5 times the length of the pixel body.

7. The optoelectronic device based on alignment bonding according to claim 1, characterized in that: The outer edge wall body also includes a second wall body layer, and the second wall body layer is in contact with the outer wall of the first wall body layer.

8. The optoelectronic device based on alignment bonding according to claim 7, characterized in that: The second wall layer is a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer.

9. The optoelectronic device based on alignment bonding according to claim 7, characterized in that: A step portion is formed on one end of the first wall layer close to the driving wafer, and the second wall layer is located on the step portion.

10. The optoelectronic device based on alignment bonding according to claim 1, characterized in that: Metal grids are also arranged on both sides of each pixel unit, and the metal grids are electrically connected to the common cathode.

11. The optoelectronic device based on alignment bonding according to claim 10, characterized in that: The metal grid is located between the common cathode and the first insulating layer.

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