Circuit structure
By designing the first line on a large-size substrate with one core, the application problem of the existing technology of small and medium-sized substrate design on large-size substrates is solved, and higher wiring space utilization and line-through capabilities are achieved, meeting the design needs of large-size substrates.
Patent Information
- Application Number
- CN202421465616.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-25
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-06-25
AI Technical Summary
The prior art is difficult to effectively apply small-size substrate design on large-size substrates, resulting in problems such as substrate yield, reliability, package warping and heat sinking.
By configuring the first line to have a core, the spacing between lines is reduced at its bottom surface, and space for wiring is increased to achieve more line layout.
It realizes the increase in wiring space on large-sized substrates, reduces the spacing between lines, improves the line crossing ability, and meets the design needs of large-sized substrates.
Smart Images
Figure CN222914805U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly, to a circuit structure. Background Art
[0002] Consider the need to apply the currently common small-size substrate design to large-size substrates. Currently, the embedded trace substrate (ETS) that can be docked with the 80-90 micron chip bump pitch can be applied to a 15mm×15mm, four-layer structure. However, when the substrate exceeds this size and reaches the level of 70mm×70mm, if the small-size substrate design is still applied, problems may occur in terms of its yield / reliability / package warpage / adding heat sinks. For example, the current application of the ARM architecture is about to expand to, for example, laptops, and the size / layers of the substrates used are getting larger and more numerous. However, the original chip bump pitch of the ARM architecture is about 80-90 microns, and the original substrate requirements are only about 15mm×15mm and four layers to use the ETS strip substrate to meet this requirement. When exceeding this size, the yield, reliability, package warpage, adding heat sinks, etc. of the substrate cannot meet the design requirements. Although traditional single substrates can meet the requirements of large size / multiple layers, their bump pitch and circuit layout cannot meet the design requirements.
[0003] On the other hand, as Figure 1 shown in the existing circuit structure 10, at the current stage, when operating with a single substrate at a bump pitch of 80-90 microns, the required line width W0 of the line 14 passing through the middle of the bump pitch P0 is 6 microns. In Figure 1 , the bump pitch P0 is 90 microns, the width W1 of the pad 12 is 70 microns, and the line width / line pitch of the line 14 is 7 microns (S1) / 6 microns (W0) / 7 microns (S1). However, currently, no supplier in the market can meet this requirement during the substrate manufacturing process because the limit of the current photoresist process is 8 microns. Figures 2A to 2E is a cross-sectional schematic view at multiple steps of forming a circuit structure in the dielectric layer 20. First, as Figure 2A , the pad 22 and the line 24 are covered by the dielectric layer 20, where the spacing S2 between the pad 22 and the line 24 is ≥8 microns; see Figure 2B , an opening 32 exposing the pad 22 is formed in the dielectric layer 20 by a laser process, and a seed layer 16 is plated in the opening 32 and on the dielectric layer 20; see Figure 2C , a patterned photoresist layer 34 is formed on the dielectric layer 20; see Figure 2D , a conductive material is filled in the opening 32 and the exposed portion of the photoresist layer 34 to form the pad 12 and the line 14 above the dielectric layer 20; then see Figure 2E, remove the photoresist layer 34, and then form a solder resist layer 40 to expose the pad 12. The current photoresist process has a limit of 8 microns, so the pitch between the circuits of the substrate connected to the chip needs to be smaller to meet the current needs. Utility Model Content
[0004] In view of the above problems, the present application proposes a circuit structure, which can at least increase the space for wiring, achieve more circuits, and reduce the spacing between circuits at the bottom surface of the first circuit.
[0005] The technical solution of this application is implemented as follows:
[0006] According to one aspect of the present application, a circuit structure is provided, which includes: a first dielectric layer; a metal layer, which is arranged in the first dielectric layer, the metal layer includes a first circuit that penetrates the first dielectric layer and a second circuit that is laterally spaced apart from the first circuit, and the first circuit has a core; a seed layer, which is distributed on the edge of the core.
[0007] In some embodiments, in a direction penetrating the first dielectric layer, a height of the second line is smaller than a height of the first line.
[0008] In some embodiments, a height of the second line is smaller than a height of the first dielectric layer.
[0009] In some embodiments, the core is flush with the height of the second line in a direction penetrating the first dielectric layer.
[0010] In some embodiments, a horizontal width of a top surface of the first line is greater than a horizontal width of a bottom surface of the first line, and vertical projections of the first line and the second line partially overlap.
[0011] In some embodiments, a horizontal width of a top surface of the second circuit is equal to a horizontal width of a bottom surface of the second circuit.
[0012] In some embodiments, a top surface of the second line is not exposed by the first dielectric layer.
[0013] In some embodiments, a horizontal width of the second line is smaller than a horizontal width of a bottom surface of the first line.
[0014] In some embodiments, the metal layer further includes a third line spaced apart from the first line and the second line, a top surface of the third line is not exposed by the first dielectric layer, and a horizontal width of the third line is smaller than a horizontal width of the first line.
[0015] In some embodiments, a distance between the third line and the second line is not equal to a distance between the third line and the first line.
[0016] In the above technical solution, by configuring the first circuit to have a core, it is possible to avoid bonding the first circuit to a pad with a relatively large size. As a result, more circuits can be achieved on the bottom surface of the first circuit, reducing the spacing between the core and the second circuit. That is, the spacing between circuits is reduced on the bottom surface of the first circuit, thereby increasing the space available for wiring. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0018] Figure 1 is a cross-sectional schematic diagram of an existing circuit structure.
[0019] Figures 2A to 2E is a cross-sectional schematic diagram at multiple steps of forming the existing circuit structure.
[0020] Figure 3A is a cross-sectional schematic diagram of a circuit structure according to an embodiment of the present application.
[0021] Figure 3B is Figure 3A a top view schematic diagram of the circuit structure shown.
[0022] Figures 4A to 4E is for forming Figure 3A a cross-sectional schematic diagram at multiple steps of the circuit structure in
[0023] Figures 5A to 5E is a cross-sectional schematic diagram of a circuit structure according to other embodiments of the present application.
[0024] Figures 6A - 6C is a cross-sectional schematic diagram of a circuit structure according to some other embodiments of the present application.
[0025] Figure 7 is a cross-sectional schematic diagram of a package structure according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.
[0027] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present utility model. Of course, these are merely examples and are not intended to limit the present utility model. For example, in the following description, forming the first component above or on the second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals and / or letters in various examples. Such repetition is only for the sake of brevity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.
[0028] Figure 3A is a cross-sectional schematic view of a circuit structure 100A according to an embodiment of the present application. Refer to Figure 3A As shown, the circuit structure 100A may include a first dielectric layer 110 and a metal layer 130 disposed within the first dielectric layer 110. The metal layer 130 may include a first line 112 penetrating through the first dielectric layer 110 and a second line 114 arranged laterally spaced from the first line 112 in the horizontal direction.
[0029] In some embodiments, the first line 112 may have a core 1121. The core 1121 protrudes from the bottom surface of the first line 112 towards the inside of the first line 112. In some embodiments, the materials of the first line 112 and the second line 114 may be suitable conductive materials such as copper, for example. According to an embodiment of the present application, a seed layer 150 is distributed at the edge of the core 1121, and the seed layer 150 extends along the sidewall and the top surface of the core 1121. Further, the seed layer 150 may also be distributed on the bottom surface of the first line 112 not occupied by the core 1121 and on the inclined outer wall of the first line 112.
[0030] In the above technical solution, by configuring the first line 112 to have a core 1121, it is thus possible not to bond the first line 112 to a pad with a larger size, thereby enabling more lines to be achieved at the bottom surface of the first line 112, reducing the spacing between the core 1121 and the second line 114, that is, reducing the spacing between lines at the bottom surface of the first line 112, thereby increasing the space available for wiring.
[0031] Figure 3B is Figure 3A a top view schematic of the circuit structure 100A shown. In combination with Figure 3A and Figure 3BAs shown, the first line 112 may further include a body portion 1122 in addition to the core 1121. In some embodiments, the body portion 1122 of the first line 112 may be a via hole penetrating the first dielectric layer 110, and the body portion 1122 may have a circular or elliptical shape in a top view. The body portion 1122 has an inclined outer wall. The seed layer 150 may be distributed on the bottom surface of the body portion 1122 of the first line 112 and on the inclined outer wall of the body portion 1122. In some embodiments, the core 1121 may be a trace extending in a horizontal plane. In some embodiments, the second line 114 may be a trace extending in a horizontal plane. In other embodiments, the first line 112, the core 1121, and the second line 114 may also be other applicable types of conductive structures.
[0032] Continuing to refer to Figure 3A As shown, in the direction of penetrating the first dielectric layer 110, that is, in the Figure 3A vertical direction in, the first line 112, the second line 114, and the first dielectric layer 110 each have their respective heights. In some embodiments, the height of the second line 114 may be less than the height of the first line 112. Among them, the bottom surface of the second line 114 may be coplanar with the bottom surface of the first line 112, and the top surface of the second line 114 is lower than the top surface 112t of the first line 112. In some embodiments, the height of the second line 114 is less than the height of the first dielectric layer 110. The bottom surface of the second line 114 may be coplanar with the bottom surface of the first dielectric layer 110. The top surface of the second line 114 is not exposed by the first dielectric layer 110. In some embodiments, the height of the core 1121 and the second line 114 may be flush, that is, the top surface of the core 1121 and the top surface of the second line 114 may be flush. In some embodiments, the top surface 112t of the first line 112 may be lower than the top surface 110t of the first dielectric layer 110.
[0033] In some embodiments, the horizontal width of the top surface of the first line 112 is greater than the horizontal width of the bottom surface of the first line 112. That is, the width of the first line 112 may be tapered from top to bottom. The horizontal width of the top surface of the core 1121 may be equal to the horizontal width of the bottom surface of the core 1121. That is, the width of the core 1121 may be the same from top to bottom. The side wall of the core 1121 may be covered by the body portion 1122. In some embodiments, the horizontal width of the top surface of the second line 114 may be equal to the horizontal width of the bottom surface of the second line 114. The horizontal width of the second line 114 may be the same as the horizontal width of the core 1121. In some embodiments, the horizontal width of the second line 114 is less than the horizontal width of the bottom surface of the first line 112.
[0034] Figures 4A to 4E is formed Figure 3ACross-sectional schematic views at multiple steps of the circuit structure 100A in. First, refer to Figure 4A , the core 1121 of the first circuit 112 and the second circuit 114 are covered by the first dielectric layer 110. Here, compared to Figure 2A the spacing S2 in, the spacing between the core 1121 and the second circuit 114 can be larger, so it can be not limited by the existing process limits.
[0035] Refer to Figure 4B , an opening 192 exposing the core 1121 is formed in the first dielectric layer 110 by a laser process. The opening 192 passes through the first dielectric layer 110 and can have inclined sidewalls. Refer to Figure 4C , a seed layer 150 is plated in the opening 192 and on the first dielectric layer 110. Refer to Figure 4D , a patterned photoresist layer 194 is formed on the first dielectric layer 110. Refer to Figure 4E , a conductive material is filled in the opening 192 and the exposed portion of the photoresist layer 194 to form the main body portion 1122 of the first circuit 112. Then the photoresist layer 34 is removed to obtain the circuit structure 100A.
[0036] Figures 5A to 5E is a cross-sectional schematic view of a circuit structure according to other embodiments of the present application. Figures 5A to 5E Many aspects of the illustrated embodiment can be similar to those referred to above Figure 3A and Figure 3B described, only the differences of the illustrated embodiment will be described below Figures 5A to 5E hereinafter.
[0037] Refer to Figure 5A the illustrated embodiment, the first circuit 112 can have an electroless nickel immersion gold (ENIG) layer as an end layer, and the electroless nickel immersion gold layer specifically includes a nickel layer 1123 covering the main body portion 1122 and a gold layer 1124 covering the nickel layer 1123. Refer to Figure 5B the illustrated embodiment, a bonding layer 170 can also be provided above the gold layer 1124 of the first circuit 112. The lower part of the bonding layer 170 is located below the top surface 110t of the first dielectric layer 110, and the upper part of the bonding layer 170 is located above the top surface 110t of the first dielectric layer 110. The width of the top surface of the bonding layer 170 can be greater than the width of the top surface of the first circuit 112. In some embodiments, the material of the bonding layer 170 can be, for example, solder.
[0038] Refer to Figure 5C the illustrated embodiment, the first circuit 112 can protrude from the first dielectric layer 110. In this embodiment, the gold layer 1124 protrudes from the top surface 110t of the first dielectric layer 110. Refer to Figure 5DIn the illustrated embodiment, the top surface of the main body portion 1122 of the first line 112 protrudes above the top surface 110t of the first dielectric layer 110. Refer to Figure 5E In the illustrated embodiment, a bonding layer 170 in contact with the main body portion 1122 may be disposed above the main body portion 1122 of the first line 112.
[0039] Figure 6A FIG. is a cross-sectional schematic view of a line structure 100B according to another embodiment of the present application. In Figure 6A In the illustrated embodiment, the main body portion 1122 of the first line 112 may partially overlap with the vertical projection of the second line 114. That is, a part of the second line 114 may be located below the top surface 112t of the first line 112. By configuring the first line 112 to have a core 1121, the horizontal width of the bottom surface of the first line 112 may be smaller than the horizontal width of the top surface of the first line 112. Thus, the second line 114 can be closer to the first line 112 to partially overlap with the vertical projection of the first line 112, that is, the distance between the first line 112 and the second line 114 is further reduced.
[0040] Figure 6B FIG. is a cross-sectional schematic view of a line structure 110C according to another embodiment of the present application. In Figure 6B In the illustrated embodiment, the metal layer 130 may further include another first line 112. The second line 114 is located between the two first lines 112. In some embodiments, at the bottom surface of the first line 112, the pitch P11 between the two first lines 112 is 90 microns, and the horizontal width W21 of the bottom surface of the first line 112 is 65 microns. As described above, by configuring the first line 112 to have a core 1121, the distance between the core 1121 and the second line 114 can be reduced, thereby reducing the distance S11 between the first line 112 and the second line 114. In some embodiments, at the bottom surface of the first line 112, the distance S11 between the second line 114 and the adjacent two first lines 112 may be 5 microns each. Correspondingly, the width W11 of the second line 114 is, for example, 15 microns. It can be seen that the line width can be increased to 15 microns to pass the line, which relaxes the requirement limit for the line width passing the line compared with the 6-micron requirement in the prior art, and greatly improves the line passing ability. Specifically, in this embodiment, the line width / line pitch of the second line 114 is 5 microns (S11) / 15 microns (W11) / 5 microns (S11). As described above, the line passing ability between the two first lines 112 is increased. In such an embodiment, the pitch P11 (P11 = W21 + S11 + W11 + S11) is configured as 65 microns (W21) / 5 microns (S11) / 15 microns (W11) / 5 microns (S11).
[0041] Figure 6C is a cross-sectional schematic view of a circuit structure 100D according to another embodiment of the present application. In Figure 6C the illustrated embodiment, the metal layer 130 may further include a third circuit 116 arranged at intervals with the first circuit 112 and the second circuit 114. In some embodiments, the third circuit 116 may be similar to that described above for the second circuit 114. The top surface of the third circuit 116 is not exposed by the first dielectric layer 110, and the horizontal width of the third circuit 116 may be smaller than the horizontal width of the first circuit 112.
[0042] In some embodiments, the distance between the third circuit 116 and the second circuit 114 may not be equal to the distance between the third circuit 116 and the first circuit 112. In this embodiment, the third circuit 116 is located between the first circuit 112 and the second circuit 114. In other embodiments, the second circuit 114 may be located between the first circuit 112 and the third circuit 116, that is, the positions of the second circuit 114 and the third circuit 116 may be interchanged.
[0043] In Figure 6C the illustrated embodiment, the metal layer 130 may further include another first circuit 112, and the second circuit 114 and the third circuit 116 are located between the two first circuits 112. In some embodiments, at the bottom surface of the first circuit 112, the pitch P11 between the two first circuits 112 may be about 90 micrometers, and the horizontal width W21 at the bottom surface of the first circuit 112 is 65 micrometers. Since the spacing S21 between the core 1121 and the second circuit 114 is reduced, two vias, that is, the second circuit 114 and the third circuit 116, can be arranged between the two first circuits 112. In this embodiment, the spacing S21 between the second circuit 114 and the third circuit 116 and the adjacent corresponding first circuit 112 can be reduced, for example, reduced to about 1.5 micrometers, thereby allowing the second circuit 114 and the third circuit 116 to be arranged between the two first circuits 112. This increases the via capacity between the two first circuits 112.
[0044] In this embodiment, the widths W11 and W31 of the second line 114 and the third line 116 can be 7 microns respectively, and the spacings S21 and S22 between the first line 112, the second line 114 and the third line 116 can be reduced to S21 = 1.5 microns and S22 = 8 microns respectively. The line width / line pitch of the second line 114 and the third line 116 is 1.5 microns (S21) / 7 microns (W31) / 8 microns (S22) / 7 microns (W11) / 1.5 microns (S21). In such an embodiment, the pitch P11 (P11 = W21 + S21 + W31 + S22 + W11 + S21) is configured as 65 microns (W21) / 1.5 microns (S21) / 7 microns (W31) / 8 microns (S22) / 7 microns (W11) / 1.5 microns (S21). In the embodiment where two through-lines (the second line 114 and the third line 116) are placed between the two first lines 112, the spacings S21 and S22 are reduced to 1.5 microns and 8 microns respectively. In some embodiments, the pitch P11 between the two first lines 112 can also be 80 microns or 85 microns, as shown in Table 1 below.
[0045] The following Table 1 shows examples of several different configurations of the current line structure 10 (as Figure 1 shown), the line structure 100C of the present application ( Figure 6B ), and the line structure 100D ( Figure 6C ).
[0046] Table 1
[0047]
[0048] Compared with the line structure 10 in the prior art, the line structure of the present application reduces the spacing between lines and improves the through-line ability between the two first lines 112. When two through-lines are placed between the first lines 112, the spacing can be reduced to 1.5 microns and 8 microns. If only one through-line is placed between the first lines 112, the spacing can also be reduced to 2 microns - 5 microns due to the precision of the laser.
[0049] The embodiment of the present application also provides a packaging structure, which can include any of the line structures described above. Hereinafter, the packaging structure 1000 including the line structure 100C as Figure 7 shown will be taken as an example for illustration. Refer to Figure 7, the encapsulation structure 1000 may include a circuit structure 100C and a chip 200 disposed on a first dielectric layer 110. In some embodiments, the chip 200 is disposed on a substrate 300, and the circuit structure 100C may be the outermost layer of the substrate 300. In some embodiments, the first dielectric layer 110 may be a solder mask layer or an ABF (Ajinomoto Build-up Film) layer. The substrate 300 may further include other dielectric layers and metal layers located below the circuit structure 100C, such as a second dielectric layer 310 located below the first dielectric layer 110 and a metal layer 330 disposed within the second dielectric layer 310.
[0050] Electrical connectors 202 are disposed on the active surface 200F of the chip 200. The electrical connectors 202 may also be referred to as chip bumps. It should be understood that Figure 7 only a part of the chip 200 is shown, and the chip 200 may have a greater number of electrical connectors 202. Two adjacent electrical connectors 202 are respectively bonded to two adjacent first circuits 112. In some embodiments, the pitch between two adjacent electrical connectors 202 is in the range of 80 micrometers to 90 micrometers.
[0051] By configuring the outermost layer of the substrate 300 as the circuit structure provided by the present application (such as 100C), the substrate 300 can be docked with the chip 200 having an electrical connector 202 pitch of 80 micrometers to 90 micrometers. Since the wiring capacity between the first circuits 112 is improved, the pitch and the circuit layout can meet the design requirements.
[0052] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.
Claims
1. A circuit structure, characterized in that: include: a first dielectric layer; A metal layer disposed in the first dielectric layer, the metal layer comprising a first circuit penetrating the first dielectric layer and a second circuit laterally spaced from the first circuit, the first circuit having a core; A seed layer is distributed on the edge of the core.
2. The circuit structure according to claim 1, characterized in that: In a direction penetrating the first dielectric layer, a height of the second circuit is smaller than a height of the first circuit.
3. The circuit structure according to claim 2, characterized in that: The height of the second circuit is smaller than the height of the first dielectric layer.
4. The circuit structure according to claim 1, characterized in that: The core is flush with the height of the second line in a direction penetrating the first dielectric layer.
5. The circuit structure according to claim 1, characterized in that: A horizontal width of a top surface of the first circuit is greater than a horizontal width of a bottom surface of the first circuit, and vertical projections of the first circuit and the second circuit partially overlap.
6. The circuit structure according to claim 5, characterized in that: The horizontal width of the top surface of the second circuit is equal to the horizontal width of the bottom surface of the second circuit.
7. The circuit structure according to claim 1, characterized in that: A top surface of the second line is not exposed by the first dielectric layer.
8. The circuit structure according to claim 1, characterized in that: The horizontal width of the second circuit is smaller than the horizontal width of the bottom surface of the first circuit.
9. The circuit structure according to claim 1, characterized in that: The metal layer further includes a third line spaced apart from the first line and the second line, a top surface of the third line is not exposed by the first dielectric layer, and a horizontal width of the third line is smaller than a horizontal width of the first line.
10. The circuit structure according to claim 9, characterized in that: The distance between the third line and the second line is not equal to the distance between the third line and the first line.