Multi-chip power unit, semiconductor power device and power electronic equipment

Abstract

The utility model provides a multi-chip power unit, a semiconductor power device and power electronic equipment, and relates to the technical field of semiconductors. Wherein the first power chip unit and the second power chip unit are respectively arranged on the first circuit board; the plurality of power terminals comprise a first power terminal, and the first power chip unit and the second power chip unit are respectively provided with a first power connecting part used for being conductively connected with the first power terminal; the projection of the first power terminal on a first set surface parallel to the first circuit board is a first projection; the projections of the two first power connection parts on the first set surface are second projections, and the two second projections are distributed at intervals in the first set direction; the two second projections are both located in a set rectangular area, the two edges of the set rectangular area in the width direction correspond to the two second projections respectively, and a preset included angle is formed between the extension direction of the set rectangular area and the first set direction; the first projection at least partially coincides with the set rectangular area.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and in particular, to a multi-chip power unit, a semiconductor power device, and a power electronic device. Background Art

[0002] In some semiconductor power modules, such as half-bridge power modules, there are multiple chips. These chips are connected through an internal conductive structure and then connected to an external circuit through conductive terminals, such as power terminals and signal terminals. The power terminals are used to transmit large currents, and power conversion is achieved through the semiconductor power module. The signal terminals are used to transmit control signals, detection signals, etc.

[0003] However, during the power conversion process, losses will inevitably occur, and these losses are released in the form of heat, which may cause local heat concentration in the multi-chip power unit and affect its performance. For example, the path lengths of the conductive paths corresponding to some chips vary greatly, and the heat is uneven, which may affect the performance of the multi-chip power unit. Summary of the Utility Model

[0004] The present disclosure aims to solve, to a certain extent, the problem in the related art of how to improve the heat dissipation performance of a multi-chip power unit and enhance its stability and reliability.

[0005] To solve at least one aspect of the above problems to at least a certain extent, in a first aspect, the present disclosure provides a multi-chip power unit, which includes a first circuit board, a first power chip unit, a second power chip unit, and a plurality of power terminals for connecting to an external circuit;

[0006] The first power chip unit and the second power chip unit are respectively disposed on the first circuit board;

[0007] Among the plurality of power terminals, there is a first power terminal, and the first power chip unit and the second power chip unit are respectively provided with first power connection portions for electrically connecting to the first power terminal;

[0008] The projection of the first power terminal on a first set plane parallel to the first circuit board is a first projection; the projections of the two first power connection portions on the first set plane are respectively second projections, and the two second projections are spaced apart along a first set direction;

[0009] Both of the two second projections are located within a set rectangular area. The two edges along the width direction of the set rectangular area respectively correspond to the two second projections, and the extending direction of the set rectangular area is set at a preset angle with the first set direction; at least a part of the first projection coincides with the set rectangular area.

[0010] Optionally, the perpendicular bisector of the line connecting the two second projections passes through the first projection.

[0011] Optionally, the ratio of the shortest path lengths of the conductive paths corresponding to different first power connection portions is greater than or equal to 0.85 and less than or equal to 1.15; wherein, the conductive path corresponding to the first power connection portion is formed between the first power connection portion and the first power terminal.

[0012] Optionally, the first power chip unit and the second power chip unit also respectively have second power connection portions, and each second power connection portion is electrically connected to a power terminal other than the first power terminal.

[0013] Optionally, the first power chip unit includes a first controllable switch tube, and the second power chip unit includes a second controllable switch tube;

[0014] Wherein, the first power connection portion of the first power chip unit is arranged corresponding to the collector of the first controllable switch tube, the second power connection portion of the first power chip unit is arranged corresponding to the emitter of the first controllable switch tube, and the first power connection portion of the second power chip unit is arranged corresponding to the collector of the second controllable switch tube, and the second power connection portion of the second power chip unit is arranged corresponding to the emitter of the second controllable switch tube;

[0015] Or, the first power connection portion of the first power chip unit is arranged corresponding to the emitter of the first controllable switch tube, the second power connection portion of the first power chip unit is arranged corresponding to the collector of the first controllable switch tube, and the first power connection portion of the second power chip unit is arranged corresponding to the emitter of the second controllable switch tube, and the second power connection portion of the second power chip unit is arranged corresponding to the collector of the second controllable switch tube;

[0016] Or, the first power connection portion of the first power chip unit is arranged corresponding to the emitter of the first controllable switch tube, the second power connection portion of the first power chip unit is arranged corresponding to the collector of the first controllable switch tube, and the first power connection portion of the second power chip unit is arranged corresponding to the collector of the second controllable switch tube, and the second power connection portion of the second power chip unit is arranged corresponding to the emitter of the second controllable switch tube;

[0017] Alternatively, the first power connection portion of the first power chip unit is disposed corresponding to the collector of the first controllable switch tube, and the second power connection portion of the first power chip unit is disposed corresponding to the emitter of the first controllable switch tube; and the first power connection portion of the second power chip unit is disposed corresponding to the emitter of the second controllable switch tube, and the second power connection portion of the second power chip unit is disposed corresponding to the collector of the second controllable switch tube.

[0018] Optionally, when the first power connection portion of the first power chip unit is disposed corresponding to the collector of the first controllable switch tube, and the first power connection portion of the second power chip unit is disposed corresponding to the collector of the second controllable switch tube; the two second power connection portions are respectively conductively connected to two of the power terminals other than the first power terminal, and the two power terminals other than the first power terminal are insulated from each other, or, the two second power connection portions are both conductively connected to at least one of the power terminals other than the first power terminal;

[0019] When the first power connection portion of the first power chip unit is disposed corresponding to the emitter of the first controllable switch tube, and the first power connection portion of the second power chip unit is disposed corresponding to the emitter of the second controllable switch tube; the two second power connection portions are respectively conductively connected to two of the power terminals other than the first power terminal, and the two power terminals other than the first power terminal are insulated from each other, or, the two second power connection portions are both conductively connected to at least one of the power terminals other than the first power terminal;

[0020] When the first power connection portion of the first power chip unit is disposed corresponding to the emitter of the first controllable switch tube and the first power connection portion of the second power chip unit is disposed corresponding to the collector of the second controllable switch tube, or, the first power connection portion of the first power chip unit is disposed corresponding to the collector of the first controllable switch tube, and the first power connection portion of the second power chip unit is disposed corresponding to the emitter of the second controllable switch tube; the two second power connection portions are respectively conductively connected to two of the power terminals other than the first power terminal, and the two power terminals other than the first power terminal are insulated from each other.

[0021] Optionally, at least one of the first power chip unit and the second power chip unit further includes a diode;

[0022] The cathode of the diode of the first power chip unit is electrically connected to the collector of the first controllable switch tube, and the anode is electrically connected to the emitter of the first controllable switch tube;

[0023] The cathode of the diode of the second power chip unit is electrically connected to the collector of the second controllable switch transistor, and the anode is electrically connected to the emitter of the second controllable switch transistor.

[0024] Optionally, the first power connection portion or the second power connection portion of the first power chip unit corresponding to the collector of the first controllable switch transistor, and the power terminal corresponding to the collector of the second controllable switch transistor are all connected to the same conductive region of the first metal layer of the first circuit board;

[0025] The first power connection portion or the second power connection portion of the second power chip unit corresponding to the collector of the second controllable switch transistor, and the power terminal corresponding to the collector of the first controllable switch transistor are all connected to the same conductive region of the first metal layer of the first circuit board.

[0026] Optionally, in the first set direction, a plurality of the power terminals are sequentially distributed, and at least one side of the first power terminal is provided with the power terminal.

[0027] Optionally, the multi-chip power unit further includes a signal terminal. A plurality of the power terminals are sequentially distributed in the first set direction, and the signal terminal is distributed at one end or both ends of all the power terminals in the first set direction.

[0028] Optionally, both the power terminal and the signal terminal include plug-in pins, and the plug-in pins are parallel to each other; the plug-in pins are parallel to the first circuit board, and the extending direction of the plug-in pins is perpendicular to the first set direction.

[0029] In a second aspect, the present disclosure provides a semiconductor power device, including a packaging unit and the multi-chip power unit as described in the first aspect above, and the packaging unit packages the multi-chip power unit.

[0030] Optionally, the packaging unit includes a packaging housing, the packaging housing forms a packaging cavity, and the packaging cavity is at least used to accommodate the first power chip unit and the second power chip unit of the multi-chip power unit; a boss structure is further provided on the packaging housing, and the fixed ends of the plug-in pins of the multi-chip power unit are embedded in the boss structure;

[0031] In the thickness direction of the first circuit board of the multi-chip power unit, the projection of the plug-in pin on the second set surface, the projection of the first power chip unit on the second set surface, and the projection of the first circuit board on the second set surface are sequentially distributed, wherein the second set surface is perpendicular to the first circuit board.

[0032] Optionally, the semiconductor power device further includes at least one of a first heat sink and a second heat sink;

[0033] At least one conductive area of ​​the first metal layer on the first circuit board of the multi-chip power unit is correspondingly welded with the first heat sink, and the first heat sink is a conductive plate;

[0034] A second metal layer is provided on a side of the first circuit board of the multi-chip power unit that is away from the first metal layer in a thickness direction thereof, and the second metal layer is connected to the second heat sink.

[0035] In a third aspect, the present disclosure provides a power electronic device, comprising a multi-chip power unit as described in any one of the first aspect above, and / or comprising a semiconductor power device as described in any one of the second aspect above.

[0036] Compared with the related prior art, in the multi-chip power unit, semiconductor power device and power electronic device of the present disclosure, among the multiple power terminals of the multi-chip power unit, there is a first power terminal. The first power chip unit and the second power chip unit are respectively provided with first power connection parts for electrically connecting with the first power terminal. Specifically, the first power terminal is electrically connected to the two first power connection parts through a conductive medium. That is to say, the first power connection part of the first power chip unit and the first power connection part of the second power chip unit share the first power terminal, which can avoid separately equipping each of the two first power connection parts with a separate power terminal and can reduce the number of equipped power terminals. At the same time, define the projection of the first power terminal on a first set plane parallel to the first circuit board as a first projection, and define the projections of the two first power connection parts electrically connected to the first power terminal on the first set plane as second projections respectively. The two second projections are spaced apart along a first set direction, for example, distributed in sequence along the left-right direction. Further, a set rectangular area is virtually defined by the two second projections, and the first projection is set to at least partially coincide with the set rectangular area. Specifically, both of the two second projections are located within the set rectangular area. The two edges along the width direction of the set rectangular area are respectively corresponding to the two second projections. The extending direction of the set rectangular area is set at a preset angle with the first set direction, for example, set at a right angle. That is to say, the edges of the set rectangular area in its width direction are determined by the positions of the two second projections in the left-right direction. By setting the preset angle, for example, setting the preset angle to a 90° angle, the deviation of the width direction of the set rectangular area from the first set direction, that is, the left-right direction, can be avoided. Thus, compared with setting the first projection outside the set rectangular area (for example, setting the first projection to be located on the extension line of the connection line of the two second projections), on the one hand, the difference in the distances between the first projection and each second projection is relatively small, and the difference in the shortest path lengths of the conductive paths between the first power terminal and each first power connection part it needs to connect is relatively small, reducing the current density difference caused by the excessive difference in the shortest path lengths of the conductive paths, and can reduce, for example, the excessive heating caused by large resistance in the local area at the first power terminal. This design method helps to maintain the temperature consistency of the areas near the first power terminal and reduce the temperature difference of each power chip unit connected to the first power terminal, prevent the formation of local hot spots, and improve the overall thermal stability of the multi-chip power unit. On the other hand, such a setting is beneficial to reducing the total length of the conductive paths from the first power terminal to each first power connection part, thereby being beneficial to reducing the resistance and reducing the loss of thermal energy. Generally speaking, the multi-chip power unit of the present disclosure can improve the heat dissipation performance of the multi-chip power unit and enhance its stability and reliability. Description of the Drawings

[0037] Figure 1Schematic diagram of the structure of the multi-chip power unit in the first embodiment of the present disclosure;

[0038] Figure 2 Equivalent circuit schematic diagram of the multi-chip power unit in the first embodiment of the present disclosure;

[0039] Figure 3 Schematic diagram of the structure of the multi-chip power unit in the second embodiment of the present disclosure;

[0040] Figure 4 Equivalent circuit schematic diagram of the multi-chip power unit in the second embodiment of the present disclosure;

[0041] Figure 5 Schematic diagram of the structure of the multi-chip power unit in the third embodiment of the present disclosure;

[0042] Figure 6 Equivalent circuit schematic diagram of the multi-chip power unit in the third embodiment of the present disclosure;

[0043] Figure 7 Schematic diagram of the structure of the multi-chip power unit in the fourth embodiment of the present disclosure;

[0044] Figure 8 Equivalent circuit schematic diagram of the multi-chip power unit in the fourth embodiment of the present disclosure;

[0045] Figure 9 Schematic diagram of the structure of the multi-chip power unit in the fifth embodiment of the present disclosure;

[0046] Figure 10 Equivalent circuit schematic diagram of the multi-chip power unit in the fifth embodiment of the present disclosure;

[0047] Figure 11 Schematic diagram of the structure of the multi-chip power unit in the sixth embodiment of the present disclosure;

[0048] Figure 12 Equivalent circuit schematic diagram of the multi-chip power unit in the sixth embodiment of the present disclosure;

[0049] Figure 13 Schematic diagram of the structure of the multi-chip power unit in the seventh embodiment of the present disclosure;

[0050] Figure 14 Equivalent circuit schematic diagram of the multi-chip power unit in the seventh embodiment of the present disclosure;

[0051] Figure 15 Schematic three-dimensional structure diagram of the semiconductor power device in the embodiment of the present disclosure;

[0052] Figure 16 Top view schematic diagram of the semiconductor power device in the embodiment of the present disclosure;

[0053] Figure 17 is Figure 16 a schematic cross-sectional view at the A-A cross-section in it;

[0054] Figure 18 is an exploded view of a semiconductor power device in an embodiment of the present disclosure;

[0055] Figure 19 is a schematic structural view of a semiconductor power device in another embodiment of the present disclosure;

[0056] Figure 20 is a schematic structural view of a semiconductor power device in yet another embodiment of the present disclosure.

[0057] Explanation of reference numerals:

[0058] S1 - Set rectangular area; 1 - First circuit board; 11 - First insulating layer; 12 - First metal layer; 121 - First conductive area; 122 - Second conductive area; 123 - Third conductive area; 124 - Fourth conductive area; 125 - Fifth conductive area; 13 - Second metal layer; 21 - First power chip unit; Q1 - First controllable switch tube; D1 - First diode; 22 - Second power chip unit; Q2 - Second controllable switch tube; D2 - Second diode; 201 - First power connection part; 202 - Second power connection part; 31 - Power terminal; C1 - First power terminal; C2 - Second power terminal; C3 - Third power terminal; 32 - Signal terminal; G1 - First signal terminal; E1 - Second signal terminal; N1 - Third signal terminal; N2 - Fourth signal terminal; NTC - Thermistor; G2 - Fifth signal terminal; E2 - Sixth signal terminal; 4 - Welding connection layer; 5 - Encapsulation unit; 51 - Encapsulation housing; 52 - Boss structure; 61 - Plug-in pin; 62 - Interconnection structure; 71 - First heat sink; 72 - Second heat sink. Detailed implementation manners

[0059] To make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following will describe the specific embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0060] In the description of the present disclosure, it should be noted that, unless otherwise clearly defined and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

[0061] In the description of this specification, the descriptions referring to terms such as "embodiment", "one embodiment", "some embodiments", "exemplarily", and "one embodiment" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or embodiments are included in at least one embodiment or embodiment of the present disclosure. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or embodiment. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or embodiments in a suitable manner.

[0062] The terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second" may explicitly or implicitly include at least one of such features.

[0063] In the drawings, the Z-axis represents the vertical direction, that is, the up and down position, and the positive direction of the Z-axis (that is, the direction of the arrow of the Z-axis) represents up, and the negative direction of the Z-axis represents down; the X-axis in the drawings represents the front and back position, and the positive direction of the X-axis (that is, the direction of the arrow of the X-axis) represents the front side, and the negative direction of the X-axis represents the back side; the Y-axis in the drawings represents the horizontal direction and is specified as the left and right position, and the positive direction of the Y-axis (that is, the direction of the arrow of the Y-axis) represents the right side, and the negative direction of the Y-axis represents the left side; at the same time, it should be noted that the above-mentioned meanings represented by the Z-axis, Y-axis, and X-axis are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present disclosure.

[0064] As Figure 1 and Figure 2 shown, in a first aspect, an embodiment of the present disclosure provides a multi-chip power unit, and the multi-chip power unit includes a first circuit board 1, a first power chip unit 21, a second power chip unit 22, and a plurality of power terminals 31 for connecting to an external circuit;

[0065] The first power chip unit 21 and the second power chip unit 22 are respectively arranged on the first circuit board 1;

[0066] Among the plurality of power terminals 31, there is a first power terminal C1, and the first power chip unit 21 and the second power chip unit 22 are respectively provided with first power connection portions 201 for electrically connecting to the first power terminal C1;

[0067] The projection of the first power terminal C1 on a first set plane parallel to the first circuit board 1 is a first projection; the projections of the two first power connection portions 201 on the first set plane are respectively second projections, and the two second projections are spaced apart along a first set direction;

[0068] Both of the two second projections are located within the set rectangular area S1, and the two second projections are respectively arranged corresponding to two edges of the set rectangular area S1 along the first set direction; the set rectangular area S1 extends along the second set direction and at least partially overlaps with the first projection, and the second set direction is set at a preset angle with the first set direction.

[0069] It should be understood that the multi-chip power unit includes a plurality of conductive terminals. Generally, the plurality of conductive terminals include power terminals 31 and signal terminals 32. The conductive terminals serve as interfaces for connecting the multi-chip power unit to an external circuit outside the multi-chip power unit. The specific connection manner of the conductive terminals to the external circuit is not limited. For example, the multi-chip power unit can be plugged and connected to a second circuit board outside the multi-chip power unit through the conductive terminals. On the basis of meeting the external connection requirements, the positions and structures of the plurality of conductive terminals are not limited, and relevant technologies can be adopted, or the technologies described later in this specification can also be adopted.

[0070] The composition of the first power chip unit 21 and the second power chip unit 22 and their specific setting manners on the first circuit board 1 are not limited, and exemplary descriptions will be given later.

[0071] The first set surface is arranged parallel to the first circuit board 1. For example, the first set surface is parallel to the XY plane. The first circuit board 1 may include a first insulating layer 11 and a first metal layer 12 disposed on one side (such as the upper side) of the first insulating layer 11. The first metal layer 12 can be set as a plurality of conductive regions (or, a plurality of conductive patterns) according to needs. The first circuit board 1 is connected to the corresponding structure through the conductive regions, such as welding or pressing connection. The welding connection layer 4 formed by welding can be referred to Figure 18 The conductive regions are arranged according to the corresponding circuit layout requirements in the multi-chip power unit, and exemplary descriptions will be given later in combination with specific embodiments.

[0072] It should be understood that both the first power chip unit 21 and the second power chip unit 22 have power connection parts for connecting to other parts inside the multi-chip power unit. Both the power terminals 31 and the power connection parts are used for transmitting large currents. The power terminals 31 realize the input or output of the power current of the first power chip unit 21 through the corresponding power connection parts. In this embodiment, the first power chip unit 21 and the second power chip unit 22 respectively have two power connection parts. One power connection part of the first power chip unit 21 and one power connection part of the second power chip unit 22 are respectively electrically connected to one power terminal 31 through the corresponding conductive media. This power terminal 31 is the above-mentioned first power terminal C1, and these two power connection parts are the above-mentioned first power connection parts 201.

[0073] Such as Figure 1As shown, exemplarily, the first power chip includes a first controllable switch Q1, and the second power chip includes a second controllable switch Q2. For example, the first controllable switch Q1 is an IGBT, and the collector (i.e., the C pole, Figure 2 as shown in the figures and other drawings, represented by the letter C) is located on the lower surface, which is also the surface connected to the first metal layer 12 of the first circuit board 1. The emitter (i.e., the E pole, Figure 2 as shown in the figures and other drawings, represented by the letter E) of the first controllable switch Q1 is located on the upper surface. For example, the second controllable switch Q2 is an IGBT, and the collector (i.e., the C pole, Figure 2 as shown in the figures and other drawings, represented by the letter C) is located on the lower surface, which is also the surface connected to the first metal layer 12 of the first circuit board 1. The emitter (i.e., the E pole, Figure 2 as shown in the figures and other drawings, represented by the letter E) of the second controllable switch Q2 is located on the upper surface.

[0074] As Figure 1 shown, exemplarily, the collectors of the first controllable switch Q1 and the second controllable switch Q2 are respectively welded to the first conductive region 121 of the first metal layer 12, and the first conductive region 121 is welded to the first power terminal C1. The collector of the first controllable switch Q1 is used to form the first power connection part 201 of the first power chip unit 21, and the collector of the second controllable switch Q2 is used to form the first power connection part 201 of the second power chip unit 22. In this case, the two second projections respectively correspond to the collector (lower surface) of the first controllable switch Q1 and the collector (lower surface) of the second controllable switch Q2. That is, the projection of the lower surface of the first controllable switch Q1 on the first set surface forms one of the second projections, and the projection of the lower surface of the second controllable switch Q2 on the first set surface forms the other second projection. The two second projections are spaced apart in the left-right direction, for example, in the first set direction such as Figure 1 the left-right direction.

[0075] Figure 1 In the figure, the first power chip unit 21 and the second power chip unit 22 are respectively outlined schematically with dashed boxes. The set rectangular area S1 is a virtual area. In Figure 1It is schematically outlined by a double-dot dash frame. The left and right edges or boundaries of the set rectangular area S1 respectively correspond to two second projection settings. For example, the second projection corresponding to the collector (lower surface) of the first controllable switch tube Q1 intersects with the left edge of the set rectangular area S1, and the second projection corresponding to the collector (lower surface) of the second controllable switch tube Q2 intersects with the right edge of the set rectangular area S1. For example, the left edge of the second projection corresponding to the collector (lower surface) of the first controllable switch tube Q1 intersects with the left edge of the set rectangular area S1, and the right edge of the second projection corresponding to the collector (lower surface) of the second controllable switch tube Q2 intersects with the right edge of the set rectangular area S1. In this embodiment, for simplicity of understanding, the two second projections can be equivalent to two points, and the left and right edges or boundaries of the set rectangular area S1 respectively pass through the points equivalently formed by the two second projections.

[0076] The extending direction of the set rectangular area S1 is set at a preset angle with the first set direction. For example, the angle between the extending direction of the set rectangular area S1 and the first set direction is 90°±15°. When the angle between the extending direction of the set rectangular area S1 and the first set direction is 90°, the width direction of the set rectangular area S1 is consistent with the first set direction, that is, the width direction of the set rectangular area S1 is consistent with the left and right direction, and the extending direction (i.e., the length direction) is consistent with the front and back direction.

[0077] When the multi-chip power unit is connected to an external circuit through each power terminal 31 (for example, in the case where the power terminal 31 is plugged and connected to the second circuit board), a large current is transmitted through each power terminal 31, and the large current can be transmitted to at least two power chip units respectively through the first power terminal C1 and the corresponding at least two first power connection parts 201.

[0078] Thus, among the multiple power terminals 31 of the multi-chip power unit, there is a first power terminal C1. The first power chip unit 21 and the second power chip unit 22 are respectively provided with first power connection parts 201 for electrically connecting with the first power terminal C1. Specifically, the first power terminal C1 is electrically connected to the two first power connection parts 201 through a conductive medium respectively. That is to say, the first power connection part 201 of the first power chip unit 21 and the first power connection part 201 of the second power chip unit 22 share the first power terminal C1, which can avoid separately equipping the two first power connection parts 201 with individual power terminals 31 and can reduce the number of equipped power terminals 31. At the same time, define the projection of the first power terminal C1 on a first set plane parallel to the first circuit board 1 as a first projection, and define the projections of the two first power connection parts 201 electrically connected to the first power terminal C1 on the first set plane as second projections respectively. The two second projections are spaced apart along a first set direction, for example, distributed in sequence along the left-right direction. Also, a set rectangular area S1 is virtually defined by the two second projections, and the first projection is set to at least partially coincide with the set rectangular area S1. Specifically, both second projections are located within the set rectangular area S1. The two edges along the width direction of the set rectangular area S1 are respectively corresponding to the two second projections. The extending direction of the set rectangular area S1 forms a preset included angle with the first set direction, for example, a right angle is set. That is to say, the edges of the set rectangular area S1 in its width direction are determined by the positions of the two second projections in the left-right direction, and by setting the preset included angle, for example, the preset included angle is set to 90°, it can be avoided that the width direction of the set rectangular area S1 deviates too much from the first set direction, that is, the left-right direction. Thus, compared with setting the first projection outside the set rectangular area S1 (for example, setting the first projection on the extension line of the connection line of the two second projections), on the one hand, the difference in the distances between the first projection and each second projection is relatively small, and the difference in the shortest path lengths of the conductive paths between the first power terminal C1 and the first power connection parts 201 it needs to connect is relatively small, reducing the current density difference caused by too large a difference in the shortest path lengths of the conductive paths, and can reduce, for example, the overheating caused by large resistance in the local area at the first power terminal C1. This design method helps to maintain the temperature consistency of the areas near the first power terminal C1 and reduce the temperature difference of the power chip units connected to the first power terminal C1, prevent the formation of local hot spots, and improve the overall thermal stability of the multi-chip power unit. On the other hand, this setting is beneficial to reducing the total length of the conductive paths from the first power terminal C1 to each first power connection part 201, thereby being beneficial to reducing the resistance and reducing the loss of thermal energy. Generally speaking, the multi-chip power unit of the present disclosure can improve the heat dissipation performance of the multi-chip power unit and enhance its stability and reliability.

[0079] Optionally, the perpendicular bisector of the line connecting the two second projections passes through the first projection.

[0080] In this embodiment, the second projections corresponding to the first power connection portions 201 of the first power chip unit 21 and the second projections corresponding to the first power connection portions 201 of the second power chip unit 22 can be equivalently regarded as points, and the perpendicular bisector is the perpendicular bisector of the line connecting these two points.

[0081] In this way, since the points on the perpendicular bisector are equidistant from the two second projections, when the first power terminal C1 and the corresponding two first power connection portions 201 are electrically connected through the conductive medium respectively, it is beneficial to further reduce the difference in the shortest path lengths of the conductive paths from the first power terminal C1 to the two first power connection portions 201, and it is convenient for the arrangement of the corresponding conductive medium, reducing the possibility of forming local hot spots. In some cases, the shortest path length of the conductive path from the first power terminal C1 to the first power connection portion 201 of the first power chip unit 21 is equal to the shortest path length of the conductive path from the first power terminal C1 to the second power connection portion 202 of the second power chip unit 22.

[0082] Optionally, the ratio of the shortest path lengths of the conductive paths corresponding to different first power connection portions 201 is greater than or equal to 0.85 and less than or equal to 1.15.

[0083] It should be understood that the conductive path corresponding to a certain determined first power connection portion 201 is formed between the first power connection portion 201 and the first power terminal C1. Specifically, the first power connection portion 201 and the first power terminal C1 are electrically connected through a conductive medium such as Figure 1 electrically connected through the first metal layer 12 in the first conductive region 121, and the conductive path is located in the conductive medium. Of course, the specific composition of the conductive medium is not limited, and it may include one or more of the first metal layer 12 of the first circuit board 1, bonding wires, and conductive metal strips, which are set according to actual needs and will be exemplarily described later.

[0084] It should be understood that there may be multiple conductive paths corresponding to a certain determined first power connection portion 201, and the length of the shortest one among the conductive paths is its corresponding shortest path length.

[0085] Exemplarily, the conduction path formed by the conductive medium between the first power connection portion 201 of the first power chip unit 21 and the first power terminal C1 is the first conduction path, and the conduction path formed by the conductive medium between the first power connection portion 201 of the second power chip unit 22 and the first power terminal C1 is the second conduction path. The ratio of the shortest path length of the first conduction path to the shortest path length of the second conduction path is greater than or equal to 0.85 and less than or equal to 1.15. For example, this ratio is greater than or equal to 0.95 and less than or equal to 1.05. For example, the ratio of the shortest path length of the first conduction path to the shortest path length of the second conduction path is 1. That is, the shortest path length of the first conduction path is equal to the shortest path length of the second conduction path.

[0086] In this way, setting the ratio of the shortest path lengths of the conduction paths corresponding to different first power connection portions 201 to be greater than or equal to 0.85 and less than or equal to 1.15, for example, the shortest path lengths of the conduction paths corresponding to different first power connection portions 201 are equal, can, to a certain extent, avoid excessive resistance differences in each conduction path resulting in excessive power loss on some conduction paths, avoid causing local overheating, help make the heat distribution more uniform, reduce thermal stress and mechanical stress, avoid damage to structures such as the first power terminal C1 due to uneven thermal expansion, and extend the service life of the multi-chip power unit. At the same time, the parasitic inductances on each conduction path tend to be consistent, which helps reduce the loop inductance, reduce the voltage overshoot and ringing phenomena when the power chips are switched, and improve the stability and efficiency of the multi-chip power unit. In addition, in scenarios where multiple chips need to work synchronously, such as in half-bridge or full-bridge topologies, the shortest path lengths of each conduction path tend to be consistent, which helps keep the current propagation time consistent, reduce the uncertainty of the dead time, and improve the control accuracy and response speed of the power chips.

[0087] Optionally, the first power chip unit 21 and the second power chip unit 22 also respectively have second power connection portions 202, and each second power connection portion 202 is respectively conductively connected to a power terminal 31 other than the first power terminal C1.

[0088] That is to say, each first power chip unit 21 is correspondingly provided with a first power connection portion 201 and a second power connection portion 202, and the first power connection portion 201 and the second power connection portion 202 are respectively conductively connected to power terminals 31, and are connected to an external circuit outside the multi-chip power unit through the corresponding power terminals 31.

[0089] In this embodiment, the first power chip unit 21 includes a first controllable switch Q1, and the second power chip unit 22 includes a second controllable switch Q2; the first power connection portion 201 and the second power connection portion 202 of the first power chip unit 21 are respectively arranged corresponding to the collector and the emitter of the first controllable switch Q1, and the first power connection portion 201 and the second power connection portion 202 of the second power chip unit 22 are respectively arranged corresponding to the collector and the emitter of the second controllable switch Q2.

[0090] As Figure 1 and Figure 2 shown, in some scenarios, the first power connection portion 201 of the first power chip unit 21 is arranged corresponding to the collector of the first controllable switch Q1, the second power connection portion 202 of the first power chip unit 21 is arranged corresponding to the emitter of the first controllable switch Q1, and the first power connection portion 201 of the second power chip unit 22 is arranged corresponding to the collector of the second controllable switch Q2, and the second power connection portion 202 of the second power chip unit 22 is arranged corresponding to the emitter of the second controllable switch Q2. Subsequently, the setting of the first power chip unit 21 and the second power chip unit 22 in this case is regarded as Case 1.

[0091] In the above Case 1, taking the first power chip unit 21 as an example, the above corresponding setting method is described. The current between the first power connection portion 201 and the second power connection portion 202 of the first power chip unit 21 will flow through the first controllable switch Q1. On the current flow path, among the first power connection portion 201 and the second power connection portion 202, the first power connection portion 201 is arranged closer to the collector of the first controllable switch Q1, and the second power connection portion 202 is arranged closer to the emitter of the second power connection portion 202. Thus, it can be known that the specific positions of the first power connection portion 201 and the second power connection portion 202 in the first power chip unit 21 are determined according to its circuit layout requirements. In this Case 1, the first power connection portion 201 can be formed at the collector of the first controllable switch Q1, or can also be formed at the cathode position (lower surface position) of the first diode D1 connected in parallel with the first controllable switch Q1.

[0092] As Figures 1 to 4 shown, in a further optional solution 1 of this Case 1, the two second power connection portions 202 are respectively conductively connected to two power terminals 31 other than the first power terminal C1, and the two power terminals 31 other than the first power terminal C1 are insulated from each other.

[0093] Specifically, in this embodiment, the multi-chip power unit has three power terminals 31, namely a first power terminal C1, a second power terminal C2, and a third power terminal C3. The first power terminal C1 is electrically connected to the first power connection portion 201 of the first power chip unit 21 (referring to the collector of the first controllable switch Q1) and the first power connection portion 201 of the second power chip unit 22 (referring to the collector of the second controllable switch Q2). The second power terminal C2 is electrically connected to the second power connection portion 202 of the first power chip unit 21 (referring to the emitter of the first controllable switch Q1), and the third power terminal C3 is electrically connected to the second power connection portion 202 of the second power chip unit 22 (referring to the emitter of the second controllable switch Q2). The second power terminal C2 and the third power terminal C3 are respectively connected to the second conductive region 122 and the third conductive region 123 of the first metal layer 12, for example, by welding. There is a gap between the second conductive region 122 and the third conductive region 123, so as to realize insulation between the second power terminal C2 and the third power terminal C3.

[0094] As Figures 1 to 4 shown in the figure, the multi-chip power unit provides a solution in which the collectors of the first controllable switch Q1 and the second controllable switch Q2 share the first power terminal C1. When the multi-chip power unit is subsequently connected to an external circuit, the second power terminal C2 and the third power terminal C3 can be short-circuited through the external circuit, so as to realize the parallel use of the first power chip unit 21 and the second power chip unit 22. Specifically, reference can be made to Figure 2 . By short-circuiting the second power terminal C2 and the third power terminal C3 with a light-colored dotted line (the light gray dotted line corresponds to the external circuit), the parallel use requirements in some scenarios can be met. When the multi-chip power unit is subsequently connected to an external circuit, the external circuit can also not short-circuit the second power terminal C2 and the third power terminal C3, so as to realize the series use of the first power chip unit 21 and the second power chip unit 22 in such a way that the collectors of the first controllable switch Q1 and the second controllable switch Q2 share the first power terminal C1. The equivalent circuit of their series connection can be referenced to Figure 4 .

[0095] It should be understood that in the short-circuiting scheme and the non-short-circuiting scheme, the number of signal terminals 32 provided and the layout manner can be different, which is not limited. For example Figure 1 and Figure 2 in the corresponding short-circuiting scheme, the first signal terminal G1 is respectively conductively connected to the gates (i.e., G poles, represented by the letter G in the figure) of the first controllable switch Q1 and the second controllable switch Q2, for outputting a control signal to the gates. The second signal terminal E1 is respectively conductively connected to the emitters of the first controllable switch Q1 and the second controllable switch Q2, for transmitting the corresponding detection current. Figure 3And Figure 4 In the corresponding non-shorted scheme, the first signal terminal G1 is conductively connected to the gate of the first controllable switch Q1, the fifth signal terminal G2 is conductively connected to the gate of the second controllable switch Q2, the second signal terminal E1 is conductively connected to the emitter of the first controllable switch Q1, and the sixth signal terminal E2 is conductively connected to the emitter of the second controllable switch Q2. Figure 1 In [it], the first metal layer 12 respectively forms a fifth conductive region 125, a fourth conductive region 124, a first conductive region 121, a second conductive region 122, and a third conductive region 123 corresponding to the first signal terminal G1, the second signal terminal E1, the first power terminal C1, the second power terminal C2, and the third power terminal C3, which will not be elaborated here.

[0096] As Figure 5 And Figure 6 shown (the first power connection portion 201 and the second power connection portion 202 are only shown in Figure 6 ), in the further alternative solution two of case one, both of the two second power connection portions 202 are conductively connected to at least one power terminal 31 other than the first power terminal C1.

[0097] As Figure 5 shown, exemplarily, the two second power connection portions 202 are respectively connected to the second power terminal C2 and the third power terminal C3. For example, the emitter of the first controllable switch Q1 is conductively connected to the second power terminal C2 via a bonding wire ( Figure 5 and in other drawings, each bonding wire is schematically shown by the thickest solid line), the second conductive region 122, etc., and the emitter of the second controllable switch Q2 is conductively connected to the third power terminal C3 via a bonding wire, the third conductive region 123, etc. The two second power connection portions 202 are connected by a bonding wire, or, the second conductive region 122 and the third conductive region 123 are conductively connected by a bonding wire, or, the two second power connection portions 202 are conductively connected, so that the equivalent circuit of the multi-chip power unit can refer to Figure 6 . It should be understood that in this case, only one of the second power terminal C2 and the third power terminal C3 can also be provided. For example, only the second power terminal C2 is provided, and the second power terminal C2 is respectively conductively connected to the two second power connection portions 202.

[0098] In this way, the multi-chip power unit provides an integration scheme in which the first power chip unit 21 and the second power chip unit 22 are connected in parallel and the first power terminal C1 shared by the collectors of the first controllable switch Q1 and the second controllable switch Q2, and can be conveniently put into use.

[0099] As Figures 7 to 10 shown (the first power connection portion 201 and the second power connection portion 202 are only shown inFigure 8 and Figure 10 shown), in some scenarios, the first power connection portion 201 of the first power chip unit 21 is disposed corresponding to the emitter of the first controllable switch Q1, the second power connection portion 202 of the first power chip unit 21 is disposed corresponding to the collector of the first controllable switch Q1, and the first power connection portion 201 of the second power chip unit 22 is disposed corresponding to the emitter of the second controllable switch Q2, and the second power connection portion 202 of the second power chip unit 22 is disposed corresponding to the collector of the second controllable switch Q2. Subsequently, the setting of the first power chip unit 21 and the second power chip unit 22 in this case is taken as Case 2.

[0100] That is, Figures 7 to 9 shown a technical solution in a multi-chip power unit where the emitter of the second controllable switch Q2 and the emitter of the second controllable switch Q2 share the first power terminal C1.

[0101] As Figures 9 to 10 shown (the first power connection portion 201 and the second power connection portion 202 are only shown in Figure 10 shown), in the first alternative of Case 2, the two second power connection portions 202 are respectively conductively connected to two power terminals 31 other than the first power terminal C1, and the two power terminals 31 other than the first power terminal C1 are insulated from each other.

[0102] Similar to the first alternative of the above Case 1, in this case, the first power chip unit 21 and the second power chip unit 22 of the multi-chip power unit can be formed into a parallel scheme or a series scheme through the design of the external circuit. In some scenarios, it can also be switched between the parallel scheme and the series scheme by controlling the external circuit, and its flexibility and adaptability are relatively strong, which will not be elaborated here.

[0103] As Figure 7 and Figure 8 shown, in the second alternative of Case 2, the two second power connection portions 202 (the second power connection portion 202 is only shown in Figure 8 shown) are both conductively connected to at least one power terminal 31 other than the first power terminal C1.

[0104] Specifically, through the setting of the internal conductive medium or the conductive structure in the multi-chip power unit, a scheme in which the first power chip unit 21 and the second power chip unit 22 are in parallel is formed. The equivalent circuit of the multi-chip power unit refers to Figure 8 .

[0105] As Figure 11 and Figure 12 shown (the first power connection portion 201 and the second power connection portion 202 are only shown in Figure 12As shown, in some scenarios, the first power connection portion 201 of the first power chip unit 21 is arranged corresponding to the emitter of the first controllable switch Q1, the second power connection portion 202 of the first power chip unit 21 is arranged corresponding to the collector of the first controllable switch Q1, and the first power connection portion 201 of the second power chip unit 22 is arranged corresponding to the collector of the second controllable switch Q2, and the second power connection portion 202 of the second power chip unit 22 is arranged corresponding to the emitter of the second controllable switch Q2. Subsequently, the arrangement of the first power chip unit 21 and the second power chip unit 22 in this case is regarded as Case 3.

[0106] As Figure 13 and Figure 14 shown (the first power connection portion 201 and the second power connection portion 202 are only shown in Figure 14 As shown, in some scenarios, the first power connection portion 201 of the first power chip unit 21 is arranged corresponding to the collector of the first controllable switch Q1, the second power connection portion 202 of the first power chip unit 21 is arranged corresponding to the emitter of the first controllable switch Q1; and the first power connection portion 201 of the second power chip unit 22 is arranged corresponding to the emitter of the second controllable switch Q2, and the second power connection portion 202 of the second power chip unit 22 is arranged corresponding to the collector of the second controllable switch Q2. Subsequently, the arrangement of the first power chip unit 21 and the second power chip unit 22 in this case is regarded as Case 4.

[0107] Furthermore, in any one of Case 3 and Case 4; the two second power connection portions 202 are respectively conductively connected to two power terminals 31 other than the first power terminal C1, and the two power terminals 31 other than the first power terminal C1 are insulated from each other. When the multi-chip power unit is connected to an external circuit, it can provide a scheme in which the first power chip unit 21 and the second power chip unit 22 are connected in series to meet the corresponding usage requirements.

[0108] As Figures 1 to 14 shown, in the above embodiments, optionally, at least one of the first power chip unit 21 and the second power chip unit 22 further includes a diode;

[0109] The cathode of the diode of the first power chip unit 21 is electrically connected to the collector of the first controllable switch Q1, and the anode is electrically connected to the emitter of the first controllable switch Q1;

[0110] The cathode of the diode of the second power chip unit 22 is electrically connected to the collector of the second controllable switch Q2, and the anode is electrically connected to the emitter of the second controllable switch Q2.

[0111] Specifically, the cathode of the diode is located on the lower surface, and the anode is located on the upper surface, as Figures 1 to 14It shows a case where the first power chip unit 21 includes a diode, which is the first diode D1, and the second power chip unit 22 includes a diode, which is the second diode D2. The corresponding usage requirements can be met. For example Figures 10 to 14 Corresponding to a half-bridge power module, it can be put into use as needed. In some scenarios, the setting of the diode can reduce the possibility of the controllable switch tube in parallel with it being broken down, which will not be elaborated here.

[0112] Optionally, the first power connection part 201 or the second power connection part 202 of the first power chip unit 21 corresponding to the collector of the first controllable switch tube Q1, and the power terminal 31 corresponding to the collector of the first controllable switch tube Q1 are both connected to the same conductive area of the first metal layer 12 of the first circuit board 1;

[0113] The first power connection part 201 or the second power connection part 202 of the second power chip unit 22 corresponding to the collector of the second controllable switch tube Q2, and the power terminal 31 corresponding to the collector of the second controllable switch tube Q2 are both connected to the same conductive area of the first metal layer 12 of the first circuit board 1.

[0114] Subsequently, an example will be given with the first power chip unit 21 including the first diode D1 and the second power chip unit 22 including the second diode D2.

[0115] Specifically, when the first power connection part 201 of the first power chip unit 21 is set corresponding to the collector of the first controllable switch tube Q1, the collector of the first controllable switch tube Q1, the cathode of the first diode D1, and the corresponding power terminal 31 are all connected to the same conductive area. For example, as Figure 1 、 Figure 13 shown, the collector of the first controllable switch tube Q1, the cathode of the first diode D1, and the first power terminal C1 are all connected to the first conductive area 121.

[0116] When the second power connection part 202 of the first power chip unit 21 is set corresponding to the collector of the first controllable switch tube Q1, the collector of the first controllable switch tube Q1, the cathode of the first diode D1, and the corresponding power terminal 31 are all connected to the same conductive area. For example, as Figure 7 、 Figure 9 、 Figure 11 shown, the collector of the first controllable switch tube Q1, the cathode of the first diode D1, and the first power terminal C1 are all connected to the second conductive area 122.

[0117] When the first power connection portion 201 of the second power chip unit 22 is disposed corresponding to the collector of the second controllable switch Q2, the collector of the second controllable switch Q2, the cathode of the second diode D2, and the corresponding power terminal 31 are all connected to the same conductive region. For example, as Figure 1 , Figure 11 shown, the collector of the second controllable switch Q2, the cathode of the second diode D2, and the first power terminal C1 are all connected to the first conductive region 121.

[0118] When the second power connection portion 202 of the second power chip unit 22 is disposed corresponding to the collector of the second controllable switch Q2, the collector of the second controllable switch Q2, the cathode of the second diode D2, and the corresponding power terminal 31 are all connected to the same conductive region. For example, as Figure 9 and Figure 13 shown, the collector of the second controllable switch Q2, the cathode of the second diode D2, and the third power terminal C3 are all connected to the third conductive region 123.

[0119] In this way, part of the conductive region can be used to connect multiple components, with a simple structure and strong practicability. In particular, in the cases shown in Figure 1 and Figure 3 , the same conductive region can be used to connect more components, with a simple structure and facilitating the layout of the position of the first power terminal C1.

[0120] As Figure 1 shown, in the above embodiments, optionally, in the first set direction, a plurality of power terminals 31 are sequentially distributed, and at least one side of the first power terminal C1 is provided with a power terminal 31.

[0121] Exemplarily, the number of power terminals 31 is three, which are the second power terminal C2, the first power terminal C1, and the third power terminal C3 from left to right. The layout of the power terminals 31 is relatively regular, facilitating the layout of the position of the first power terminal C1. For example, in the left - right direction, the first power terminal C1 is disposed corresponding to the middle region of the first circuit board 1.

[0122] As Figure 1 shown, in the above embodiments, optionally, the multi - chip power unit further includes signal terminals 32. A plurality of power terminals 31 are sequentially distributed in the first set direction, and the signal terminals 32 are distributed at one or both ends of all the power terminals 31 in the first set direction.

[0123] It should be understood that among the multiple signal terminals 32, the above - mentioned first signal terminal G1, second signal terminal E1, etc. may be included, and a third signal terminal N1 and a fourth signal terminal N2 may also be included. The third signal terminal N1 and the fourth signal terminal N2 can be electrically connected to both ends of the thermistor NTC.

[0124] In this way, the power terminals 31 are relatively concentrated, and the signal terminals 32 are located at the left or right end of all the power terminals 31, which can reduce the electromagnetic interference between the power terminals 31 and the signal terminals 32 and ensure the reliability of the electrical signal transmission in the signal terminals 32.

[0125] Furthermore, both the power terminals 31 and the signal terminals 32 include plug-in pins 61, and the plug-in pins 61 are parallel to each other.

[0126] Specifically, the plug-in pins 61 are used for plugging and connecting with an external circuit. The plug-in pins 61 are parallel to each other, which can ensure that the multi-chip power unit is electrically connected to the second circuit board, such as the second circuit board, through the plug-in connection of the plug-in pins 61. The structure is simple and practical.

[0127] Furthermore, the plug-in pins 61 are parallel to the first circuit board 1, and the extending direction of the plug-in pins 61 is set at a preset angle with the first set direction, for example, they are perpendicular to each other.

[0128] Specifically, the plug-in pins 61 extend in the front-back direction, which is convenient for arranging the positions of the plug-in pins 61. For example, each of the plug-in pins 61 can be arranged at the edge position of the multi-chip power unit in the front-back direction.

[0129] It should be understood that the fixed ends of the plug-in pins 61 can be directly connected to the first metal layer 12 of the first circuit board 1, such as by welding, so as to realize the conductive connection between the power terminals 31 or the signal terminals 32 and the corresponding chips.

[0130] As Figure 17 and Figure 18 shown, optionally, both the power terminals 31 and the signal terminals 32 include an interconnection structure 62. The fixed ends (i.e., the ends far from the plug-in ends) of the plug-in pins 61 are connected to the first ends of the interconnection structure 62, and the second ends of the interconnection structure 62 are connected to the first circuit board 1. There is a gap between the first ends and the second ends of the interconnection structure 62 in the thickness direction of the first circuit board 1.

[0131] The interconnection structure 62 can be integrally formed with the plug-in pins 61 or connected by welding, etc., which will not be elaborated here in detail. Thus, there is a gap between the plug-in pins 61 and the first circuit board 1 in the thickness direction of the first circuit board 1, and this gap can form the safety distance between the plug-in pins 61 and the first circuit board 1, improving the safety of the multi-chip power unit.

[0132] As Figures 15 to 18 shown, in a second aspect, an embodiment of the present disclosure further provides a semiconductor power device, including a packaging unit 5 and the multi-chip power unit as in the above embodiment, and the packaging unit 5 packages the multi-chip power unit.

[0133] Specifically, the encapsulation unit 5 includes an encapsulation housing 51 which forms an encapsulation cavity for accommodating at least the first power chip unit 21 and the second power chip unit 22 of the multi-chip power unit.

[0134] Exemplarily, the surface of the first insulating layer 11 of the first circuit board 1 facing the first metal layer 12 is flush with the lower surface of the encapsulation housing 51, or the lower surface of the second metal layer 13 of the first circuit board 1 is flush with the lower surface of the encapsulation housing 51.

[0135] As Figure 15 and Figure 17 shown, optionally, a boss structure 52 is further provided on the encapsulation housing 51, and the fixed end of the insertion pin 61 of the multi-chip power unit is embedded in the boss structure 52;

[0136] In the thickness direction of the first circuit board 1, the projection of the insertion pin 61 on the second set plane, the projection of the first power chip unit 21 on the second set plane, and the projection of the first circuit board 1 on the second set plane are sequentially distributed, where the second set plane is perpendicular to the first circuit board 1.

[0137] As Figure 17 shown, the second set plane is parallel to the XZ plane, and the projection of the insertion pin 61 on the second set plane, the projection of the first power chip unit 21 on the second set plane, and the projection of the first circuit board 1 on the second set plane are sequentially distributed from top to bottom. The insertion pin 61 is connected to the circuit board through an interconnection structure 62. The setting of the boss structure 52 enables the insertion pin 61 to obtain a suitable interval from the first circuit board 1 in the thickness direction of the first circuit board 1, meeting the safety distance requirement between the insertion end of the insertion pin 61 and the first circuit board 1, and avoiding the over-large volume of the semiconductor power device. Its structure is simple and practical.

[0138] As Figure 19 and Figure 20 shown, optionally, the semiconductor power device further includes at least one of a first heat sink 71 and a second heat sink 72.

[0139] As Figure 20 described, at least one conductive region of the first metal layer 12 on the first circuit board 1 of the multi-chip power unit is correspondingly welded with a first heat sink 71, and the first heat sink 71 is a conductive plate.

[0140] Specifically, the conductive region and the corresponding first heat sink 71 are welded and connected. When first heat sinks 71 are correspondingly provided for different conductive regions, the first heat sinks 71 corresponding to different conductive regions are different from each other. The setting of the first heat sink 71 is beneficial to enhancing the heat conduction performance between the chip corresponding to the conductive region and the first insulating layer 11.

[0141] AsFigure 19 As shown, the first circuit board 1 of the multi-chip power unit is provided with a second metal layer 13 on a side thereof facing away from the first metal layer 12 in the thickness direction, and the second metal layer 13 is connected to the second heat sink 72 .

[0142] Specifically, the second metal layer 13 is welded to the second heat sink 72. The provision of the second heat sink 72 is conducive to enhancing the heat dissipation performance of the entire multi-chip power unit. In this case, illustratively, the second heat sink 72 can be embedded in the packaging shell 51 of the semiconductor power device and flush with the lower surface of the packaging shell 51, or the upper surface of the second heat sink 72 can be flush with the lower surface of the packaging shell 51, which is not a limitation.

[0143] In a third aspect, the present disclosure provides a power electronic device, which includes the semiconductor power device of the above embodiment, and / or includes the multi-chip power unit of the above embodiment. For example, the power electronic device is an inverter, a converter, etc.

[0144] Optionally, the power electronic device also includes a heat sink, the multi-chip power unit of the semiconductor power device is connected to the second circuit board, and the semiconductor power device is bonded and connected to the heat sink at one end close to the first circuit board 1 in the thickness direction of the first circuit board 1, and thermal conductive silicone can be provided at the bonding point.

[0145] In a fourth aspect, the present disclosure provides an electric power system, which includes the power electronic device of the above-mentioned embodiment, for example, the electric power system is a photovoltaic system.

[0146] Although the disclosure is disclosed as above, the protection scope of the disclosure is not limited thereto. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the disclosure, and these changes and modifications will fall within the protection scope of the disclosure.

Claims

1. A multi-chip power unit, characterized in that: The multi-chip power unit comprises a first circuit board (1), a first power chip unit (21), a second power chip unit (22), and a plurality of power terminals (31) for connecting to an external circuit; The first power chip unit (21) and the second power chip unit (22) are respectively arranged on the first circuit board (1); The plurality of power terminals (31) include a first power terminal (C1), and the first power chip unit (21) and the second power chip unit (22) are respectively provided with a first power connection portion (201) for conductively connecting to the first power terminal (C1); The projection of the first power terminal (C1) on a first setting surface parallel to the first circuit board (1) is a first projection; the projections of the two first power connecting parts (201) on the first setting surface are respectively second projections, and the two second projections are spaced apart and distributed along a first setting direction; The two second projections are both located within a set rectangular area (S1); the two edges of the set rectangular area (S1) along its width direction correspond to the two second projections respectively; the extension direction of the set rectangular area (S1) is set at a preset angle with the first set direction; and the first projection at least partially overlaps with the set rectangular area (S1).

2. The multi-chip power unit according to claim 1, wherein: The perpendicular bisector of the line connecting the two second projections passes through the first projection.

3. The multi-chip power unit according to claim 1, wherein: The ratio of the shortest path lengths of the conductive paths corresponding to different first power connection parts (201) is greater than or equal to 0.85 and less than or equal to 1.15; wherein the conductive path corresponding to the first power connection part (201) is formed between the first power connection part (201) and the first power terminal (C1).

4. The multi-chip power unit according to claim 1, wherein: The first power chip unit (21) and the second power chip unit (22) also respectively have a second power connection portion (202), and each of the second power connection portions (202) is respectively conductively connected to the power terminal (31) other than the first power terminal (C1).

5. The multi-chip power unit according to claim 4, characterized in that: The first power chip unit (21) comprises a first controllable switch tube (Q1), and the second power chip unit (22) comprises a second controllable switch tube (Q2); The first power connection portion (201) of the first power chip unit (21) corresponds to the collector of the first controllable switch tube (Q1), the second power connection portion (202) of the first power chip unit (21) corresponds to the emitter of the first controllable switch tube (Q1), and the first power connection portion (201) of the second power chip unit (22) corresponds to the collector of the second controllable switch tube (Q2), and the second power connection portion (202) of the second power chip unit (22) corresponds to the emitter of the second controllable switch tube (Q2); Alternatively, the first power connection portion (201) of the first power chip unit (21) corresponds to the emitter setting of the first controllable switch tube (Q1), the second power connection portion (202) of the first power chip unit (21) corresponds to the collector setting of the first controllable switch tube (Q1), and the first power connection portion (201) of the second power chip unit (22) corresponds to the emitter setting of the second controllable switch tube (Q2), and the second power connection portion (202) of the second power chip unit (22) corresponds to the collector setting of the second controllable switch tube (Q2); Alternatively, the first power connection portion (201) of the first power chip unit (21) corresponds to the emitter setting of the first controllable switch tube (Q1), the second power connection portion (202) of the first power chip unit (21) corresponds to the collector setting of the first controllable switch tube (Q1), and the first power connection portion (201) of the second power chip unit (22) corresponds to the collector setting of the second controllable switch tube (Q2), and the second power connection portion (202) of the second power chip unit (22) corresponds to the emitter setting of the second controllable switch tube (Q2); Alternatively, the first power connection portion (201) of the first power chip unit (21) corresponds to the collector setting of the first controllable switch tube (Q1), and the second power connection portion (202) of the first power chip unit (21) corresponds to the emitter setting of the first controllable switch tube (Q1); and the first power connection portion (201) of the second power chip unit (22) corresponds to the emitter setting of the second controllable switch tube (Q2), and the second power connection portion (202) of the second power chip unit (22) corresponds to the collector setting of the second controllable switch tube (Q2).

6. The multi-chip power unit according to claim 5, characterized in that: When the first power connection portion (201) of the first power chip unit (21) is arranged corresponding to the collector of the first controllable switch tube (Q1), and the first power connection portion (201) of the second power chip unit (22) is arranged corresponding to the collector of the second controllable switch tube (Q2); the two second power connection portions (202) are respectively conductively connected to the two power terminals (31) other than the first power terminal (C1), and the two power terminals (31) other than the first power terminal (C1) are insulated from each other, or the two second power connection portions (202) are both conductively connected to at least one power terminal (31) other than the first power terminal (C1); When the first power connection portion (201) of the first power chip unit (21) is arranged corresponding to the emitter of the first controllable switch tube (Q1), and the first power connection portion (201) of the second power chip unit (22) is arranged corresponding to the emitter of the second controllable switch tube (Q2); the two second power connection portions (202) are respectively conductively connected to the two power terminals (31) other than the first power terminal (C1), and the two power terminals (31) other than the first power terminal (C1) are insulated from each other, or the two second power connection portions (202) are both conductively connected to at least one power terminal (31) other than the first power terminal (C1); When the first power connection part (201) of the first power chip unit (21) is arranged corresponding to the emitter of the first controllable switch tube (Q1) and the first power connection part (201) of the second power chip unit (22) is arranged corresponding to the collector of the second controllable switch tube (Q2), or when the first power connection part (201) of the first power chip unit (21) is arranged corresponding to the collector of the first controllable switch tube (Q1) and the first power connection part (201) of the second power chip unit (22) is arranged corresponding to the emitter of the second controllable switch tube (Q2); the two second power connection parts (202) are respectively conductively connected to the two power terminals (31) other than the first power terminal (C1), and the two power terminals (31) other than the first power terminal (C1) are insulated from each other.

7. The multi-chip power unit according to claim 5, characterized in that: At least one of the first power chip unit (21) and the second power chip unit (22) further comprises a diode; The cathode of the diode of the first power chip unit (21) is electrically connected to the collector of the first controllable switch tube (Q1), and the anode is electrically connected to the emitter of the first controllable switch tube (Q1); The cathode of the diode of the second power chip unit (22) is electrically connected to the collector of the second controllable switch tube (Q2), and the anode is electrically connected to the emitter of the second controllable switch tube (Q2).

8. The multi-chip power unit according to any one of claims 5 to 7, characterized in that: The first power connection portion (201) or the second power connection portion (202) of the first power chip unit (21) corresponding to the collector of the first controllable switch tube (Q1), and the power terminal (31) corresponding to the collector of the first controllable switch tube (Q1) are both connected to the same conductive area of ​​the first metal layer (12) of the first circuit board (1); The first power connection portion (201) or the second power connection portion (202) of the second power chip unit (22) corresponding to the collector of the second controllable switch tube (Q2), and the power terminal (31) corresponding to the collector of the second controllable switch tube (Q2) are both connected to the same conductive area of ​​the first metal layer (12) of the first circuit board (1).

9. The multi-chip power unit according to any one of claims 1 to 7, characterized in that: In the first setting direction, the plurality of power terminals (31) are distributed in sequence, and the power terminal (31) is disposed on at least one side of the first power terminal (C1).

10. The multi-chip power unit according to any one of claims 1 to 7, characterized in that: The multi-chip power unit further comprises a signal terminal (32), a plurality of the power terminals (31) are sequentially distributed in the first setting direction, and the signal terminal (32) is distributed at one end or both ends of all the power terminals (31) in the first setting direction.

11. The multi-chip power unit according to claim 10, wherein: The power terminal (31) and the signal terminal (32) both comprise plug pins (61), and the plug pins (61) are parallel to each other; the plug pins (61) are parallel to the first circuit board (1), and the extension direction of the plug pins (61) is perpendicular to the first set direction.

12. A semiconductor power device, characterized in that: It comprises a packaging unit (5) and a multi-chip power unit according to any one of claims 1 to 11, wherein the packaging unit (5) packages the multi-chip power unit.

13. The semiconductor power device according to claim 12, characterized in that: The packaging unit (5) comprises a packaging shell (51), the packaging shell (51) forming a packaging cavity, the packaging cavity being used to accommodate at least a first power chip unit (21) and a second power chip unit (22) of the multi-chip power unit; the packaging shell (51) is also provided with a boss structure (52), and the fixed ends of the plug-in pins (61) of the multi-chip power unit are embedded in the boss structure (52); In the thickness direction of the first circuit board (1) of the multi-chip power unit, the projection of the plug pin (61) on the second setting surface, the projection of the first power chip unit (21) on the second setting surface, and the projection of the first circuit board (1) on the second setting surface are distributed in sequence, wherein the second setting surface is perpendicular to the first circuit board (1).

14. The semiconductor power device according to claim 12, characterized in that: The semiconductor power device further comprises at least one of a first heat sink (71) and a second heat sink (72); At least one conductive area of ​​the first metal layer (12) on the first circuit board (1) of the multi-chip power unit is correspondingly welded with the first heat sink (71), and the first heat sink (71) is a conductive plate; The first circuit board (1) of the multi-chip power unit is provided with a second metal layer (13) on a side thereof facing away from the first metal layer (12) in the thickness direction, and the second metal layer (13) is connected to the second heat sink (72).

15. A power electronic device, characterized in that: It comprises a multi-chip power unit as described in any one of claims 1-11, and / or it comprises a semiconductor power device as described in any one of claims 12-14.

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