Chip layout structure with built-in charge pump
By rationally laying out the circuit modules, setting output capacitances and adopting switch MOS tube design with high ESD protection capabilities in the chip layout structure, the existing built-in charge pump chip system has been solved, and higher power supply stability and ESD protection capabilities have been achieved.
Patent Information
- Application Number
- CN202421725691.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-19
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-07-19
AI Technical Summary
The chip system with built-in charge pumps has poor performance and insufficient ESD protection capabilities, which affects the performance and life of the chip system.
Design a chip layout structure with built-in charge pump, effectively isolate the digital circuit module and the analog circuit module through a reasonable and compact layout layout, and set the output capacitors in the chip, and use a switch MOS tube design with electrostatic discharge protection capability.
It improves the power supply stability of the charge pump in the chip, enhances ESD protection capabilities, reduces the manufacturing cost of the chip, and improves the performance and reliability of the chip.
Smart Images
Figure CN222965676U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuit design, in particular to a chip layout structure with a built-in charge pump. Background Art
[0002] With the continuous reduction of the feature size of the CMOS (Complementary Metal Oxide Semiconductor) process, the power supply voltage required by the chip system is also continuously reduced. However, some local circuits in the chip system may require a voltage several times higher than the power supply voltage to work properly. Therefore, the existing chip systems usually use a charge pump to generate a voltage higher than the power supply voltage to ensure the normal operation of the chip system or to improve the performance of the chip.
[0003] Since the output of the charge pump is usually used to supply power to other module loads in the chip system, in order to ensure the stability of power supply, a large capacitor is usually added at the output end. Considering the chip area, the large capacitor is generally placed on the circuit board outside the chip with a separate capacitor element to reduce the chip area. In this way, the chip needs to add a switch interface at the output end to connect to the external large capacitor. However, in actual applications, if the switch interface adopts the existing conventional design, there will be a situation of insufficient ESD (Electro-Static discharge) protection ability, thus affecting the performance and service life of the chip system.
[0004] In addition, in the existing chip layout design, usually all devices share the P-type substrate of the chip. However, the chip substrate is prone to generate various noises, so some devices in the chip will inevitably be affected by the substrate noise, thus affecting the performance of the entire chip. Summary of the Utility Model
[0005] The purpose of the utility model is to provide a chip layout structure with a built-in charge pump to at least solve the problem of poor performance of the existing chip system with a built-in charge pump.
[0006] To solve the above technical problems, the utility model provides a chip layout structure with a built-in charge pump, which is characterized by comprising a first layout area, a second layout area, a third layout area, a fourth layout area, a fifth layout area, a sixth layout area, a seventh layout area, an eighth layout area and a ninth layout area;
[0007] The first layout area is located in the upper left corner of the chip layout; the second layout area is located below the first layout area; the third layout area is located below the second layout area; the fourth layout area is located below the first layout area, to the right of the second layout area and the third layout area; the fifth layout area is located in the upper right corner of the chip layout; the sixth layout area is located below the fifth layout area; the seventh layout area is located below the fifth layout area, to the right of the sixth layout area; the eighth layout area is located below the fifth layout area, to the right of the seventh layout area; the ninth layout area is located below the chip layout.
[0008] Among them, an output terminal capacitor is arranged in the eighth layout area.
[0009] Optionally, in the chip layout structure with a built-in charge pump, the left edge of the second layout area is aligned with the left edge of the first layout area; the left and right edges of the third layout area are aligned with the left and right edges of the second layout area; the upper edge of the fourth layout area is aligned with the upper edge of the second layout area, the lower edge is aligned with the lower edge of the third layout area, and the right edge is aligned with the right edge of the first layout area; the upper edge of the fifth layout area is aligned with the upper edge of the first layout area; the left edge of the sixth layout area is aligned with the left edge of the fifth layout area, and the lower edge is aligned with the lower edge of the fourth layout area; the upper and lower edges of the seventh layout area are aligned with the upper and lower edges of the sixth layout area; the upper and lower edges of the eighth layout area are aligned with the upper and lower edges of the seventh layout area; the left edge of the ninth layout area is aligned with the left edge of the first layout area, and the right edge is aligned with the right edge of the fifth layout area.
[0010] Optionally, in the chip layout structure with a built-in charge pump, the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area and the ninth layout area are all rectangular and are arranged at intervals.
[0011] Optionally, in the chip layout structure with a built-in charge pump, a shift register and a low-voltage to high-voltage unit array are arranged in the first layout area to provide control signals; a reference voltage generation module is arranged in the second layout area to provide a reference voltage for a comparator; a feedback voltage generation module is arranged in the third layout area to provide a feedback voltage for the comparator; a comparator is arranged in the fourth layout area to generate a comparison voltage; a voltage boosting module is arranged in the fifth layout area to generate a boosted voltage; an oscillator is arranged in the sixth layout area to convert the comparison voltage into an oscillating voltage and then input it to the voltage boosting module; a switch module is arranged in the seventh layout area; an input / output interface is arranged in the ninth layout area.
[0012] Optionally, in the chip layout structure with the built-in charge pump, the first layout area is connected by traces to the second layout area, the third layout area, the fourth layout area, the fifth layout area, and the sixth layout area; the second layout area is connected by traces to the fourth layout area; the third layout area is connected by traces to the fourth layout area and the seventh layout area; the fourth layout area is connected by traces to the sixth layout area; the fifth layout area is connected by traces to the sixth layout area and the seventh layout area; the seventh layout area is connected by traces to the eighth layout area and the ninth layout area.
[0013] Optionally, in the chip layout structure with the built-in charge pump, the switching module includes switching MOS transistors.
[0014] The switching MOS transistors adopt a source-drain asymmetric design, and the drain is wider than the source.
[0015] And / or, the drain of the switching MOS transistor has a ring-shaped metal silicide blocking layer.
[0016] And / or, an electrostatic discharge voltage withstand layer is added to the drain of the switching MOS transistor.
[0017] Optionally, in the chip layout structure with the built-in charge pump, two of the switching MOS transistors form a switching unit, and the switching module includes multiple groups of parallel-connected switching units.
[0018] Optionally, in the chip layout structure with the built-in charge pump, the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area, and the ninth layout area are all formed on an isolation structure; the isolation structure is used to isolate the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area, and the ninth layout area from the chip substrate.
[0019] Optionally, in the chip layout structure with the built-in charge pump, the isolation structure includes a deep N-well layer, a ring-shaped N-well layer formed on the deep N-well layer, and a P-type substrate filled in the ring-shaped N-well layer; the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area, and the ninth layout area are all formed on the P-type substrate.
[0020] Optionally, in the chip layout structure with the built-in charge pump, a reverse bias voltage is connected between the chip substrate and the ring-shaped N-well layer.
[0021] The chip layout structure with a built-in charge pump provided by the present utility model includes a first layout area, a second layout area, a third layout area, a fourth layout area, a fifth layout area, a sixth layout area, a seventh layout area, an eighth layout area, and a ninth layout area; the first layout area is located in the upper left corner of the chip layout; the second layout area is located below the first layout area; the third layout area is located below the second layout area; the fourth layout area is located below the first layout area and to the right of the second layout area and the third layout area; the fifth layout area is located in the upper right corner of the chip layout; the sixth layout area is located below the fifth layout area; the seventh layout area is located below the fifth layout area and to the right of the sixth layout area; the eighth layout area is located below the fifth layout area and to the right of the seventh layout area; the ninth layout area is located below the chip layout; wherein, an output terminal capacitor is arranged in the eighth layout area. Through a reasonable and compact layout, while the digital circuit module and the analog circuit module of the charge pump in the chip can be effectively isolated, the chip area is fully utilized, thereby not only reducing the manufacturing cost of the chip, but also improving the performance of the chip; by setting an output terminal capacitor in the chip, the power supply stability of the charge pump in the chip can be improved to a certain extent, and the problem of poor performance of the existing chip system with a built-in charge pump is solved. Description of the Drawings
[0022] Figure 1 is the circuit schematic diagram of the charge pump provided by this embodiment;
[0023] Figure 2 is the schematic diagram of the chip layout structure with a built-in charge pump provided by this embodiment;
[0024] Figure 3 is the schematic diagram of the semiconductor structure of the switch module provided by this embodiment;
[0025] Figure 4 is the schematic diagram of the chip semiconductor structure with a built-in charge pump provided by this embodiment;
[0026] Figure 5 is the schematic diagram of the semiconductor device manufacturing structure provided by this embodiment. Detailed Embodiments
[0027] The following further details the chip layout structure with a built-in charge pump proposed by the present utility model in conjunction with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present utility model. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the focus to be shown in each drawing is different, and sometimes different scales are used.
[0028] It should be noted that the "first", "second", etc. in the description, claims and attached drawings of the present utility model are used to distinguish similar objects in order to describe the embodiments of the present utility model, rather than to describe a specific order or sequence. It should be understood that such structures can be interchanged under appropriate circumstances. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0029] The charge pump provided in this embodiment has a circuit schematic diagram as Figure 1 shown, and mainly includes a shift register (SR), a low-voltage to high-voltage unit array (L2H), a reference voltage generation module, a feedback voltage generation module, a comparator, an oscillator (OSC), a voltage boost module (Boost boost circuit), a switch module, an output terminal capacitor, and an input / output interface.
[0030] The operating principle of the charge pump provided in this embodiment is generally as follows: Set the required voltage value at the reference voltage generation module, and the voltage value generated at node A is fed back to the feedback voltage generation module after voltage division; The comparator compares the set voltage at the reference voltage generation module with the feedback voltage at the feedback voltage generation module. If the feedback voltage is less than the set voltage, the output of the comparator is given to the oscillator to obtain a rectangular wave to the voltage boost module, and the voltage boost module is used to boost the voltage, so that the voltage at node A increases; Continuous feedback and boosting are performed until the feedback voltage is equal to the set voltage. When the feedback voltage at node A has not reached the set voltage, the switch module is in the off state, and the input / output interface does not output voltage; until the feedback voltage reaches the set voltage, the switch module conducts, and after noise reduction by the output terminal capacitor, it is output by the input / output interface.
[0031] In the prior art, usually the output terminal capacitor is relatively large and is arranged outside the chip, and is connected to the circuit system through the switch module. When using a conventional switch design, it is very easy to occur the situation of insufficient ESD protection ability, thus affecting the performance and life of the chip system.
[0032] Based on this, this embodiment proposes a chip layout structure with a built-in charge pump, as Figure 2As shown, the chip layout structure includes a first layout area, a second layout area, a third layout area, a fourth layout area, a fifth layout area, a sixth layout area, a seventh layout area, an eighth layout area, and a ninth layout area; the first layout area is located in the upper left corner of the chip layout; the second layout area is located below the first layout area; the third layout area is located below the second layout area; the fourth layout area is located below the first layout area, to the right of the second layout area and the third layout area; the fifth layout area is located in the upper right corner of the chip layout; the sixth layout area is located below the fifth layout area; the seventh layout area is located below the fifth layout area, to the right of the sixth layout area; the eighth layout area is located below the fifth layout area, to the right of the seventh layout area; the ninth layout area is located below the chip layout; wherein, an output terminal capacitor is arranged in the eighth layout area.
[0033] The chip layout structure with a built-in charge pump provided in this embodiment enables effective isolation between the digital circuit module and the analog circuit module of the charge pump in the chip while making full use of the chip area through a reasonable and compact layout, thereby not only reducing the manufacturing cost of the chip but also improving the performance of the chip; by setting an output terminal capacitor in the chip, the power supply stability of the charge pump in the chip can be improved to a certain extent, solving the problem of poor performance of the existing chip system with a built-in charge pump.
[0034] Furthermore, in order to make full use of the chip area, in this embodiment, the left edge of the second layout area is aligned with the left edge of the first layout area; the left and right edges of the third layout area are aligned with the left and right edges of the second layout area; the upper edge of the fourth layout area is aligned with the upper edge of the second layout area, the lower edge is aligned with the lower edge of the third layout area, and the right edge is aligned with the right edge of the first layout area; the upper edge of the fifth layout area is aligned with the upper edge of the first layout area; the left edge of the sixth layout area is aligned with the left edge of the fifth layout area, and the lower edge is aligned with the lower edge of the fourth layout area; the upper and lower edges of the seventh layout area are aligned with the upper and lower edges of the sixth layout area; the upper and lower edges of the eighth layout area are aligned with the upper and lower edges of the seventh layout area; the left edge of the ninth layout area is aligned with the left edge of the first layout area, and the right edge is aligned with the right edge of the fifth layout area.
[0035] Preferably, for the convenience of subsequent chip processing and to ensure sufficient space for effective isolation between the digital circuit module and the analog circuit module, in this embodiment, the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area, and the ninth layout area are all rectangular and are arranged at intervals.
[0036] Control Figure 1 and Figure 2 , the layout method and reasons of the chip layout structure with a built-in charge pump provided in this embodiment are described in detail:
[0037] In this embodiment, a shift register (SR) and a low-voltage to high-voltage unit array (L2H) are arranged in the first layout area to provide control signals. Specifically, the first layout area is connected by traces to the second layout area, the third layout area, the fourth layout area, the fifth layout area, and the sixth layout area to provide control signals to the analog circuit modules in the second layout area, the third layout area, the fourth layout area, the fifth layout area, and the sixth layout area through the traces. Since the accuracy requirements of each analog circuit module for the control signal are not high, it is not sensitive to the length of the traces; at the same time, considering that the digital circuit module and the analog circuit module need to be designed separately, the first layout area is set in the upper left corner of the chip layout, with a certain distance from the circuit modules in other layouts.
[0038] In addition, a reference voltage generation module is arranged in the second layout area to provide a reference voltage for the comparator. Specifically, the second layout area is connected by traces to the fourth layout area. Since the output of the reference voltage generation module is an input of the comparator and this module is controlled by the control signal, it is set adjacent to the first layout area and the fourth layout area and connected by traces.
[0039] Similarly, a feedback voltage generation module is arranged in the third layout area to provide a feedback voltage for the comparator. Specifically, the third layout area is connected by traces to the fourth layout area. Since the output of the feedback voltage generation module is the other input of the comparator and this module is controlled by the control signal, it is set adjacent to the first layout area and the fourth layout area and connected by traces. In addition, since the feedback voltage generation module also needs to receive the feedback voltage at the output OUT terminal, the third layout area also needs to be connected by traces to the seventh layout area. To reduce trace crossing, the third layout area is set at a position lower on the left side.
[0040] In addition, a comparator is arranged in the fourth layout area to generate a comparison voltage. Specifically, the input terminals of the fourth layout area are connected by traces to the first layout area, the second layout area, and the third layout area. Considering that the comparator needs to receive the set voltage of the reference voltage generation module and the feedback voltage of the feedback voltage generation module, the fourth layout area is set adjacent to the second layout area and the third layout area, and the trace lengths therein are made as consistent as possible. At the same time, considering that the output of the comparator needs to be connected to the oscillator, the output terminal of the fourth layout area is connected by traces to the sixth layout area.
[0041] And, an oscillator is arranged in the sixth layout area, configured to convert a comparison voltage into an oscillation voltage and then input it to the voltage boosting module. Specifically, since the input of the oscillator needs to be connected to the output of the comparator, the sixth layout area is disposed adjacent to the fourth layout area and connected by traces. Meanwhile, considering that the oscillator is a noise module, it is kept at a certain distance from the circuit modules in other layout areas.
[0042] And, a voltage boosting module is arranged in the fifth layout area to generate a boosted voltage. Specifically, since the input of the voltage boosting module (Boost boost circuit) comes from the oscillator, the fifth layout area needs to be disposed adjacent to the sixth layout area and connected by traces; meanwhile, since the voltage boosting module is controlled by a control signal, the fifth layout area needs to be disposed adjacent to the first layout area and connected by traces. In addition, considering that there are capacitors in the Boost boost circuit, the area of the voltage boosting module is relatively large and has a certain jitter. To provide sufficient chip area and ensure the stability of the chip, the fifth layout area is set in the upper right corner and kept at a certain distance from other layout areas and modules.
[0043] And, a switch module is arranged in the seventh layout area. Since the switch module needs to be connected to the voltage boosting module and the output terminal capacitor, the seventh layout area is disposed adjacent to the eighth layout area and the ninth layout area and connected by traces.
[0044] And, an output terminal capacitor is arranged in the eighth layout area. Since the capacitor generally has a large area and it needs to be connected to the switch module, the eighth layout area is set on the right side adjacent to the seventh layout area and has a relatively large area.
[0045] And, an input / output interface is arranged in the ninth layout area. To supply power to the chip, output the boosted voltage, and provide an effective electrostatic discharge path, the ninth layout is set at the bottom of the chip layout and has a relatively long dimension. The ninth layout area is connected to the seventh layout area by traces.
[0046] Furthermore, considering the chip area limitation, using only the output terminal capacitor cannot meet the requirement of outputting a stable voltage, and a large capacitor still needs to be connected outside the chip through the switch module. Therefore, to improve the ESD protection ability of the switch module, in this embodiment, the switch module includes switching MOS transistors. Specifically, in this embodiment, as Figure 3 shown, two of the switching MOS transistors form a switch unit, and the switch module includes multiple groups of parallel switch units.
[0047] In order to further improve the ESD protection ability of the switching MOS transistor, in this embodiment, the switching MOS transistor adopts an asymmetric design for the source terminal and the drain terminal, and the drain terminal is wider than the source terminal. In this way, it can ensure that the drain terminal has the electrostatic discharge protection ability.
[0048] And / or, the drain terminal of the switching MOS transistor has a ring-shaped silicide blocking layer (SAB). In this way, it can ensure that no silicide is generated around the drain terminal, thereby increasing the resistance between the source terminal and the drain terminal.
[0049] And / or, an electrostatic discharge (ESD) withstand voltage layer is added to the drain terminal of the switching MOS transistor. In this way, it can effectively increase the high-voltage resistance ability of the switching MOS transistor.
[0050] Furthermore, considering that in the prior art, the devices in the chip are directly formed on the P-type substrate of the chip, which causes the devices to be affected by noise and results in poor chip performance. Therefore, in this embodiment, the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area, and the ninth layout area are all formed on an isolation structure; the isolation structure is used to isolate the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area, and the ninth layout area from the chip substrate.
[0051] Specifically, as Figure 4 shown, the isolation structure includes a deep N-well layer, a ring-shaped N-well layer formed on the deep N-well layer, and a P-type substrate filled in the ring-shaped N-well layer; the functional circuit modules composed of the devices arranged in the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area, and the ninth layout area are all formed on the P-type substrate. In this way, through the deep N-well layer and the ring-shaped N-well layer, the required P-type substrate of the layout area is separated from the P-type chip substrate, thereby avoiding the noise influence of the chip substrate on the device structure in the layout area.
[0052] In actual application, during device fabrication, as Figure 5 shown, PMOS devices can be fabricated on the N-well and connected to the deep N-well; NMOS devices can be fabricated on the P-type substrate of the isolation structure and completely isolated from the chip substrate, so as to make full use of the area of the isolation structure.
[0053] Preferably, in order to prevent the latch-up effect, in this embodiment, a reverse bias voltage is connected between the chip substrate and the ring-shaped N-well layer.
[0054] The chip layout structure with a built-in charge pump provided in this embodiment effectively isolates the digital circuit module and the analog circuit module through reasonable and compact layout. The switch module adopts a design method with electrostatic discharge protection ability, and all devices are fabricated in an isolation structure, which not only optimizes the chip area but also ensures better performance and reliability of the chip.
[0055] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. In addition, the different parts among the embodiments can also be combined and used, and the present invention does not limit this.
[0056] The chip layout structure with a built-in charge pump provided in this embodiment includes a first layout area, a second layout area, a third layout area, a fourth layout area, a fifth layout area, a sixth layout area, a seventh layout area, an eighth layout area, and a ninth layout area. The first layout area is located in the upper left corner of the chip layout. The second layout area is located below the first layout area. The third layout area is located below the second layout area. The fourth layout area is located below the first layout area, to the right of the second layout area and the third layout area. The fifth layout area is located in the upper right corner of the chip layout. The sixth layout area is located below the fifth layout area. The seventh layout area is located below the fifth layout area, to the right of the sixth layout area. The eighth layout area is located below the fifth layout area, to the right of the seventh layout area. The ninth layout area is located below the chip layout. Among them, an output terminal capacitor is arranged in the eighth layout area. Through reasonable and compact layout, the digital circuit module and the analog circuit module of the charge pump in the chip can be effectively isolated while making full use of the chip area, thereby not only reducing the manufacturing cost of the chip but also improving the performance of the chip. By setting an output terminal capacitor in the chip, the power supply stability of the charge pump in the chip can be improved to a certain extent, solving the problem of poor performance of the existing chip system with a built-in charge pump.
[0057] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure are within the scope of protection of the claims.
Claims
1. A chip layout structure with a built-in charge pump, characterized in that: Including the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area and the ninth layout area; The first layout area is located at the upper left of the chip layout; the second layout area is located below the first layout area; the third layout area is located below the second layout area; the fourth layout area is located below the first layout area and to the right of the second layout area and the third layout area; the fifth layout area is located at the upper right of the chip layout; the sixth layout area is located below the fifth layout area; the seventh layout area is located below the fifth layout area and to the right of the sixth layout area; the eighth layout area is located below the fifth layout area and to the right of the seventh layout area; the ninth layout area is located below the chip layout; Wherein, the eighth layout area is arranged with output terminal capacitors.
2. The chip layout structure with a built-in charge pump according to claim 1, characterized in that: The left edge of the second layout area is aligned with the left edge of the first layout area; the left and right edges of the third layout area are aligned with the left and right edges of the second layout area; The upper edge of the fourth layout area is aligned with the upper edge of the second layout area, the lower edge is aligned with the lower edge of the third layout area, and the right edge is aligned with the right edge of the first layout area; the upper edge of the fifth layout area is aligned with the upper edge of the first layout area; the left edge of the sixth layout area is aligned with the left edge of the fifth layout area, and the lower edge is aligned with the lower edge of the fourth layout area; the upper and lower edges of the seventh layout area are aligned with the upper and lower edges of the sixth layout area; The upper and lower edges of the eighth layout area are aligned with the upper and lower edges of the seventh layout area; The left edge of the ninth layout area is aligned with the left edge of the first layout area, and the right edge is aligned with the right edge of the fifth layout area.
3. The chip layout structure with a built-in charge pump according to claim 1, characterized in that: The first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area and the ninth layout area are all rectangular and are spaced apart from each other.
4. The chip layout structure with a built-in charge pump according to claim 1, characterized in that: The first layout area is arranged with a shift register and a low-voltage to high-voltage unit array to provide a control signal; the second layout area is arranged with a reference voltage generating module to provide a reference voltage for the comparator; the third layout area is arranged with a feedback voltage generating module to provide a feedback voltage for the comparator; the fourth layout area is arranged with a comparator to generate a comparison voltage; the fifth layout area is arranged with a voltage boosting module to generate a boosting voltage; the sixth layout area is arranged with an oscillator for converting the comparison voltage into an oscillation voltage and then inputting it into the voltage boosting module; the seventh layout area is arranged with a switch module; and the ninth layout area is arranged with an input and output interface.
5. The chip layout structure with a built-in charge pump according to claim 4, characterized in that: The first layout area is connected by wiring with the second layout area, the third layout area, the fourth layout area, the fifth layout area and the sixth layout area; the second layout area is connected by wiring with the fourth layout area; the third layout area is connected by wiring with the fourth layout area and the seventh layout area; the fourth layout area is connected by wiring with the sixth layout area; the fifth layout area is connected by wiring with the sixth layout area and the seventh layout area; the seventh layout area is connected by wiring with the eighth layout area and the ninth layout area.
6. The chip layout structure with a built-in charge pump according to claim 4, characterized in that: The switch module includes a switch MOS tube; The switch MOS tube adopts an asymmetric design of the source end and the drain end, and the drain end is wider than the source end; And / or, the drain end of the switch MOS tube has a ring-shaped metal silicide barrier layer; And / or, an electrostatic release voltage-resistant layer is added to the drain end of the switch MOS tube.
7. The chip layout structure with a built-in charge pump according to claim 6, characterized in that: The two switch MOS tubes constitute a switch unit, and the switch module includes a plurality of switch units connected in parallel.
8. The chip layout structure with a built-in charge pump according to claim 1, characterized in that: The first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area and the ninth layout area are all formed on an isolation structure; the isolation structure is used to isolate the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area and the ninth layout area from the chip substrate.
9. The chip layout structure with a built-in charge pump according to claim 8, characterized in that: The isolation structure includes a deep N-well layer, an annular N-well layer formed on the deep N-well layer, and a P-type substrate filled in the annular N-well layer; the first layout area, the second layout area, the third layout area, the fourth layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area and the ninth layout area are all formed on the P-type substrate.
10. The chip layout structure with a built-in charge pump according to claim 9, characterized in that: A reverse bias voltage is connected between the chip substrate and the annular N-well layer.