MOS tube parallel circuit capable of improving use reliability of MOS tubes

Abstract

The utility model provides an MOS (Metal Oxide Semiconductor) tube parallel circuit capable of improving the use reliability of MOS tubes, which comprises a plurality of MOS tubes, the grid electrode G and the source electrode S of each MOS tube are electrically connected together, and the drain electrode D of each MOS tube is respectively connected into a circuit loop; a plurality of MOS tubes are connected in parallel to carry out rectification output, and a driving circuit of each MOS tube is connected in series with a driving resistor RG with a low resistance value, so that the problems of high-frequency interference signals generated during layout of a PCB and starting voltage deviation existing in the MOS tubes can be solved, the starting time of the plurality of MOS tubes can be ensured to be consistent as much as possible, and the reliability of the PCB is improved. Therefore, the instantaneous current borne by the single MOS tube is basically the same, and the anti-current impact risk of the MOS tube is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS transistor parallel circuits, and particularly relates to a MOS transistor parallel circuit that can improve the reliability of MOS transistor use. Background Art

[0002] In products with low-voltage and high-current output, since the output current is very large and has exceeded the maximum load current that a single MOS transistor can withstand, multiple MOS transistors need to be used in parallel to share the current-carrying capacity of the MOS transistors, reduce the energy consumption generated by the current in the MOS transistors, reduce heat generation, and improve the overall efficiency, so as to achieve the goals of energy conservation, emission reduction, and carbon emissions.

[0003] Taking the LLC resonant power converter circuit as an example, the LLC resonant circuit is the basic conversion unit. When the circuit resonates, conditions are created for the switching devices and output rectifying devices to turn on or off under zero-voltage or zero-current conditions, thereby achieving soft switching and reducing switching losses. Due to its simple structure and convenient control, it is widely used in high-efficiency switching power supplies. In an actual circuit with high-current output, the conduction loss of the output rectifying MOS transistor accounts for the main part. Therefore, reducing the impedance of the MOS transistor is the most important aspect. Based on the fact that the impedance of the current single MOS transistor has reached its limit in device design, when further reducing losses, the most effective method is to use multiple MOS transistors in parallel. However, the problems brought about are the consistency issues of multiple MOS transistors during the turn-on and use processes, and the difference in the instantaneous current of the MOS transistors caused by the sequence of switching, which leads to the risk of single MOS transistor failure. Summary of the Invention

[0004] Aiming at the defects existing in the prior art, the purpose of the utility model is to provide a MOS transistor parallel circuit that can improve the reliability of MOS transistor use, so as to solve the problem that the difference in the instantaneous current of MOS transistors caused by the sequence of switching of multiple existing MOS transistors in parallel leads to the risk of single MOS transistor failure.

[0005] To achieve the above purpose, the technical solution adopted by the utility model is as follows:

[0006] The present application provides a MOS transistor parallel circuit that can improve the reliability of MOS transistor use. The MOS transistor parallel circuit includes multiple MOS transistors. The gate G and source S of each MOS transistor are electrically connected together, and the drain D of each MOS transistor is respectively connected to the circuit loop.

[0007] Further, a driving resistor RG is serially installed on the gate G of each MOS transistor.

[0008] Further, the driving resistor RG is a low-resistance resistor that matches the MOS transistor electrically connected thereto.

[0009] Further, multiple MOS transistors are MOS transistors with the same parameters.

[0010] The beneficial effects of the present utility model are as follows: By using multiple MOS transistors in parallel for rectification output, and a low-resistance driving resistor RG is connected in series on the driving circuit of each MOS transistor, which is used to balance the high-frequency interference signals generated during PCB layout and the problem of the turn-on voltage deviation existing in the MOS transistor itself. At the same time, it can ensure that the turn-on time of multiple MOS transistors is as consistent as possible, so the instantaneous current borne by a single MOS transistor is basically the same, reducing the risk of current impact on the MOS transistor. Description of the Drawings

[0011] Figure 1 It is a schematic circuit diagram of a MOS transistor parallel circuit that can improve the reliability of MOS transistor use in the embodiment of the present application. Detailed Embodiment

[0012] The following further describes the present utility model in detail in conjunction with the drawings of the specification and the specific embodiments.

[0013] Refer to the attached Figure 1 As shown, this embodiment provides a MOS transistor parallel circuit 100 that can improve the reliability of MOS transistor use, which includes multiple MOS transistors 1. The multiple MOS transistors 1 are connected in parallel. Specifically, the gate G and the source S of each MOS transistor 1 are electrically connected together, and the drain D of each MOS transistor 1 is respectively connected to the circuit loop.

[0014] Continue to refer to the attached Figure 1 As shown, in order to balance the high-frequency interference signals generated during PCB layout and solve the problem of the turn-on voltage deviation existing in the Mos itself, a low-resistance driving resistor RG is connected in series on the driving circuit of each MOS transistor 1. The resistance value of the driving resistor RG is for the low-resistance resistor connected thereto. In addition, in order to ensure that the current value on each MOS transistor 1 is the same, multiple MOS transistors 1 adopt the MOS transistor structure with the same parameters.

[0015] For example, in this embodiment, there are six MOS transistors 1, and low-resistance driving resistors RG1, RG2, RG3, RG4, RG5, and RG6 are respectively connected in series on the driving circuits of the six MOS transistors 1.

[0016] By adopting multiple MOS transistors 1 in parallel for rectification output, and a low-resistance driving resistor RG is connected in series on the driving circuit of each MOS transistor 1, which is used to balance the high-frequency interference signals generated during PCB board layout and the problem of the turn-on voltage deviation existing in the MOS transistor 1 itself. At the same time, it can ensure that the turn-on time of multiple MOS transistors 1 is as consistent as possible, so the instantaneous current borne by a single MOS transistor 1 is basically the same, reducing the risk of current impact on the MOS transistor 1.

[0017] Obviously, those skilled in the art can make various changes and modifications to the present utility model without departing from the spirit and scope of the present utility model. Thus, if these modifications and variations of the present utility model fall within the scope of the claims of the present utility model and its equivalent technologies, then the present utility model is also intended to include these modifications and variations.

Claims

1. A MOS tube parallel circuit capable of improving the reliability of MOS tube use, characterized in that: The MOS tube parallel circuit includes multiple MOS tubes, the gate G and the source S of each MOS tube are electrically connected together, and the drain D of each MOS tube is respectively connected to the circuit loop.

2. A MOS tube parallel circuit capable of improving the reliability of MOS tube use according to claim 1, characterized in that: A driving resistor RG is installed in series on the gate G of each MOS tube.

3. The MOS tube parallel circuit capable of improving the reliability of MOS tube use according to claim 2, characterized in that: The driving resistor RG is a low-resistance resistor that matches the MOS tube electrically connected thereto.

4. A MOS tube parallel circuit capable of improving the reliability of MOS tube use according to claim 2 or 3, characterized in that: The multiple MOS tubes are MOS tubes with the same parameters.

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