Abnormal startup and shutdown judgment control circuit based on SIO and GP41

Abstract

The utility model belongs to the technical field of computer control, and particularly relates to an abnormal startup and shutdown judgment control circuit based on SIO and GP41, which comprises an SIO system, and the SIO system comprises a single chip microcomputer U57. A P1.7 interface of the single chip microcomputer U57 is electrically connected with a wireless transmitter GP41 through a resistor SR141, and the wireless transmitter GP41 is in signal connection with the MCU; the single chip microcomputer U57 is electrically connected with a connector, a debugging interface circuit and a burning interface circuit; the single chip microcomputer U57 is electrically connected with the MCU LED1; the single-chip microcomputer U57 is electrically connected with the CPU temperature detection circuit. According to the scheme, the SIO and the GP41 are added to serve as judgment bases when the system is shut down, the GP41 can send out low pulses when the system is shut down, and the MCU judges that the system is shut down legally after receiving the low pulses; on the contrary, if no pulse signal exists and only the PLTRST # becomes low, it is judged that abnormal power failure shutdown occurs, the MCU sends out a PSIN signal, and the starting step is executed.

Description

Technical Field

[0001] The utility model relates to the technical field of computer control, and particularly relates to an abnormal power-on and power-off judgment and control circuit based on SIO and GP41. Background Art

[0002] When working normally, the CPU sends a PLTRST# (normally high level) signal to the MCU, and the MCU recognizes the system state as powered on. When there is an accidental power outage, PLTRST# will become low, and when shutting down normally, PLTRST# will also become low. Judging only by the PLTRST# signal, the system will not be able to shut down.

[0003] Therefore, it is necessary to design an abnormal power-on and power-off judgment and control circuit based on SIO and GP41. Summary of the Utility Model

[0004] The purpose of the utility model is to provide an abnormal power-on and power-off judgment and control circuit based on SIO and GP41 to solve the problems raised in the background art.

[0005] To achieve the above purpose, the utility model provides the following technical solution: An abnormal power-on and power-off judgment and control circuit based on SIO and GP41, including an SIO system, where the SIO system includes a single-chip microcomputer U57, and the single-chip microcomputer U57 is an MS51FC0AETSSOP20 single-chip microcomputer;

[0006] The P1.7 interface of the single-chip microcomputer U57 is electrically connected to the wireless transmitter GP41 through a resistor SR141, and the wireless transmitter GP41 is signal-connected to the MCU;

[0007] The P0.4 interface of the single-chip microcomputer U57 is electrically connected to a resistor SR137. The resistor SR137 is connected to the positive pole of the 3.3V power supply through a resistor R2263. The resistor SR137 is connected to the power switch POWER BTN1 through a resistor SR138. The power switch POWER BTN1 is connected to the positive pole of the 3.3V power supply through a resistor R2081. The power switch POWERBTN1 is connected to the P1.0 interface of the single-chip microcomputer U57 through a resistor SR120. The power switch POWER BTN1 is connected to the pin 1 of the BAT54C SOT23 chip. The pin 2 of the BAT54C SOT23 chip is connected to the power switch POWER BTN2. The pin 3 of the BAT54C SOT23 chip is connected to a capacitor C1455. The pin 3 of the BAT54C SOT23 chip is connected to the pin 1 of the pin row HEADER1X2 through a resistor R2320. The pin 2 of the pin row HEADER1X2 is grounded;

[0008] The single-chip microcomputer U57 is electrically connected to a connector, a debugging interface circuit, and a programming interface circuit;

[0009] The single-chip microcomputer U57 is electrically connected to MCU_LED1;

[0010] The single-chip microcomputer U57 is electrically connected to the CPU temperature detection circuit.

[0011] For the abnormal power-on and power-off judgment and control circuit based on SIO and GP41 of the present utility model, wherein, the connector is a HEADER1X3 2.0MM connector, the P0.0 interface of the single-chip microcomputer U57 is electrically connected to pin 2 of the connector through the resistor SR139, pin 1 of the connector is connected to the positive pole of the 3.3V power supply through the resistor SR2265, and pin 3 of the connector is grounded through the resistor SR140.

[0012] For the abnormal power-on and power-off judgment and control circuit based on SIO and GP41 of the present utility model, wherein, the P0.5 interface of the single-chip microcomputer U57 is electrically connected to the positive pole of MCU_LED1, and the negative pole of MCU_LED1 is grounded through the resistor 2SR147.

[0013] For the abnormal power-on and power-off judgment and control circuit based on SIO and GP41 of the present utility model, wherein, the debugging interface circuit includes a connection terminal J4, the specification of the connection terminal J4 is HEADER 1X4 2.54MM, port 1 of the connection terminal J4 is grounded, port 2 of the connection terminal J4 is electrically connected to the P0.7 interface of the single-chip microcomputer U57, port 3 of the connection terminal J4 is electrically connected to the P0.6 interface of the single-chip microcomputer U57, and port 4 of the connection terminal J4 is connected to the positive pole of the 3.3V power supply.

[0014] For the abnormal power-on and power-off judgment and control circuit based on SIO and GP41 of the present utility model, wherein, the programming interface circuit includes a wiring terminal J3, the specification of the wiring terminal J3 is HEADER 1X52.54MM, port 1 of the wiring terminal J3 is grounded, port 2 of the wiring terminal J3 is electrically connected to the reset key nRESET, the reset key nRESET is electrically connected to the P2.0 interface of the single-chip microcomputer U57, the reset key nRESET is grounded through the capacitor C1361, port 3 of the wiring terminal J3 is electrically connected to the P0.2 interface of the single-chip microcomputer U57, port 4 of the wiring terminal J3 is electrically connected to the P1.6 interface of the single-chip microcomputer U57, and port 5 of the wiring terminal J3 is connected to the positive pole of the 3.3V power supply.

[0015] The abnormal power-on and power-off judgment and control circuit based on SIO and GP41 according to the present utility model, wherein the CPU temperature detection circuit includes a digital temperature sensor chip, the specification of the digital temperature sensor chip is TMP75AIDR / 12bit / SOIC8, the SDA pin of the digital temperature sensor chip is electrically connected to the P1.4 interface of the single-chip microcomputer U57, the SCL pin of the digital temperature sensor chip is electrically connected to the P1.3 interface of the single-chip microcomputer U57, the positive pole of the 3.3V power supply is respectively connected to the SDA and SCL pins of the digital temperature sensor chip through the resistor R435 and the resistor R446, the positive pole of the 3.3V power supply is connected to the OS pin of the digital temperature sensor chip through R426, the CND pin of the digital temperature sensor chip is grounded, the VCC pin of the digital temperature sensor chip is connected to the positive pole of the 3.3V power supply, the VCC pin of the digital temperature sensor chip is grounded through the capacitor C274, the VCC pin of the digital temperature sensor chip is respectively connected to its A0, A1, A2 pins through the resistors R2241, R2242, R2243, and the A0, A1, A2 pins are respectively grounded through the resistors R2244, R2245, R2246.

[0016] The abnormal power-on and power-off judgment and control circuit based on SIO and GP41 according to the present utility model, wherein the VSS pin of the single-chip microcomputer U57 is grounded, and the P1.6 pin of the single-chip microcomputer U57 is connected to the positive pole of the 3.3V power supply through the resistor R455; the VDD pin of the single-chip microcomputer U57 is connected to the positive pole of the 3.3V power supply through the resistor R337, the VDD pin of the single-chip microcomputer U57 is electrically connected to the positive poles of the capacitor C1363 and the capacitor C1362, and the negative poles of the capacitor C1363 and the capacitor C1362 are connected in parallel and then grounded.

[0017] Compared with the prior art, the beneficial effects of the present utility model: The abnormal power-on and power-off judgment and control circuit based on SIO and GP41 adds SIO and GP41 as the judgment basis when the system shuts down. When the system shuts down, GP41 will emit a low pulse of 100MS. After the MCU receives it, it is determined as a legal shutdown; otherwise, without a pulse signal and only PLTRST# becoming low, it is determined as an abnormal power-off shutdown, and the MCU emits a PSIN signal and enters the power-on step.

[0018] In addition, through the connector, the debugging interface circuit and the programming interface circuit, it is convenient to program and debug the program, and through the CPU temperature detection circuit, it is convenient to detect the temperature of the CPU. Description of the Drawings

[0019] To more clearly illustrate the specific embodiments of the present utility model or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is the circuit diagram of the single-chip microcomputer U57 of the abnormal power-on and power-off judgment and control circuit of the present utility model based on SIO and GP41;

[0021] Figure 2 It is the partial circuit diagram of the abnormal power-on and power-off judgment and control circuit of the present utility model based on SIO and GP41;

[0022] Figure 3 It is the circuit diagram of the connector of the abnormal power-on and power-off judgment and control circuit of the present utility model based on SIO and GP41;

[0023] Figure 4 It is the circuit diagram of MCU_LED1 of the abnormal power-on and power-off judgment and control circuit of the present utility model based on SIO and GP41;

[0024] Figure 5 It is the circuit diagram of the debugging interface circuit of the present utility model;

[0025] Figure 6 It is the circuit diagram of the programming interface circuit of the present utility model;

[0026] Figure 7 It is the circuit diagram of the CPU temperature detection circuit of the present utility model Specific Embodiments

[0027] The terms "first", "second", "third", "fourth", etc. in the specification, claims and drawings of the present utility model are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include steps or units not listed, or may optionally further include other steps or units inherent to these processes, methods, products or devices.

[0028] Reference to "embodiment" in this document means that the specific features, structures, or characteristics described in connection with the embodiment may be included in at least one embodiment of the present utility model. The phrase appearing at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0029] "Plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0030] Moreover, terms indicating directions such as "upper, lower, left, right, upper end, lower end, longitudinal" etc. are all referenced based on the attitude position of the device or equipment described in this solution during normal use.

[0031] In order to make the objectives, technical solutions, and advantages of the embodiments of the present utility model clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model. Obviously, the described embodiments are partial embodiments of the present utility model, rather than all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present utility model.

[0032] Please refer to Figure 1 - Figure 2 as shown, in the embodiment of the utility model,

[0033] An abnormal power-on / off judgment and control circuit based on SIO and GP41 includes: an SIO system, the SIO system includes a single-chip microcomputer U57, and the single-chip microcomputer U57 is an MS51FC0AE TSSOP20 single-chip microcomputer;

[0034] The P1.7 interface of the single-chip microcomputer U57 is electrically connected to the wireless transmitter GP41 through a resistor SR141, and the wireless transmitter GP41 is signal-connected to the MCU;

[0035] The P0.4 interface of the single-chip microcomputer U57 is electrically connected to the resistor SR137. The resistor SR137 is connected to the positive pole of the 3.3V power supply through the resistor R2263. The resistor SR137 is electrically connected to the power switch POWER BTN1 through the resistor SR138. The power switch POWER BTN1 is connected to the positive pole of the 3.3V power supply through the resistor R2081. The power switch POWER BTN1 is electrically connected to the P1.0 interface of the single-chip microcomputer U57 through the resistor SR120. The power switch POWER BTN1 is connected to the pin 1 of the BAT54C SOT23 chip. The pin 2 of the BAT54C SOT23 chip is connected to the power switch POWER BTN2. The pin 3 of the BAT54C SOT23 chip is electrically connected to the capacitor C1455. The pin 3 of the BAT54C SOT23 chip is connected to the pin 1 of the pin row HEADER1X2 through the resistor R2320. The pin 2 of the pin row HEADER1X2 is grounded;

[0036] The single-chip microcomputer U57 is electrically connected to a connector, a debugging interface circuit, and a programming interface circuit;

[0037] The single-chip microcomputer U57 is electrically connected to the MCU_LED1;

[0038] The single-chip microcomputer U57 is electrically connected to the CPU temperature detection circuit.

[0039] Please refer to Figure 1 and Figure 3 As shown, the connector is a HEADER1X3 2.0MM connector. The P0.0 interface of the single-chip microcomputer U57 is electrically connected to the pin 2 of the connector through the resistor SR139. The pin 1 of the connector is connected to the positive pole of the 3.3V power supply through the resistor SR2265. The pin 3 of the connector is grounded through the resistor SR140.

[0040] Please refer to Figure 1 and Figure 4 As shown, the P0.5 interface of the single-chip microcomputer U57 is connected to the positive pole of the MCU_LED1. The negative pole of the MCU_LED1 is grounded through the resistor 2SR147.

[0041] Please refer to Figure 1 and Figure 5 As shown, the debugging interface circuit includes the connection terminal J4. The specification of the connection terminal J4 is HEADER1X4 2.54MM. The port 1 of the connection terminal J4 is grounded. The port 2 of the connection terminal J4 is electrically connected to the P0.7 interface of the single-chip microcomputer U57. The port 3 of the connection terminal J4 is electrically connected to the P0.6 interface of the single-chip microcomputer U57. The port 4 of the connection terminal J4 is connected to the positive pole of the 3.3V power supply.

[0042] Please refer to Figure 1And Figure 6 As shown in the figure, the programming interface circuit includes a terminal block J3. The specification of the terminal block J3 is HEADER 1X5 2.54MM. The port 1 of the terminal block J3 is grounded. The port 2 of the terminal block J3 is electrically connected to the reset key nRESET. The reset key nRESET is electrically connected to the P2.0 interface of the single-chip microcomputer U57. The reset key nRESET is grounded through the capacitor C1361. The port 3 of the terminal block J3 is electrically connected to the P0.2 interface of the single-chip microcomputer U57. The port 4 of the terminal block J3 is electrically connected to the P1.6 interface of the single-chip microcomputer U57. The port 5 of the terminal block J3 is connected to the positive pole of the 3.3V power supply.

[0043] Please refer to Figure 1 And Figure 7 As shown in the figure, the CPU temperature detection circuit includes a digital temperature sensor chip. The specification of the digital temperature sensor chip is TMP75AIDR / 12bit / SOIC8. The SDA pin of the digital temperature sensor chip is electrically connected to the P1.4 interface of the single-chip microcomputer U57. The SCL pin of the digital temperature sensor chip is electrically connected to the P1.3 interface of the single-chip microcomputer U57. The positive pole of the 3.3V power supply is connected to the SDA and SCL pins of the digital temperature sensor chip through the resistors R435 and R446 respectively. The positive pole of the 3.3V power supply is connected to the OS pin of the digital temperature sensor chip through R426. The CND pin of the digital temperature sensor chip is grounded. The VCC pin of the digital temperature sensor chip is connected to the positive pole of the 3.3V power supply. The VCC pin of the digital temperature sensor chip is grounded through the capacitor C274. The VCC pin of the digital temperature sensor chip is connected to its A0, A1, and A2 pins through the resistors R2241, R2242, and R2243 respectively. The A0, A1, and A2 pins are grounded through the resistors R2244, R2245, and R2246 respectively.

[0044] Please refer to Figure 1 As shown in the figure, the VSS pin of the single-chip microcomputer U57 is grounded. The P1.6 pin of the single-chip microcomputer U57 is connected to the positive pole of the 3.3V power supply through the resistor R455. The VDD pin of the single-chip microcomputer U57 is connected to the positive pole of the 3.3V power supply through the resistor R337. The VDD pin of the single-chip microcomputer U57 is electrically connected to the positive poles of the capacitors C1363 and C1362. The negative poles of the capacitors C1363 and C1362 are connected in parallel and then grounded.

[0045] Traditional determination method:

[0046] When working normally, the CPU sends a PLTRST# (normally high level) signal to the MCU, and the MCU recognizes the system state as powered on. When there is an unexpected power outage, PLTRST# will become low. When shutting down normally, PLTRST# will also become low. Relying solely on the PLTRST# signal for judgment, the system will not be able to shut down;

[0047] Determination method of this solution:

[0048] Due to power grid fluctuations, the system may think it is powered on when it is actually not. The MCU adds a flag signal. When the power-on signal is sent to the MCU and there is an electrical signal sent to the MCU, a restart is required. When it is really necessary to shut down, a separate shutdown signal or forced shutdown needs to be sent;

[0049] Add SIO and GP41 as the determination basis when the system shuts down. When the system shuts down, GP41 will send a low pulse for 100 ms. After the MCU receives it, it is determined as a legal shutdown; conversely, if there is no pulse signal and only PLTRST# becomes low, it is determined as an abnormal power-off shutdown, and the MCU sends a PSIN signal to enter the power-on procedure.

[0050] In addition, the program can be easily burned and debugged through the connector, debug interface circuit, and burn interface circuit, and the temperature of the CPU can be easily detected through the CPU temperature detection circuit.

[0051] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations shall fall within the protection scope of the appended claims of the present utility model.

Claims

1. An abnormal power on / off judgment control circuit based on SIO and GP41, characterized in that: It includes an SIO system, wherein the SIO system includes a single-chip microcomputer U57, and the single-chip microcomputer U57 is a MS51FC0AE TSSOP20 single-chip microcomputer; The P1.7 interface of the single-chip computer U57 is electrically connected to the wireless transmitter GP41 through the resistor SR141, and the wireless transmitter GP41 is connected to the MCU signal; The P0.4 interface of the single-chip computer U57 is electrically connected to a resistor SR137, and the resistor SR137 is connected to the positive electrode of the 3.3V power supply through a resistor R2263. The resistor SR137 is electrically connected to the power switch POWER BTN1 through a resistor SR138. The power switch POWER BTN1 is connected to the positive electrode of the 3.3V power supply through a resistor R2081. The power switch POWER BTN1 is electrically connected to the P1.0 interface of the single-chip computer U57 through a resistor SR120. The power switch POWER BTN1 is electrically connected to pin 1 of the BAT54CSOT23 chip, and pin 2 of the BAT54C SOT23 chip is electrically connected to the power switch POWER BTN2. Pin 3 of the BAT54C SOT23 chip is electrically connected to a capacitor C1455. Pin 3 of the SOT23 chip is electrically connected to pin 1 of the header HEADER1X2 through resistor R2320, and pin 2 of the header HEADER1X2 is grounded; The single chip microcomputer U57 is electrically connected with a connector, a debugging interface circuit, and a burning interface circuit; The single chip microcomputer U57 is electrically connected to MCU_LED1; The single chip microcomputer U57 is electrically connected to the CPU temperature detection circuit.

2. The abnormal on / off judgment control circuit based on SIO and GP41 according to claim 1, characterized in that: The connector is a HEADER1X3 2.0MM connector. The P0.0 interface of the microcontroller U57 is electrically connected to pin 2 of the connector through resistor SR139. Pin 1 of the connector is connected to the positive pole of the 3.3V power supply through resistor SR2265. Pin 3 of the connector is grounded through resistor SR140.

3. The abnormal on / off judgment control circuit based on SIO and GP41 according to claim 1, characterized in that: The interface of P0.5 of the single chip microcomputer U57 is electrically connected to the positive electrode of MCU_LED1, and the negative electrode of MCU_LED1 is grounded through the resistor 2SR147.

4. The abnormal on / off judgment control circuit based on SIO and GP41 according to claim 1, characterized in that: The debugging interface circuit includes a connection terminal J4, the specification of the connection terminal J4 is HEADER 1X4 2.54MM, the port 1 of the connection terminal J4 is grounded, the port 2 of the connection terminal J4 is electrically connected to the P0.7 interface of the microcontroller U57, the port 3 of the connection terminal J4 is electrically connected to the P0.6 interface of the microcontroller U57, and the port 4 of the connection terminal J4 is connected to the positive pole of the 3.3V power supply.

5. The abnormal on / off judgment control circuit based on SIO and GP41 according to claim 1, characterized in that: The burning interface circuit includes a terminal J3, the specification of the terminal J3 is HEADER 1X5 2.54MM, port 1 of the terminal J3 is grounded, port 2 of the terminal J3 is electrically connected to the reset key nRESET, the reset key nRESET is electrically connected to the P2.0 interface of the microcontroller U57, the reset key nRESET is grounded through a capacitor C1361, port 3 of the terminal J3 is electrically connected to the P0.2 interface of the microcontroller U57, port 4 of the terminal J3 is electrically connected to the P1.6 interface of the microcontroller U57, and port 5 of the terminal J3 is connected to the positive pole of a 3.3V power supply.

6. The abnormal on / off judgment control circuit based on SIO and GP41 according to claim 1, characterized in that: The CPU temperature detection circuit includes a digital temperature sensor chip, the specification of the digital temperature sensor chip is TMP75AIDR / 12bit / SOIC8, the SDA pin of the digital temperature sensor chip is electrically connected to the P1.4 interface of the single-chip microcomputer U57, the SCL pin of the digital temperature sensor chip is electrically connected to the P1.3 interface of the single-chip microcomputer U57, the positive electrode of the 3.3V power supply is connected to the SDA and SCL pins of the digital temperature sensor chip through resistors R435 and R446 respectively, and the 3.3V power supply The positive electrode is connected to the OS pin of the digital temperature sensor chip through R426, the CND pin of the digital temperature sensor chip is grounded, the VCC pin of the digital temperature sensor chip is connected to the positive electrode of the 3.3V power supply, the VCC pin of the digital temperature sensor chip is grounded through capacitor C274, and the VCC pin of the digital temperature sensor chip is connected to its A0, A1, and A2 pins through resistors R2241, R2242, and R2243, respectively, and the A0, A1, and A2 pins are grounded through resistors R2244, R2245, and R2246, respectively.

7. The abnormal on / off judgment control circuit based on SIO and GP41 according to claim 1, characterized in that: The VSS pin of the single-chip computer U57 is grounded, and the P1.6 pin of the single-chip computer U57 is connected to the positive electrode of the 3.3V power supply through the resistor R455; the VDD pin of the single-chip computer U57 is connected to the positive electrode of the 3.3V power supply through the resistor R337, and the VDD pin of the single-chip computer U57 is electrically connected to the positive electrodes of the capacitors C1363 and C1362, and the negative electrodes of the capacitors C1363 and C1362 are connected in parallel and then grounded.

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