Visual intelligent PD load tester

Abstract

The utility model provides a visual intelligent PD load tester, which utilizes a signal separation module to take a power receiving signal of PoE equipment to be tested, detects a PoE protocol through a PD chip protocol detection control module and outputs a PoE voltage to a load resistance module, an electrical parameter sampling module collects a voltage and a current value of the power receiving signal and inputs the voltage and the current value to the control module for conversion, and the control module controls the PD chip protocol detection control module to detect the PoE protocol and output the PoE voltage to the load resistance module. The control module outputs a parameter display control signal to the man-machine interaction module so as to display the port power of the PoE equipment, a user sends a power receiving power control signal to the control module through the man-machine interaction module, and when the overall power of the PoE equipment is measured, the control module outputs the power receiving power control signal to the load resistance module so as to display the port power of the PoE equipment. The load resistor module is controlled to supply power to the heat dissipation module to start the high-power heat dissipation fan, the power of the high-power heat dissipation fan is controlled through the man-machine interaction module, the reliability and stability of the tester are ensured, and the service life of the tester is prolonged.

Description

Technical Field

[0001] The utility model relates to the technical field of equipment detection, and particularly relates to a visual intelligent PD load tester. Background Technique

[0002] With the rapid development of the Internet of Things technology, the terminals that need to provide network services are becoming more and more abundant. It is becoming more and more difficult to supply power to various intelligent terminals in the traditional high-voltage way. The popularization of the Power over Ethernet (PoE) technology is gradually solving the power supply problems of various intelligent terminals. At present, the PoE technology has been extended from traditional application scenarios such as Wireless Local Area Network (WLAN), network monitoring, and IP telephones to various scenarios such as new retail, Internet of Things (IoT), and smart cities, and is widely used. It has the characteristics of low cost, convenient construction, stable power supply, and high operation and maintenance efficiency. Without any modification to the existing Ethernet wiring structure, the PoE technology can transmit data signals and provide DC power supply for IP-based terminals, and maintain compatibility with the existing Ethernet and users. In this way, there is no need to add processes such as grooving, pipe laying, wire threading, debugging, wall and floor beautification in the construction environment, greatly shortening the construction period and reducing the cost.

[0003] However, in the prior art, standard PoE devices all have a large PoE output power. If the power of the powered device (PD, Power Device) exceeds the maximum output power of the power supply device (PSE, Power Sourcing Equipment), the reliability and stability cannot be satisfied. Summary of the Utility Model

[0004] The utility model provides a visual intelligent PD load tester, and its purpose is to avoid the power supply power of the PoE device exceeding the power supply specification and power false labeling, and ensure the reliability and stability of the PoE device power supply.

[0005] To achieve the above purpose, the utility model provides a visual intelligent PD load tester, including:

[0006] A signal separation module, a PD chip protocol detection and control module, an electrical parameter sampling module, a control module, a human-computer interaction module, a load resistance module, and a heat dissipation module;

[0007] The input end of the signal separation module is connected to the output end of the PoE device to be tested, and the output end of the signal separation module is connected to the input end of the PD chip protocol detection and control module;

[0008] The first output terminal of the PD chip protocol detection and control module is connected to the input terminal of the electrical parameter sampling module, and the second output terminal of the PD chip protocol detection and control module is connected to the input terminal of the load resistance module;

[0009] The output terminal of the electrical parameter sampling module is connected to the input terminal of the control module;

[0010] The output terminal of the load resistance module is connected to the input terminal of the heat dissipation module, and the output terminal of the heat dissipation module is connected to the input terminal of the high-power heat dissipation fan;

[0011] The signal transmission terminal of the load resistance module is connected to the first signal transmission terminal of the control module;

[0012] The signal transmission terminal of the human-machine interaction module is connected to the second signal transmission terminal of the control module.

[0013] The signal output by the PoE device to be tested is input to the signal separation module, and the signal separation module outputs the powered signal to the PD chip protocol detection and control module and the electrical parameter sampling module;

[0014] The voltage and current values of the powered signal collected by the electrical parameter sampling module are input to the control module, and the control module outputs a parameter display control signal to the human-machine interaction module;

[0015] The human-machine interaction module outputs the received powered power control signal to the control module;

[0016] The control module outputs a powered power control signal to the load resistance module to energize the heat dissipation module and the high-power heat dissipation fan.

[0017] The above solution of the present utility model has the following beneficial effects:

[0018] The utility model includes a signal separation module, a PD chip protocol detection and control module, an electrical parameter sampling module, a control module, a human-computer interaction module, a load resistance module, and a heat dissipation module. Compared with the prior art, the power receiving signal of the PoE device to be measured is separately taken by the signal separation module, the PoE protocol is detected by the PD chip protocol detection and control module and the PoE voltage is output to the load resistance module. The electrical parameter sampling module collects the voltage and current values of the power receiving signal through connection with the PD chip protocol detection and control module and inputs them to the control module for conversion. The control module outputs a parameter display control signal to the human-computer interaction module to display the port power of the POE device. When measuring the overall power of the PoE device, the user sends a power receiving control signal to the control module through the human-computer interaction module. The control module outputs a switch signal for adjusting the on-off of the MOS tube to the load resistance module to supply power to the heat dissipation module to turn on the high-power fan. The control module sends a power receiving power control module to the load resistance module to measure the maximum overall power of the PoE device by adjusting the power of the load resistance module, ensuring the reliability and stability of the tester and enhancing the service life of the tester.

[0019] Other beneficial effects of the utility model will be described in detail in the subsequent specific implementation part. Brief Description of the Drawings

[0020] Figure 1 It is the principle block diagram of the embodiment of the utility model;

[0021] Figure 2 It is the wiring diagram of the PoE device to be measured in the embodiment of the utility model;

[0022] Figure 3 It is the circuit schematic diagram of the signal separation module in the embodiment of the utility model;

[0023] Figure 4 It is the circuit schematic diagram of the polarity calibration unit in the embodiment of the utility model;

[0024] Figure 5 It is the circuit schematic diagram of the protocol detection unit in the embodiment of the utility model;

[0025] Figure 6 It is the circuit schematic diagram of the load resistance module and the heat dissipation module in the embodiment of the utility model;

[0026] Figure 7 It is the circuit schematic diagram of the electrical parameter sampling module, the human-computer interaction module and the control module in the embodiment of the utility model. Detailed Description of the Preferred Embodiments

[0027] To make the technical problems, technical solutions and advantages to be solved by the present utility model clearer, the following will be described in detail with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are some embodiments of the present utility model, rather than all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0028] In the description of the present utility model, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present utility model. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, the technical features involved in different embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.

[0029] As Figure 1 shown, an embodiment of the present utility model provides a visual intelligent PD load tester, including:

[0030] a signal separation module, a PD chip protocol detection and control module, an electrical parameter sampling module, a control module, a human-machine interaction module, a load resistance module, and a heat dissipation module;

[0031] The input end of the signal separation module is connected to the output end of the PoE device to be tested, and the output end of the signal separation module is connected to the input end of the PD chip protocol detection and control module;

[0032] The first output end of the PD chip protocol detection and control module is connected to the input end of the electrical parameter sampling module, and the second output end of the PD chip protocol detection and control module is connected to the input end of the load resistance module;

[0033] The output end of the electrical parameter sampling module is connected to the input end of the control module;

[0034] The output end of the load resistance module is connected to the input end of the heat dissipation module, and the output end of the heat dissipation module is connected to the input end of the high-power heat dissipation fan;

[0035] The signal transmission end of the load resistance module is connected to the first signal transmission end of the control module;

[0036] The signal transmission end of the human-machine interaction module is connected to the second signal transmission end of the control module.

[0037] The signal output by the PoE device to be measured is input to the signal separation module, and the signal separation module outputs the powered signal to the PD chip protocol detection and control module and the electrical parameter sampling module;

[0038] The voltage and current values of the powered signal collected by the electrical parameter sampling module are input to the control module, and the control module outputs a parameter display control signal to the human-computer interaction module;

[0039] The human-computer interaction module outputs the received power control signal for the powered device to the control module;

[0040] The control module outputs a power control signal for the powered device to the load resistance module to energize the heat dissipation module and the high-power cooling fan.

[0041] The working principle of the embodiment of the present invention is as follows:

[0042] The signal separation module is used to separately extract the powered signal of the PoE device to be measured. The PD chip protocol detection and control module detects the PoE protocol and outputs the PoE voltage to the load resistance module. The electrical parameter sampling module collects the voltage and current values of the powered signal by connecting to the PD chip protocol detection and control module and inputs them to the control module for conversion. The control module outputs a parameter display control signal to the human-computer interaction module to display the port power of the POE device. When measuring the total power of the POE device, the user sends a power control signal for the powered device to the control module through the human-computer interaction module. The control module outputs a switch signal for adjusting the on / off of the MOS tube to the load resistance module to supply power to the heat dissipation module to turn on the high-power fan. The control module sends a power control module for the powered device to the load resistance module to measure the maximum total power of the PoE device by adjusting the power of the load resistance module.

[0043] In the embodiment of the present invention, from Figure 2 the wiring diagram of the PoE device to be measured shown, it can be seen that the PoE device to be measured can be powered in mode A and mode B. When the PoE device to be measured is powered in mode A, it is powered by ports 1, 2, 3, and 6, and a similar bridge rectifier structure is used to detect the power supply method. When the PoE device to be measured is in mode B, it is powered by ports 4, 5, 7, and 8, and a similar bridge rectifier structure is used to detect the power supply method. When the powered device detects a device with the BT protocol, the PoE device to be measured uses 8 wires to supply power, increasing the power supply in sequence.

[0044] Most preferably, as Figure 3 shown, the signal separation module for separating the power supply signal and the network signal in the PoE device to be measured includes:

[0045] Network transformer T1, first network port, second network port, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, fifth capacitor C5, sixth capacitor C6, seventh capacitor C7, eighth capacitor C8, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8;

[0046] The first pin of the network transformer T1 is connected to the first end of the first resistor R1, and the second end of the second resistor R2 is connected to the first end of the first capacitor C1;

[0047] The fourth pin of the network transformer T1 is connected to the first end of the second resistor R2, and the second end of the first resistor R1 is connected to the first end of the second capacitor C2;

[0048] The seventh pin of the network transformer T1 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the first end of the third capacitor C3;

[0049] The tenth pin of the network transformer T1 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the first end of the fourth capacitor C4;

[0050] The second end of the first capacitor C1 is respectively connected to the second ends of the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 and grounded;

[0051] The second pin, third pin, fifth pin, sixth pin, eighth pin, ninth pin, eleventh pin, and twelfth pin of the network transformer T1 are all connected to the output end of the PoE device under test through the second network port;

[0052] The fifteenth pin of the network transformer T1 is respectively connected to the first end of the fifth resistor R5 and the input end of the PD chip protocol detection and control module, and the second end of the fifth resistor R5 is connected to the first end of the fifth capacitor C5;

[0053] The eighteenth pin of the network transformer T1 is respectively connected to the first end of the sixth resistor R6 and the input end of the PD chip protocol detection and control module, and the second end of the sixth resistor R6 is connected to the first end of the sixth capacitor C6;

[0054] The twenty-first pin of the network transformer T1 is respectively connected to the first end of the seventh resistor R7 and the input end of the PD chip protocol detection and control module, and the second end of the seventh resistor R7 is connected to the first end of the seventh capacitor C7;

[0055] The twenty-fourth pin of the network transformer T1 is respectively connected to the first end of the eighth resistor R8 and the input end of the PD chip protocol detection and control module, and the second end of the eighth resistor R8 is connected to the first end of the eighth capacitor C8;

[0056] The second terminal of the fifth capacitor C5 is respectively connected to the second terminals of the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 and grounded.

[0057] The thirteenth pin, fourteenth pin, sixteenth pin, seventeenth pin, nineteenth pin, twentieth pin, twenty-second pin, and twenty-third pin of the network transformer T1 are all connected to the output end of the PoE device under test through the first network port.

[0058] In the embodiment of the present invention, the signal separation module receives the signals output by the PoE device under test through the first network port and the second network port, and separates the signals into a POE power supply signal and a network signal through a network transformer T1. Both the first network port and the second network port are RJ45. The model of the network transformer T1 is TR-SG24719PT-G-4214259. The network transformer T1 inputs the POE power supply signal from the fifteenth pin, eighteenth pin, twenty-first pin, and twenty-fourth pin for the subsequent circuit processing. The second pin, third pin, fifth pin, sixth pin, eighth pin, ninth pin, eleventh pin, and twelfth pin of the network transformer T1 input the network signal for data communication, so as to ensure that the power supply and data transmission do not affect each other.

[0059] Since the powered device does not know whether the power supply device at the other end is powered in mode A or mode B, it must be compatible with these two modes. Whether the ports 1 and 2 are positive, or the ports 3 and 6 are positive, or even the 8 wires are powered, the polarity needs to be calibrated. Therefore, the PD chip protocol detection and control module includes a polarity calibration unit and a protocol detection unit.

[0060] The input end of the polarity calibration unit is respectively connected to the twenty-fourth pin of the network transformer T1, the twenty-first pin of the network transformer T1, the eighteenth pin of the network transformer T1, and the fifteenth pin of the network transformer T1.

[0061] The output end of the polarity calibration unit is connected to the input end of the protocol detection unit and the input end of the electrical parameter sampling module.

[0062] The output end of the protocol detection unit is connected to the input end of the load resistance module.

[0063] Most preferably, as Figure 4 shown, the polarity calibration unit for polarizing the POE power supply signal includes:

[0064] The first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5, the sixth diode D6, the seventh diode D7, and the eighth diode D8.

[0065] The first end of the first diode D1 is respectively connected to the second end of the second diode D2 and the twenty-fourth pin of the network transformer T1;

[0066] The first end of the third diode D3 is respectively connected to the second end of the fourth diode D4 and the twenty-first pin of the network transformer T1;

[0067] The first end of the fifth diode D5 is respectively connected to the second end of the sixth diode D6 and the eighteenth pin of the network transformer T1;

[0068] The first end of the seventh diode D7 is respectively connected to the second end of the eighth diode D8 and the fifteenth pin of the network transformer T1;

[0069] The second end of the first diode D1 is respectively connected to the second end of the third diode D3, the second end of the fifth diode D5, and the second end of the seventh diode D7 and is grounded;

[0070] The first end of the second diode D2 is respectively connected to the first end of the fourth diode D4, the first end of the sixth diode D6, and the first end of the eighth diode D8 and is connected to the input end of the protocol detection unit and the input end of the electrical parameter sampling module.

[0071] Most preferably, the polarity calibration unit further includes the twenty-eighth diode D28, the twenty-ninth diode D29, the thirtieth diode D30, and the thirty-first diode D31 for port lightning protection;

[0072] The first end of the twenty-eighth diode D28 is connected to the first end of the third diode D3;

[0073] The second end of the twenty-ninth diode D29 is connected to the first end of the seventh diode D7;

[0074] The first end of the thirtieth diode D30 is connected to the first end of the first diode D1;

[0075] The second end of the thirty-first diode D31 is connected to the first end of the fifth diode D5;

[0076] The second end of the twenty-eighth diode D28 is respectively connected to the first end of the twenty-ninth diode D29, the second end of the thirtieth diode D30, and the first end of the thirty-first diode D31 and is grounded.

[0077] In the embodiment of the present invention, the twenty-eighth diode D28, the twenty-ninth diode D29, the thirtieth diode D30, and the thirty-first diode D31 for port lightning protection in the polarity calibration unit support a common-mode voltage of ±6 KV and a differential-mode voltage of ±2 KV for lightning protection of the network port.

[0078] Most preferably, asFigure 5 As shown, the protocol detection unit for detecting and switching IEEE802.3af, IEEE802.3at, IEEE802.3bt PoE protocols and load output control includes:

[0079] A detection chip, a first varistor VDR1, a second varistor VDR2, a ninth diode D9, a tenth diode D10, an eleventh diode D11, a twelfth diode D12, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty - first resistor R21, a ninth capacitor C9, a tenth capacitor C10;

[0080] The first pin of the detection chip is respectively connected to the first end of the fourteenth resistor R14 and the second end of the fifteenth resistor R15. The second end of the fourteenth resistor R14 is respectively connected to the second end of the thirteenth resistor R13, the first end of the ninth capacitor C9, the first end of the eleventh resistor R11, the first end of the twelfth resistor R12, the first end of the first varistor VDR1, and the second end of the ninth diode D9 and is grounded. The second end of the first varistor VDR1 is grounded. The second end of the ninth resistor R9 is connected to the first end of the tenth resistor R10. The second end of the eleventh resistor R11 is connected to the first end of the twelfth resistor R12. The second end of the tenth resistor R10 is respectively connected to the second end of the twelfth resistor R12 and the first end of the tenth diode D10. The second end of the tenth diode D10 is connected to the second end of the sixteenth resistor R16 and the input end of the load resistance module;

[0081] The second pin of the detection chip is connected to the first end of the thirteenth resistor R13;

[0082] The third pin of the detection chip is connected to the first end of the fifteenth resistor R15;

[0083] The fourth pin of the detection chip is connected to the input end of the load resistance module;

[0084] The fifth pin of the detection chip is respectively connected to the sixth pin of the detection chip, the seventeenth pin of the detection chip, the second end of the ninth capacitor C9, the first end of the ninth diode D9, the first end of the second varistor VDR2, and the first end of the second diode D2. The second end of the second varistor VDR2 is grounded;

[0085] The seventh pin of the detection chip is respectively connected to the eighth pin of the detection chip, the second end of the tenth capacitor C10, and the second end of the sixteenth resistor R16;

[0086] The ninth pin of the detection chip is respectively connected to the first end of the tenth capacitor C10, the first end of the sixteenth resistor R16, and the first end of the seventeenth resistor R17. The second end of the seventeenth resistor R17 is connected to the first end of the eleventh diode D11, and the second end of the eleventh diode D11 is grounded;

[0087] The tenth pin of the detection chip is connected to the second end of the nineteenth resistor R19;

[0088] The eleventh pin of the detection chip is connected to the first end of the eighteenth resistor R18. The second end of the eighteenth resistor R18 is connected to the first end of the nineteenth resistor R19 and grounded;

[0089] The twelfth pin of the detection chip is connected to the input end of the load resistance module;

[0090] The thirteenth pin of the detection chip is connected to the first end of the twelfth diode D12. The second end of the twelfth diode D12 is respectively connected to the second end of the twenty-first resistor R21 and the first end of the second diode D2;

[0091] The fourteenth pin of the detection chip is connected to the first end of the twentieth resistor R20. The second end of the twentieth resistor R20 is connected to the first end of the twenty-first resistor R21.

[0092] In the embodiment of the present utility model, the detection chip adopts MAX5995A. This chip supports the IEEE802.3bt protocol. By selecting CLSA and CLSB through the first switch SW1, power detection of 88 different levels of CLASS1 is realized. The detection results are shown in Table 1 below:

[0093] Table 1

[0094] Power receiving level Power required by the power receiving equipment <![CDATA[R CLSA > <![CDATA[R CLSB > 0 12.95W 619 Turn on 1 3.84W 118 Turn on 2 6.49W 66.5 Turn on 3 12.95W 43.2 Turn on 4 25.5W 30.9 30.9 5 38.25W 30.9 619 6 51W 30.9 118 7 61W 30.9 66.5 8 71W 30.9 43.2

[0095] In the embodiment of the present utility model, the LED pin of the detection chip can be used to detect whether the detection chip is in the normal working mode or the sleep mode. The VDD pin is connected to the twelfth diode D10 through the thirteenth resistor R13, the ninth resistor R9, the tenth resistor R10, the eleventh resistor, and the twelfth resistor R12, which can display the working state of the load and can be used for troubleshooting.

[0096] Most preferably, as Figure 6 shown, the load resistance module for adjusting the load resistance to control the power of the load includes:

[0097] The twenty-second resistor R22, the twenty-third resistor R23, the twenty-fourth resistor R24, the twenty-fifth resistor R25, the twenty-sixth resistor R26, the twenty-seventh resistor R27, the twenty-eighth resistor R28, the twenty-ninth resistor R29, the thirtieth resistor R30, the thirty-first resistor R31, the thirty-second resistor R32, the thirty-third resistor R33, the thirty-fourth resistor R34, the thirty-fifth resistor R35, the thirty-sixth resistor R36, the thirty-seventh resistor R37, the thirty-eighth resistor R38, the thirty-ninth resistor R39, the fortieth resistor R40, the forty-first resistor R41, the forty-second resistor R42, the forty-third resistor R43, the forty-fourth resistor R44, the forty-fifth resistor R45, the forty-sixth resistor R46, the forty-seventh resistor R47, the forty-eighth resistor R48, the forty-ninth resistor R49, the fiftieth resistor R50, the fifty-first resistor R51, the fifty-second resistor R52, the fifty-third resistor R53, the fifty-fourth resistor R54, the fifty-fifth resistor R55, the fifty-sixth resistor R56, the fifty-seventh resistor R57, the fifty-eighth resistor R58, the fifty-ninth resistor R59, the sixtieth resistor R60, the sixty-first resistor R61, the sixty-second resistor R62, the sixty-third resistor R63, the sixty-fourth resistor R64, the sixty-fifth resistor R65, the sixty-sixth resistor R66;

[0098] The eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, the fourteenth capacitor C14, the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18;

[0099] The thirteenth diode D13, the fourteenth diode D14, the fifteenth diode D15, the sixteenth diode D16, the seventeenth diode D17, the eighteenth diode D18, the nineteenth diode D19, the twentieth diode D20, the twenty-first diode D21, the twenty-second diode D22;

[0100] The first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, the fourth MOS transistor Q4, the fifth MOS transistor Q5, the sixth MOS transistor Q6, the seventh MOS transistor Q7;

[0101] The first switch SW1;

[0102] The first end of the twenty-second resistor R22 is connected to the second end of the thirteenth diode D13 and grounded. The second end of the twenty-second resistor R22 is connected to the first end of the twenty-third resistor R23. The second end of the twenty-third resistor R23 is respectively connected to the second end of the fourteenth diode D14, the second end of the fifteenth diode D15, the first end of the twenty-fourth resistor R24, the first end of the eleventh capacitor C11, and the first signal transmission end of the control module. The first end of the fourteenth diode D14 is respectively connected to the first end of the fifteenth diode D15, the second end of the twenty-fourth resistor R24, the second end of the eleventh capacitor C11, and the eighth pin of the detection chip;

[0103] The source electrode of the first MOS transistor Q1 is respectively connected to the first end of the twenty-fifth resistor R25, the first end of the twelfth capacitor C12, the first end of the thirteenth capacitor C13, and the eighth pin of the detection chip. The gate electrode of the first MOS transistor Q1 is respectively connected to the second end of the twelfth capacitor C12, the second end of the twenty-fifth resistor R25, and the second end of the sixteenth diode D16. The drain electrode of the first MOS transistor Q1 is connected to the first end of the twenty-sixth resistor R26. The second end of the twenty-sixth resistor R26 is sequentially connected to the twenty-seventh resistor R27, the twenty-eighth resistor R28, the twenty-ninth resistor R29, and the thirtieth resistor R30;

[0104] The source electrode of the second MOS transistor Q2 is respectively connected to the first end of the thirty-first resistor R31, the first end of the thirteenth capacitor C13, and the first end of the fourteenth capacitor C14. The gate electrode of the second MOS transistor Q2 is respectively connected to the second end of the thirteenth capacitor C13, the second end of the thirty-first resistor R31, and the second end of the seventeenth diode D17. The drain electrode of the second MOS transistor Q2 is connected to the first end of the thirty-second resistor R32. The second end of the thirty-second resistor R32 is sequentially connected to the thirty-third resistor R33, the thirty-fourth resistor R34, the thirty-fifth resistor R35, and the thirty-sixth resistor R36;

[0105] The source electrode of the third MOS transistor Q3 is respectively connected to the first end of the thirty-seventh resistor R37 and the first end of the fourteenth capacitor C14. The gate electrode of the third MOS transistor Q3 is respectively connected to the second end of the fourteenth capacitor C14, the second end of the thirty-seventh resistor R37, and the second end of the eighteenth diode D18. The drain electrode of the third MOS transistor Q3 is connected to the first end of the thirty-eighth resistor R38. The second end of the thirty-eighth resistor R38 is sequentially connected to the thirty-ninth resistor R39, the fortieth resistor R40, the forty-first resistor R41, and the forty-second resistor R42;

[0106] The second end of the thirtieth resistor R30 is connected to the second end of the thirty-sixth resistor R36 and the second end of the forty-second resistor R42 and grounded;

[0107] The source of the fourth MOS transistor Q4 is respectively connected to the first end of the forty-third resistor R43, the first end of the fifteenth capacitor C15, the first end of the seventeenth capacitor C17, and the eighth pin of the detection chip. The gate of the fourth MOS transistor Q4 is respectively connected to the second end of the fifteenth capacitor C15, the second end of the forty-third resistor R43, and the second end of the nineteenth diode D19. The drain of the fourth MOS transistor Q4 is connected to the first end of the forty-fourth resistor R44, and the second end of the forty-fourth resistor R44 is sequentially connected to the forty-fifth resistor R45, the forty-sixth resistor R46, the forty-seventh resistor R47, and the forty-eighth resistor R48;

[0108] The source of the fifth MOS transistor Q5 is respectively connected to the first end of the forty-ninth resistor R49, the first end of the sixteenth capacitor C16, and the first end of the seventeenth capacitor C17. The gate of the fifth MOS transistor Q5 is respectively connected to the second end of the sixteenth capacitor C16, the second end of the forty-ninth resistor R49, and the second end of the twenty-second diode D20. The drain of the fifth MOS transistor Q5 is connected to the first end of the fiftieth resistor R50, and the second end of the fiftieth resistor R50 is sequentially connected to the fifty-first resistor R51, the fifty-second resistor R52, the fifty-third resistor R53, and the fifty-fourth resistor R54;

[0109] The source of the sixth MOS transistor Q6 is respectively connected to the first end of the fifty-fifth resistor R55, the first end of the seventeenth capacitor C17, and the first end of the eighteenth capacitor C18. The gate of the sixth MOS transistor Q6 is respectively connected to the second end of the seventeenth capacitor C17, the second end of the fifty-fifth resistor R55, and the second end of the twenty-first diode D21. The drain of the sixth MOS transistor Q6 is connected to the first end of the fifty-sixth resistor R56, and the second end of the fifty-sixth resistor R56 is sequentially connected to the fifty-seventh resistor R57, the fifty-eighth resistor R58, the fifty-ninth resistor R59, and the sixtieth resistor R60;

[0110] The source of the seventh MOS transistor Q7 is respectively connected to the first end of the sixty-first resistor R61 and the first end of the eighteenth capacitor C18. The gate of the seventh MOS transistor Q7 is respectively connected to the second end of the eighteenth capacitor C18, the second end of the sixty-first resistor R61, and the second end of the twenty-second diode D22. The drain of the seventh MOS transistor Q7 is connected to the first end of the sixty-second resistor R62;

[0111] The second ends of the forty-eighth resistor R48, the fifty-fourth resistor R54, the sixtieth resistor R60, and the sixty-second resistor R62 are connected and grounded;

[0112] The first ends of the sixteenth diode D16, the seventeenth diode D17, the eighteenth diode D18, the nineteenth diode D19, the twentieth diode D20, the twenty-first diode D21, and the twenty-second diode D22 are all connected to the first signal transmission end of the control module;

[0113] The first pin of the first switch SW1 is connected to the first end of the sixty-third resistor R63. The second ends of the sixty-third resistor R63 and the sixty-fourth resistor R64 are both connected to the fourth pin of the detection chip. The second pin of the first switch SW1 is respectively connected to the first end of the sixty-fourth resistor R64 and the fourth pin of the first switch SW1. The third pin and the sixth pin of the first switch SW1 are both connected to the second end of the twenty-first resistor R21. The fifth pin of the first switch SW1 is connected to the first end of the sixty-sixth resistor R66. The seventh pin of the first switch SW1 is connected to the first end of the sixty-fifth resistor R65. The second ends of the sixty-fifth resistor R65 and the sixty-sixth resistor R66 are both connected to the twelfth pin of the detection chip.

[0114] In the embodiment of the present utility model, the load resistance module is mainly composed of load resistors. Its working principle is to select the PoE protocol through the first switch SW1, and then the control module controls the on-off of the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, the fourth MOS transistor Q4, the fifth MOS transistor Q5, the sixth MOS transistor Q6, and the seventh MOS transistor Q7 to control the size of the load resistance. Among them, there are a total of 7 MOS transistor switches, namely G1-G7. G1-G6 all control a power of 15W, and G7 controls a fine-tuning power of 1-15W, so as to accurately adjust the power and realize the adjustment of any power between 1-90W. Considering that the load resistance generates a large amount of heat, a heat dissipation module is set. When multiple devices are combined and installed in a chassis, power needs to be supplied to a high-power cooling fan. At this time, the load resistors of these two paths of G1 and G2 are removed, and the fan is used to replace and consume energy. The cooling fan is turned on through the heat dissipation module for heat dissipation to ensure the reliability and stability of the device and enhance the service life of the device.

[0115] Most preferably, as Figure 6 shown, the heat dissipation module includes:

[0116] The first socket U1, the second socket U2, the third socket U3, the fourth socket U4, the twenty-second capacitor C22, the twenty-third capacitor C23, the twenty-fourth capacitor C24, and the twenty-fifth capacitor C25;

[0117] The first pin of the first socket U1, the first pin of the second socket U2, the first end of the twenty-second capacitor C22, and the first end of the twenty-third capacitor C23 are all connected to the drain of the first MOS transistor Q1;

[0118] The second pin of the first socket U1 is respectively connected to the second pin of the second socket U2, the second end of the twenty-second capacitor C22, and the second end of the twenty-third capacitor C23, and is grounded;

[0119] The first pin of the third socket U3, the first pin of the fourth socket U4, the first end of the twenty-fourth capacitor C24, and the first end of the twenty-fifth capacitor C25 are all connected to the drain of the second MOS transistor Q2;

[0120] The second pin of the third socket U3 is respectively connected to the second pin of the fourth socket U4, the second end of the twenty-fourth capacitor C24, and the second end of the twenty-fifth capacitor C25, and is grounded.

[0121] Most preferably, as Figure 7 shown, the electrical parameter sampling module for converting the voltage and current collected in the form of analog signals into voltage and current in the form of digital signals and providing power to the control module includes:

[0122] A sampling chip, a sixty-seventh resistor R67, a sixty-eighth resistor R68, a sixty-ninth resistor R69, a seventieth resistor R70, and a seventy-second resistor R72;

[0123] The first end of the sixty-seventh resistor R67 is respectively connected to the eighth pin of the detection chip and the sampling chip. The second end of the sixty-seventh resistor R67 is connected to the first end of the sixty-eighth resistor R68. The second end of the sixty-eighth resistor R68 is respectively connected to the first end of the seventieth resistor R70, the pin of the sampling chip, and is grounded;

[0124] The first end of the sixty-ninth resistor R69 is connected to the pin of the sampling chip and is grounded. The second end of the sixty-ninth resistor R69 is connected to the first end of the seventy-second resistor R72. The second end of the seventy-second resistor R72 is respectively connected to the second end of the seventieth resistor R70 and the pin of the sampling chip.

[0125] Some pins of the sampling chip are connected to the input end of the control module.

[0126] In the embodiment of the present invention, the model of the sampling chip is ACS37800 chip.

[0127] Most preferably, the human-computer interaction module includes:

[0128] A key unit composed of a first key K1, a second key K2, a third key K3, a fourth key K4, a nineteenth capacitor C19, a twentieth capacitor C20, a twenty-first capacitor C21, a first crystal oscillator Y1, and a seventy-first resistor R71, for manually controlling, adjusting the power size, and setting the mode selection;

[0129] A display unit composed of a liquid crystal display screen, the seventy-third resistor R73, and the seventy-fourth resistor R74 is used to display the detected voltage, current, and power;

[0130] The third pin of the first button K1, the third pin of the second button K2, and the third pin of the third button K3 are all connected to the second signal transmission end of the control module;

[0131] The second pin of the first button K1, the second pin of the second button K2, and the second pin of the third button K3 are all connected to the fourth pin of the fourth button K4 and the second signal transmission end of the control module through the seventy-first resistor R71;

[0132] The first pin of the third button K3 is respectively connected to the first end of the twentieth capacitor C20, the first end of the twenty-first capacitor C21, and the second signal transmission end of the control module. The second end of the twentieth capacitor C20 is respectively connected to the first end of the first crystal oscillator Y1 and the second signal transmission end of the control module. The second end of the twenty-first capacitor C21 is respectively connected to the second end of the first crystal oscillator Y1 and the second signal transmission end of the control module;

[0133] The first pin of the fourth button K4 is connected to the first end of the nineteenth capacitor C19. The fourth pin of the fourth button K4 is respectively connected to the second end of the nineteenth capacitor C19, the second end of the seventy-first resistor R71, and the second signal transmission end of the control module;

[0134] The first pin of the liquid crystal display screen is connected to the second end of the seventy-third resistor R73 and grounded. The second pin of the liquid crystal display screen is connected to the first end of the seventy-fourth resistor R74. The third pin of the liquid crystal display screen is respectively connected to the first end of the seventy-third resistor R73 and the second end of the seventy-fourth resistor R74. The fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin, the ninth pin, the tenth pin, the eleventh pin, the twelfth pin, the thirteenth pin, the fourteenth pin, and the fifteenth pin of the liquid crystal display screen are all connected to the second signal transmission end of the control module, and the sixteenth pin of the liquid crystal display screen is grounded.

[0135] In the embodiment of the present invention, the button unit can set the load power. Press the first button K1, and the power can be adjusted steplessly from 1 to 15W by manually adjusting the sixty-second resistor R62. Press the second button K2 to increase the power by 15W. Press the third button K3 to reduce the power by 15W. The maximum power adjustment supported is 90W. The fourth button K4 is used for reset. The model of the liquid crystal display screen is the 16-pin LCD1602.

[0136] In the embodiment of the present utility model, the user inputs the received power control signal through the human-machine interaction module. Through program operation and processing, the received power control signal is given to the MOS transistor. The control module inputs a small signal of 3.3V, while the voltage of the load resistance module is a large signal of about 50V. Therefore, the MOS transistor needs to be used as a switch to control the large signal with the small signal, and the on / off of 7 MOS transistors is controlled. The power of each path is 15W. When the MOS transistor is turned on, the load resistance will work and the power will increase, so as to control the power of the PD load. Since a large amount of heat will be generated when the load resistance module works, a high-power cooling fan is required for heat dissipation at this time. The high-power cooling fan is controlled by controlling the MOS transistors Q1 and Q2 to ensure the reliability and stability of the PD load and enhance the service life of the PD load.

[0137] Suppose it is necessary to design a device with a POE power output of 370W. Then it is necessary to adjust the load power to about 370W, and then press the button K1 to finely adjust the sixty-second resistor R62. This mode can be finely adjusted from 1W to 15W. When the load power is adjusted to 370W and can supply power stably all the time, but the PD load will power off when it is adjusted to 371W, then the measured 370W is the maximum output power. In this way, the maximum output power of the power supply device can be accurately measured.

[0138] In the embodiment of the present utility model, the single-chip microcomputer control chip STC89C52 is adopted by the control module. This chip is a low-power, high-performance 51-core CMOS 8-bit single-chip microcomputer with an in-circuit programming function, and no longer requires a 12V VPP programming high voltage like STC89C51. It is simple to use and very inexpensive. Using the single-chip microcomputer control chip to realize data calculation belongs to the function possessed by the single-chip microcomputer control chip itself. The embodiment of the present utility model does not involve the improvement of software and algorithms. Therefore, the specific process of using the single-chip microcomputer control chip for data calculation also belongs to the prior art, and the embodiment of the present utility model will not elaborate on it one by one.

[0139] The embodiment of the utility model includes a signal separation module, a PD chip protocol detection and control module, an electrical parameter sampling module, a control module, a human-computer interaction module, a load resistance module, and a heat dissipation module. Compared with the prior art, the embodiment of the utility model uses the signal separation module to separately extract the power receiving signal of the PoE device to be measured, detects the PoE protocol through the PD chip protocol detection and control module and outputs the PoE voltage to the load resistance module. The electrical parameter sampling module collects the voltage and current values of the power receiving signal by connecting with the PD chip protocol detection and control module and inputs them to the control module for conversion. The control module outputs a parameter display control signal to the human-computer interaction module to display the port power of the POE device. When measuring the overall power of the POE device, the user sends a power receiving control signal to the control module through the human-computer interaction module. The control module outputs a switch signal for adjusting the on / off of the MOS tube to the load resistance module to supply power to the heat dissipation module to turn on the high-power fan. The control module sends a power receiving power control module to the load resistance module to measure the maximum overall power of the PoE device by adjusting the power of the load resistance module, ensuring the reliability and stability of the tester and enhancing the service life of the tester.

[0140] The above is the preferred embodiment of the utility model. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present utility model, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present utility model.

Claims

1. A visual intelligent PD load tester, characterized in that Including: A signal separation module, a PD chip protocol detection and control module, an electrical parameter sampling module, a control module, a human-machine interaction module, a load resistance module, and a heat dissipation module; The input end of the signal separation module is connected to the output end of the PoE device to be tested, and the output end of the signal separation module is connected to the input end of the PD chip protocol detection and control module; The first output end of the PD chip protocol detection and control module is connected to the input end of the electrical parameter sampling module, and the second output end of the PD chip protocol detection and control module is connected to the input end of the load resistance module; The output end of the electrical parameter sampling module is connected to the input end of the control module; The output end of the load resistance module is connected to the input end of the heat dissipation module, and the output end of the heat dissipation module is connected to the input end of a high-power heat dissipation fan; The signal transmission end of the load resistance module is connected to the first signal transmission end of the control module; The signal transmission end of the human-machine interaction module is connected to the second signal transmission end of the control module; The signal output by the PoE device to be tested is input to the signal separation module, and the signal separation module outputs a powered signal to the PD chip protocol detection and control module and the electrical parameter sampling module; The voltage and current values of the powered signal collected by the electrical parameter sampling module are input to the control module, and the control module outputs a parameter display control signal to the human-machine interaction module; The human-machine interaction module outputs the received power control signal to the control module; The control module outputs the power control signal to the load resistance module to energize the heat dissipation module and the high-power heat dissipation fan.

2. The visualized intelligent PD load tester according to claim 1, wherein The signal separation module includes: A network transformer, a first network interface, a second network interface, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor; The first pin of the network transformer is connected to the first end of the first resistor, and the second end of the first resistor is connected to the first end of the first capacitor; The fourth pin of the network transformer is connected to the first end of the second resistor, and the second end of the second resistor is connected to the first end of the second capacitor; The seventh pin of the network transformer is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first end of the third capacitor; The tenth pin of the network transformer is connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to the first end of the fourth capacitor; The second end of the first capacitor is respectively connected to the second ends of the second capacitor, the third capacitor, and the fourth capacitor and grounded; The second pin, third pin, fifth pin, sixth pin, eighth pin, ninth pin, eleventh pin, and twelfth pin of the network transformer are all connected to the second network interface; The fifteenth pin of the network transformer is respectively connected to the first end of the fifth resistor and the input end of the PD chip protocol detection and control module. The second end of the fifth resistor is connected to the first end of the fifth capacitor; The eighteenth pin of the network transformer is respectively connected to the first end of the sixth resistor and the input end of the PD chip protocol detection and control module. The second end of the sixth resistor is connected to the first end of the sixth capacitor; The twenty - first pin of the network transformer is respectively connected to the first end of the seventh resistor and the input end of the PD chip protocol detection and control module. The second end of the seventh resistor is connected to the first end of the seventh capacitor; The twenty - fourth pin of the network transformer is respectively connected to the first end of the eighth resistor and the input end of the PD chip protocol detection and control module. The second end of the eighth resistor is connected to the first end of the eighth capacitor; The second end of the fifth capacitor is connected to the second ends of the sixth capacitor, the seventh capacitor, and the eighth capacitor and grounded; The thirteenth pin, fourteenth pin, sixteenth pin, seventeenth pin, nineteenth pin, twentieth pin, twenty - second pin, and twenty - third pin of the network transformer are all connected to the output end of the PoE device under test through the first network port.

3. The visualized intelligent PD load tester according to claim 2, characterized in that, The PD chip protocol detection and control module includes a polarity calibration unit and a protocol detection unit; The input end of the polarity calibration unit is respectively connected to the twenty - fourth pin of the network transformer, the twenty - first pin of the network transformer, the eighteenth pin of the network transformer, and the fifteenth pin of the network transformer; The output end of the polarity calibration unit is connected to the input end of the protocol detection unit and the input end of the electrical parameter sampling module; The output end of the protocol detection unit is connected to the input end of the load resistance module.

4. The visualized intelligent PD load tester according to claim 3, wherein, The polarity calibration unit includes: The first diode, the second diode, the third diode, the fourth diode, the fifth diode, the sixth diode, the seventh diode, and the eighth diode; The first end of the first diode is respectively connected to the second end of the second diode and the twenty - fourth pin of the network transformer; The first end of the third diode is respectively connected to the second end of the fourth diode and the twenty - first pin of the network transformer; The first end of the fifth diode is respectively connected to the second end of the sixth diode and the eighteenth pin of the network transformer; The first end of the seventh diode is respectively connected to the second end of the eighth diode and the fifteenth pin of the network transformer; The second end of the first diode is connected to the second ends of the third diode, the fifth diode, and the seventh diode and grounded; The first end of the second diode is connected to the first ends of the fourth diode, the sixth diode, and the eighth diode and is connected to the input end of the protocol detection unit and the input end of the electrical parameter sampling module.

5. The visualized intelligent PD load tester according to claim 4, wherein The protocol detection unit includes: Detection chip, first varistor, second varistor, ninth diode, twelfth diode, eleventh diode, twelfth diode, ninth resistor, tenth resistor, eleventh resistor, twelfth resistor, thirteenth resistor, fourteenth resistor, fifteenth resistor, sixteenth resistor, seventeenth resistor, eighteenth resistor, nineteenth resistor, twentieth resistor, twenty-first resistor, ninth capacitor, tenth capacitor; The first pin of the detection chip is respectively connected to the first end of the fourteenth resistor and the second end of the fifteenth resistor. The second end of the fourteenth resistor is respectively connected to the second end of the thirteenth resistor, the first end of the ninth capacitor, the first end of the eleventh resistor, the first end of the twelfth resistor, the first end of the first varistor, and the second end of the ninth diode and is grounded. The second end of the first varistor is grounded. The second end of the ninth resistor is connected to the first end of the tenth resistor. The second end of the eleventh resistor is connected to the first end of the twelfth resistor. The second end of the tenth resistor is respectively connected to the second end of the twelfth resistor and the first end of the twelfth diode. The second end of the twelfth diode is connected to the second end of the sixteenth resistor and the input end of the load resistor module; The second pin of the detection chip is connected to the first end of the thirteenth resistor; The third pin of the detection chip is connected to the first end of the fifteenth resistor; The fourth pin of the detection chip is connected to the input end of the load resistor module; The fifth pin of the detection chip is respectively connected to the sixth pin of the detection chip, the seventeenth pin of the detection chip, the second end of the ninth capacitor, the first end of the ninth diode, the first end of the second varistor, and the first end of the second diode. The second end of the second varistor is grounded; The seventh pin of the detection chip is respectively connected to the eighth pin of the detection chip, the second end of the tenth capacitor, and the second end of the sixteenth resistor; The ninth pin of the detection chip is respectively connected to the first end of the tenth capacitor, the first end of the sixteenth resistor, and the first end of the seventeenth resistor. The second end of the seventeenth resistor is connected to the first end of the eleventh diode. The second end of the eleventh diode is grounded; The tenth pin of the detection chip is connected to the second end of the nineteenth resistor; The eleventh pin of the detection chip is connected to the first end of the eighteenth resistor. The second end of the eighteenth resistor is connected to the first end of the nineteenth resistor and is grounded; The twelfth pin of the detection chip is connected to the input end of the load resistor module; The thirteenth pin of the detection chip is connected to the first end of the twelfth diode. The second end of the twelfth diode is respectively connected to the second end of the twenty-first resistor and the first end of the second diode; The fourteenth pin of the detection chip is connected to the first end of the twentieth resistor. The second end of the twentieth resistor is connected to the first end of the twenty-first resistor.

6. The visualized intelligent PD load tester according to claim 5, wherein The load resistor module includes: The twenty-second resistor, the twenty-third resistor, the twenty-fourth resistor, the twenty-fifth resistor, the twenty-sixth resistor, the twenty-seventh resistor, the twenty-eighth resistor, the twenty-ninth resistor, the thirtieth resistor, the thirty-first resistor, the thirty-second resistor, the thirty-third resistor, the thirty-fourth resistor, the thirty-fifth resistor, the thirty-sixth resistor, the thirty-seventh resistor, the thirty-eighth resistor, the thirty-ninth resistor, the fortieth resistor, the forty-first resistor, the forty-second resistor, the forty-third resistor, the forty-fourth resistor, the forty-fifth resistor, the forty-sixth resistor, the forty-seventh resistor, the forty-eighth resistor, the forty-ninth resistor, the fiftieth resistor, the fifty-first resistor, the fifty-second resistor, the fifty-third resistor, the fifty-fourth resistor, the fifty-fifth resistor, the fifty-sixth resistor, the fifty-seventh resistor, the fifty-eighth resistor, the fifty-ninth resistor, the sixtieth resistor, the sixty-first resistor, the sixty-second resistor, the sixty-third resistor, the sixty-fourth resistor, the sixty-fifth resistor, the sixty-sixth resistor; The eleventh capacitor, the twelfth capacitor, the thirteenth capacitor, the fourteenth capacitor, the fifteenth capacitor, the sixteenth capacitor, the seventeenth capacitor, the eighteenth capacitor; The thirteenth diode, the fourteenth diode, the fifteenth diode, the sixteenth diode, the seventeenth diode, the eighteenth diode, the nineteenth diode, the twentieth diode, the twenty-first diode, the twenty-second diode; The first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor; The first switch; The first end of the twenty-second resistor is connected to the second end of the thirteenth diode and grounded. The second end of the twenty-second resistor is connected to the first end of the twenty-third resistor. The second end of the twenty-third resistor is respectively connected to the second end of the fourteenth diode, the second end of the fifteenth diode, the first end of the twenty-fourth resistor, the first end of the eleventh capacitor, and the first signal transmission end of the control module. The first end of the fourteenth diode is respectively connected to the first end of the fifteenth diode, the second end of the twenty-fourth resistor, the second end of the eleventh capacitor, and the eighth pin of the detection chip; The source electrode of the first MOS transistor is respectively connected to the first end of the twenty-fifth resistor, the first end of the twelfth capacitor, the first end of the thirteenth capacitor, and the eighth pin of the detection chip. The gate electrode of the first MOS transistor is respectively connected to the second end of the twelfth capacitor, the second end of the twenty-fifth resistor, and the second end of the sixteenth diode. The drain electrode of the first MOS transistor is connected to the first end of the twenty-sixth resistor. The second end of the twenty-sixth resistor is sequentially connected to the twenty-seventh resistor, the twenty-eighth resistor, the twenty-ninth resistor, and the thirtieth resistor; The source of the second MOS transistor is respectively connected to the first end of the thirty-first resistor, the first end of the thirteenth capacitor, and the first end of the fourteenth capacitor. The gate of the second MOS transistor is respectively connected to the second end of the thirteenth capacitor, the second end of the thirty-first resistor, and the second end of the seventeenth diode. The drain of the second MOS transistor is connected to the first end of the thirty-second resistor, and the second end of the thirty-second resistor is sequentially connected to the thirty-third resistor, the thirty-fourth resistor, the thirty-fifth resistor, and the thirty-sixth resistor; The source of the third MOS transistor is respectively connected to the first end of the thirty-seventh resistor and the first end of the fourteenth capacitor. The gate of the third MOS transistor is respectively connected to the second end of the fourteenth capacitor, the second end of the thirty-seventh resistor, and the second end of the eighteenth diode. The drain of the third MOS transistor is connected to the first end of the thirty-eighth resistor, and the second end of the thirty-eighth resistor is sequentially connected to the thirty-ninth resistor, the fortieth resistor, the forty-first resistor, and the forty-second resistor; The second end of the thirtieth resistor is connected to the second ends of the thirty-sixth resistor and the forty-second resistor and grounded; The source of the fourth MOS transistor is respectively connected to the first end of the forty-third resistor, the first end of the fifteenth capacitor, the first end of the seventeenth capacitor, and the eighth pin of the detection chip. The gate of the fourth MOS transistor is respectively connected to the second end of the fifteenth capacitor, the second end of the forty-third resistor, and the second end of the nineteenth diode. The drain of the fourth MOS transistor is connected to the first end of the forty-fourth resistor, and the second end of the forty-fourth resistor is sequentially connected to the forty-fifth resistor, the forty-sixth resistor, the forty-seventh resistor, and the forty-eighth resistor; The source of the fifth MOS transistor is respectively connected to the first end of the forty-ninth resistor, the first end of the sixteenth capacitor, and the first end of the seventeenth capacitor. The gate of the fifth MOS transistor is respectively connected to the second end of the sixteenth capacitor, the second end of the forty-ninth resistor, and the second end of the twenty-second diode. The drain of the fifth MOS transistor is connected to the first end of the fiftieth resistor, and the second end of the fiftieth resistor is sequentially connected to the fifty-first resistor, the fifty-second resistor, the fifty-third resistor, and the fifty-fourth resistor; The source of the sixth MOS transistor is respectively connected to the first end of the fifty-fifth resistor, the first end of the seventeenth capacitor, and the first end of the eighteenth capacitor. The gate of the sixth MOS transistor is respectively connected to the second end of the seventeenth capacitor, the second end of the fifty-fifth resistor, and the second end of the twenty-first diode. The drain of the sixth MOS transistor is connected to the first end of the fifty-sixth resistor, and the second end of the fifty-sixth resistor is sequentially connected to the fifty-seventh resistor, the fifty-eighth resistor, the fifty-ninth resistor, and the sixtieth resistor; The source of the seventh MOS transistor is respectively connected to the first end of the sixty-first resistor and the first end of the eighteenth capacitor. The gate of the seventh MOS transistor is respectively connected to the second end of the eighteenth capacitor, the second end of the sixty-first resistor, and the second end of the twenty-second diode. The drain of the seventh MOS transistor is connected to the first end of the sixty-second resistor; The second ends of the forty-eighth resistor, the fifty-fourth resistor, the sixtieth resistor, and the sixty-second resistor are connected and grounded; The first ends of the sixteenth diode, the seventeenth diode, the eighteenth diode, the nineteenth diode, the twentieth diode, the twenty-first diode, and the twenty-second diode are all connected to the first signal transmission end of the control module; The first pin of the first switch is connected to the first end of the sixty-third resistor. The second ends of the sixty-third resistor and the sixty-fourth resistor are both connected to the fourth pin of the detection chip. The second pin of the first switch is respectively connected to the first end of the sixty-fourth resistor and the fourth pin of the first switch. The third pin and the sixth pin of the first switch are both connected to the second end of the twenty-first resistor. The fifth pin of the first switch is connected to the first end of the sixty-sixth resistor. The seventh pin of the first switch is connected to the first end of the sixty-fifth resistor. The second ends of the sixty-fifth resistor and the sixty-sixth resistor are both connected to the twelfth pin of the detection chip.

7. The visualized intelligent PD load tester according to claim 6, characterized in that The electrical parameter sampling module includes: A sampling chip, a sixty-seventh resistor, a sixty-eighth resistor, a sixty-ninth resistor, a seventieth resistor, and a seventy-second resistor; The first end of the sixty-seventh resistor is respectively connected to the eighth pin of the detection chip and the sampling chip. The second end of the sixty-seventh resistor is connected to the first end of the sixty-eighth resistor. The second end of the sixty-eighth resistor is respectively connected to the first end of the seventieth resistor and the pin of the sampling chip and grounded; The first end of the sixty-ninth resistor is connected to the pin of the sampling chip and grounded. The second end of the sixty-ninth resistor is connected to the first end of the seventy-second resistor. The second end of the seventy-second resistor is respectively connected to the second end of the seventieth resistor and the pin of the sampling chip; Some pins of the sampling chip are connected to the input end of the control module.

8. The visualized intelligent PD load tester according to claim 7, characterized in that, The human-computer interaction module includes: A key unit composed of a first key, a second key, a third key, a fourth key, a nineteenth capacitor, a twentieth capacitor, a twenty-first capacitor, a first crystal oscillator, and a seventy-first resistor; A display unit composed of a liquid crystal display screen, a seventy-third resistor, and a seventy-fourth resistor; The third pins of the first key, the second key, and the third key are all connected to the second signal transmission end of the control module; The second pin of the first button, the second pin of the second button, and the second pin of the third button are all connected to the fourth pin of the fourth button and the second signal transmission end of the control module through the seventy-first resistor; The first pin of the third button is respectively connected to the first end of the twentieth capacitor, the first end of the twenty-first capacitor, and the second signal transmission end of the control module. The second end of the twentieth capacitor is respectively connected to the first end of the first crystal oscillator and the second signal transmission end of the control module. The second end of the twenty-first capacitor is respectively connected to the second end of the first crystal oscillator and the second signal transmission end of the control module; The first pin of the fourth button is connected to the first end of the nineteenth capacitor. The fourth pin of the fourth button is respectively connected to the second end of the nineteenth capacitor, the second end of the seventy-first resistor, and the second signal transmission end of the control module; The first pin of the liquid crystal display screen is connected to the second end of the seventy-third resistor and grounded. The second pin of the liquid crystal display screen is connected to the first end of the seventy-fourth resistor. The third pin of the liquid crystal display screen is respectively connected to the first end of the seventy-third resistor and the second end of the seventy-fourth resistor. The fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin, the ninth pin, the tenth pin, the eleventh pin, the twelfth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin of the liquid crystal display screen are all connected to the second signal transmission end of the control module, and the sixteenth pin of the liquid crystal display screen is grounded.

9. The visualized intelligent PD load tester according to claim 8, characterized in that, The polarity calibration unit includes the twenty-eighth diode, the twenty-ninth diode, the thirty-second diode, and the thirty-first diode; The first end of the twenty-eighth diode is connected to the first end of the third diode; The second end of the twenty-ninth diode is connected to the first end of the seventh diode; The first end of the thirty-second diode is connected to the first end of the first diode; The second end of the thirty-first diode is connected to the first end of the fifth diode; The second end of the twenty-eighth diode is respectively connected to the first end of the twenty-ninth diode, the second end of the thirty-second diode, and the first end of the thirty-first diode and grounded.

10. The visualized intelligent PD load tester according to claim 9, characterized in that, The heat dissipation module includes: The first socket, the second socket, the third socket, the fourth socket, the twenty-second capacitor, the twenty-third capacitor, the twenty-fourth capacitor, and the twenty-fifth capacitor; The first pin of the first socket, the first pin of the second socket, the first end of the twenty-second capacitor, and the first end of the twenty-third capacitor are all connected to the drain of the first MOS transistor; The second pin of the first socket is respectively connected to the second pin of the second socket, the second end of the twenty-second capacitor, and the second end of the twenty-third capacitor and grounded; The first pin of the third socket, the first pin of the fourth socket, the first terminal of the twenty-fourth capacitor, and the first terminal of the twenty-fifth capacitor are all connected to the drain of the second MOS transistor; The second pin of the third socket is respectively connected to the second pin of the fourth socket, the second terminal of the twenty-fourth capacitor, and the second terminal of the twenty-fifth capacitor and is grounded.

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