Laminated packaging structure and chip
Through the design of the stacked packaging structure and re-wiring layer, the problem of excessive volume when domestic DDR4 memory is expanded to large capacity is solved, and the manufacturing of small-sized large-capacity memory is achieved, and performance and efficiency improvements are achieved.
Patent Information
- Application Number
- CN202421497548.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2034-06-27
AI Technical Summary
The capacity of the existing domestic DDR4 memory is small, and directly expanding to large capacity will lead to excessive volume, making it difficult to meet the market's demand for large-capacity and small-size memory.
Using a stacked package structure, the first memory wafer is fixed on the circuit substrate, the second memory wafer is stacked on the first memory wafer, and electrical connection is achieved through the re-wiring layer. Combining the bonding layer and bonding wire of different thicknesses, the circuit substrate area and the number of lead-out ends are reduced, and the coordinated work of the memory wafer is realized.
It realizes the acquisition of large-capacity and small-sized memory chips without increasing the size of the package structure. The performance is similar to the original DDR4 memory, and reduces power consumption and improves operating efficiency.
Smart Images
Figure CN223125206U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a stacked packaging structure and a chip. Background Art
[0002] At present, the capacity specifications of the mainstream domestic DDR (Double Data Rate) 4 memories are relatively small. For example, the domestic DDR4 with a capacity of 8 Gb. However, there is a relatively strong demand in the market for domestic DDR4 memories with large capacity and small size. Directly obtaining a large-capacity domestic DDR4 based on the existing domestic DDR4 memories will result in a relatively large volume and size of the obtained large-capacity domestic DDR4.
[0003] Therefore, how to propose a chip packaging solution that can utilize the existing small-capacity domestic DDR4 memories to obtain large-capacity and small-size domestic DDR4 memories is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Utility Model
[0004] Aiming at the problems existing in the prior art, the utility model provides a stacked packaging structure and a chip.
[0005] The utility model provides a stacked packaging structure, including a circuit substrate, a first memory wafer and a second memory wafer; the first side of the first memory wafer is fixed on the first surface of the circuit substrate, and the second memory wafer is fixed on the second side of the first memory wafer; the first side and the second side of the first memory wafer are opposite sides; the circuit substrate is provided with a redistribution layer, and the pins of the first memory wafer and the pins of the second memory wafer are respectively electrically connected to the redistribution layer, and the redistribution layer is used to electrically connect the first memory wafer and the second memory wafer.
[0006] According to a stacked packaging structure provided by the utility model, a plurality of functional pads are arranged on the first surface of the circuit substrate, and each functional pad is respectively electrically connected to the redistribution layer; the pins of the first memory wafer and the pins of the second memory wafer are respectively electrically connected to the corresponding functional pads.
[0007] According to a stacked packaging structure provided by the utility model, a first bonding wire is arranged between the pin of the first memory wafer and the corresponding functional pad; a second bonding wire is arranged between the pin of the second memory wafer and the corresponding functional pad.
[0008] According to a stacked packaging structure provided by the present utility model, a first bonding layer is provided between the first side of the first memory wafer and the first surface of the circuit substrate, and a second bonding layer is provided between the second memory wafer and the second side of the first memory wafer; a first bonding wire connected to the pins of the first memory wafer is at least partially located in the second bonding layer.
[0009] According to a stacked packaging structure provided by the present utility model, at least one functional pad is electrically connected to both the first bonding wire and the second bonding wire.
[0010] According to a stacked packaging structure provided by the present utility model, the thickness of the first bonding layer is less than the thickness of the second bonding layer.
[0011] According to a stacked packaging structure provided by the present utility model, the first bonding layer is a wafer bonding film, and the second bonding layer is a wire covering film.
[0012] According to a stacked packaging structure provided by the present utility model, substrate pads are provided on the second surface of the circuit substrate, and solder balls are provided on the substrate pads.
[0013] According to a stacked packaging structure provided by the present utility model, the pins of the first memory wafer connected to the bonding wires are located on the surface of the first memory wafer away from the circuit substrate; the pins of the second memory wafer connected to the bonding wires are located on the surface of the second memory wafer away from the circuit substrate.
[0014] The present utility model also provides a chip, including the stacked packaging structure as described in any one of the above; and a housing for accommodating the stacked packaging structure.
[0015] The stacked packaging structure and the chip provided by the present utility model can reduce the area of the circuit substrate occupied by the first memory wafer and the second memory wafer by fixing the first memory wafer on the first surface of the circuit substrate and fixing the second memory wafer on the first memory wafer, thereby reducing the number of circuit lead-out ends of the circuit substrate and obtaining a packaging structure with a small size; by electrically connecting the first memory wafer and the second memory wafer through a redistribution layer, the first memory wafer and the second memory wafer can work together, thereby obtaining a packaging structure with a large capacity, and thus obtaining a memory chip with a large capacity and a small size. Description of the Drawings
[0016] To more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0017] Figure 1 It is one of the structural schematic diagrams of the stacked package structure provided by the embodiment of the present invention.
[0018] Figure 2 It is the second of the structural schematic diagrams of the stacked package structure provided by the embodiment of the present invention.
[0019] Reference numerals: 101: circuit substrate; 102: first memory wafer; 103: second memory wafer; 104: functional pad; 105: first bonding wire; 106: second bonding wire; 107: first adhesive layer; 108: second adhesive layer; 109: substrate pad; 110: solder ball. Detailed implementation manners
[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the drawings in the present invention. Obviously, the described embodiments are some embodiments of the present invention, rather than all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0021] The following will be described in conjunction with Figure 1 - Figure 2 Describe the stacked package structure of the present invention.
[0022] Figure 1 It is one of the flow schematic diagrams of the stacked package structure provided by the present invention. As Figure 1 shown, the structure includes a circuit substrate 101, a first memory wafer 102, and a second memory wafer 103; the first side of the first memory wafer 102 is fixed on the first surface of the circuit substrate 101, and the second memory wafer 103 is fixed on the second side of the first memory wafer 102; the first side and the second side of the first memory wafer 102 are opposite sides; the circuit substrate 101 is provided with a redistribution layer, and the pins of the first memory wafer 102 and the pins of the second memory wafer 103 are respectively electrically connected to the redistribution layer, and the redistribution layer is used to electrically connect the first memory wafer 102 and the second memory wafer 103.
[0023] A memory wafer refers to an unpackaged chip (die). The first memory wafer 102 and the second memory wafer 103 can be the same memory wafer or different memory wafers. Exemplarily, both the first memory wafer 102 and the second memory wafer 103 can be memory wafers corresponding to 8Gb DDR4 memory.
[0024] The Redistribution Layer (RDL) can achieve high-density signal connections by adding one or more metal wiring layers (RDL) on a chip or package. Conductive structures such as vias, buried vias, and blind vias can be provided in the Redistribution Layer.
[0025] The stacked package structure provided by the present utility model can reduce the area of the circuit board 101 occupied by the first memory wafer 102 and the second memory wafer 103 by fixing the first memory wafer 102 on the first surface of the circuit board 101 and fixing the second memory wafer 103 on the first memory wafer 102, thereby reducing the number of circuit leads of the circuit board 101 and obtaining a package structure with a small size; by electrically connecting the first memory wafer 102 and the second memory wafer 103 through the Redistribution Layer, the first memory wafer 102 and the second memory wafer 103 can work together, thereby obtaining a package structure with a large capacity, and thus obtaining a memory chip with a large capacity and a small size.
[0026] Considering that directly obtaining a large-capacity domestic DDR4 based on the existing small-capacity domestic DDR4 will result in a relatively large volume and size of the obtained large-capacity domestic DDR4. To solve this technical problem, when both the first memory wafer 102 and the second memory wafer 103 can be memory wafers corresponding to 8Gb DDR4 memory, compared with placing the first memory wafer 102 and the second memory wafer 103 side by side on the circuit board 101, the stacked package structure provided in this embodiment can place the first memory wafer 102 on the circuit board 101 and stack the second memory wafer 103 on the first memory wafer 102, enabling the size of the circuit board 101 of the stacked package structure to be basically the same as the size of the substrate of a single memory wafer and the distribution of the circuit leads of the substrate, thereby obtaining a package structure with a small size. And in the stacked package structure provided by the present utility model, the first memory wafer 102 and the second memory wafer 103 are electrically connected through the Redistribution Layer, enabling the first memory wafer 102 and the second memory wafer 103 to work together, thereby obtaining a 16Gb DDR4 memory with a small size.
[0027] As a preferred embodiment, a plurality of functional pads 104 are provided on the first surface of the circuit board 101, and each functional pad 104 is electrically connected to the redistribution layer; the pins of the first memory wafer 102 and the pins of the second memory wafer 103 are respectively electrically connected to the corresponding functional pads 104.
[0028] Among them, the functional pad 104 is an electrical contact point on the substrate for connecting the pins of the first memory wafer 102 and the pins of the second memory wafer 103. The number and position of the functional pads 104 can be determined based on the specific design of the package structure. The specific design of the package structure can be the specific design of the redistribution layer or other circuits in the circuit board 101. The pins of the first memory wafer 102 can be the pads of the first memory wafer 102, and the pins of the second memory wafer 103 can be the pads of the second memory wafer 103.
[0029] The stacked package structure provided in this embodiment can transfer the pin signals of the first memory wafer 102 to the redistribution layer through the functional pads 104 on the substrate, and transfer the pin signals of the first memory wafer 102 to specific pin positions or other circuit parts through the redistribution layer; or transfer the pin signals of the second memory wafer 103 to the redistribution layer through the functional pads 104 on the substrate, and transfer the pin signals of the second memory wafer 103 to specific pin positions or other circuit parts through the redistribution layer, so as to electrically connect the first memory wafer 102 and the second memory wafer 103 through the redistribution layer.
[0030] As Figure 2 shown, in order to increase the flexibility of the connection between the pins of the first memory wafer 102 and the pins of the second memory wafer 103 and the functional pads 104 at different positions on the circuit board 101, as a preferred embodiment, a first bonding wire 105 is provided between the pins of the first memory wafer 102 and the corresponding functional pads 104; a second bonding wire 106 is provided between the pins of the second memory wafer 103 and the corresponding functional pads 104.
[0031] The first bonding wire 105 and the second bonding wire 106 are metal wires. It can be understood that according to specific packaging requirements or cost considerations, etc., the first bonding wire 105 between the pins of the first memory wafer 102 and the corresponding functional pads 104 can be a gold wire, an aluminum wire or a copper wire, etc., and the first bonding wire 106 between the pins of the second memory wafer 103 and the corresponding functional pads 104 can be a gold wire, an aluminum wire or a copper wire, etc.
[0032] To facilitate the simple and rapid fixation of the first memory wafer 102 on the circuit board 101 and the fixation of the second memory wafer 103 on the first memory wafer 102, as a preferred embodiment, a first adhesive layer 107 is provided between the first side of the first memory wafer 102 and the first surface of the circuit board 101, and a second adhesive layer 108 is provided between the second memory wafer 103 and the second side of the first memory wafer 102; the first bonding wire 105 connected to the pins of the first memory wafer 102 is at least partially located in the second adhesive layer 108.
[0033] The portion of the first bonding wire 105 located in the second adhesive layer 108 is the first bonding wire 105 near the pin portion of the first memory wafer 102. In this way, during the process of fixing the second memory wafer 103 above the first memory wafer 102, the risk of physical damage to the first bonding wire 105 near the pin portion of the first memory wafer 102 or the pin portion of the first memory wafer 102 can be reduced. At the same time, the second adhesive layer 108 can provide mechanical support for the second memory wafer 103, thereby increasing the stability of the stacked package structure.
[0034] To reduce the complexity of the routing of the redistribution layer, as a preferred embodiment, at least one functional pad 104 is electrically connected to both the first bonding wire 105 and the second bonding wire 106.
[0035] The bonding wire between the pins of the first memory wafer 102 and the pads on the first surface of the circuit board 101 can electrically connect the first memory wafer 102 to the pads on the first surface of the circuit board 101. The bonding wire between the pins of the second memory wafer 103 and the pads on the first surface of the circuit board 101 can electrically connect the second memory wafer 103 to the pads on the first surface of the circuit board 101. In this way, a functional pad 104 is electrically connected to both the first memory wafer 102 and the second memory wafer 103, enabling the first memory wafer 102 and the second memory wafer 103 to share the signals corresponding to the functional pad 104, which can reduce the complexity of the routing of the redistribution layer and save space on the circuit board 101 at the same time.
[0036] The first memory wafer 102 can be horizontally fixed on the first surface of the circuit board 101, and the second memory wafer 103 can be parallelly fixed on the second side of the first memory wafer 102. The distance between the first memory wafer 102 and the second memory wafer 103 is relatively small, and it is relatively difficult to lead out the first bonding wire 105 connected to the pads on the second side of the first memory wafer 102 from between the first memory wafer 102 and the second memory wafer 103.
[0037] To solve the above problems, as a preferred embodiment, the thickness of the first adhesive layer 107 is less than the thickness of the second adhesive layer 108. The second adhesive layer 108 is thicker than the first adhesive layer 107. In this way, by increasing the thickness of the second adhesive layer 108, it is convenient for the first bonding wire 105 connected to the pads on the second side of the first memory wafer 102 to be led out from between the first memory wafer 102 and the second memory wafer 103; on this basis, the thickness of the second adhesive layer 108 can be specifically determined in combination with the bonding stability and mechanical support stability of the second adhesive layer 108, and no specific limitation is made here.
[0038] The thickness of the first adhesive layer can be specifically determined based on the bonding stability and mechanical support stability of the first adhesive layer 107, and no specific limitation is made here either. Under the condition of meeting the foregoing conditions, by reducing the thickness of the first adhesive layer 107, the vertical distance between the side of the second memory wafer 103 away from the circuit board 101 and the circuit board 101 can be controlled to avoid the laminated package structure from being too thick.
[0039] As a preferred embodiment, the first adhesive layer 107 is a wafer bonding film, and the second adhesive layer 108 is a film over wire. Among them, the wafer bonding film (Die Attach Film, DAF) can include a first adhesive surface, a second adhesive surface and an intermediate layer, and the intermediate layer is between the first adhesive surface and the second adhesive surface. The first adhesive surface can be bonded to the first memory wafer 102, the second adhesive surface can be bonded to the first surface of the circuit board 101, and the intermediate layer can provide a supporting effect on the first memory wafer 102. By filling the space between the first memory wafer 102 and the second memory wafer 103 with the film over wire (FOW), it is convenient to embed the first bonding wire therein.
[0040] To facilitate the connection between the circuit board 101 and the external circuit structure, as a preferred embodiment, a substrate pad 109 is provided on the second surface of the circuit board 101, and a solder ball 110 is provided on the substrate pad 109. Exemplarily, the solder ball 110 can be a lead-tin solder ball, a tin-copper solder ball or a tin-silver solder ball, etc.
[0041] The substrate pad 109 on the second surface of the circuit board 101 can also be electrically connected to the redistribution layer. In this way, when the circuit board 101 is connected to other circuit structures through the substrate pad 109 and the solder ball 110, the signal connection between the first memory wafer 102 and the second memory wafer 103 and the circuit structure can be realized. Exemplarily, the substrate pad 109 can be electrically connected to the conductive structure of the redistribution layer.
[0042] When a certain functional pad 104 is electrically connected to the first bonding wire 105 and the second bonding wire 106 simultaneously, and the second memory wafer 103 is disposed on a side of the first memory wafer 102 away from the circuit board 101, the length of the first bonding wire 105 between the pin of the first memory wafer 102 and the functional pad 104 is less than the length of the second bonding wire 106 between the pin of the second memory wafer 103 and the functional pad 104. In this way, the time for the same type of signal to be transmitted to the first memory wafer 102 and the second memory wafer 103 through the redistribution layer is different, which may affect the signal connection between the first memory wafer 102 and the second memory wafer 103.
[0043] To solve this problem, in this embodiment, the routing of the redistribution layer of the circuit board 101 is configured such that the total length from the substrate pad 109 on the second surface of the circuit board 101 to the first memory wafer 102 is substantially the same as the total length from the substrate pad 109 on the second surface of the circuit board 101 to the second memory wafer 103, so that the electrical signals transmitted through the redistribution layer can reach the first memory wafer 102 and the second memory wafer 103 substantially simultaneously.
[0044] On the first surface of the circuit board 101, a molded resin may be covered. The molded resin may be provided with an inner cavity, and the inner cavity corresponds to the overall shape formed by the first memory wafer 102 and the second memory wafer 103 on the circuit board 101.
[0045] In order to facilitate the extraction of the first bonding wire 105 and the second bonding wire 106 while shortening the length difference between the first bonding wire 105 and the second bonding wire 106, as a preferred embodiment, the pin of the first memory wafer 102 connected to the first bonding wire 105 is located on the surface of the first memory wafer 102 away from the circuit board 101; the pin of the second memory wafer 103 connected to the second bonding wire 106 is located on the surface of the second memory wafer 103 away from the circuit board 101.
[0046] The surface of the second memory wafer 103 away from the circuit board 101 is the surface of the second memory wafer 103 away from the first memory wafer 102. Compared with the case where the first bonding wire 105 is disposed on the surface of the first memory wafer 102 close to the circuit board 101 and the second bonding wire 106 is disposed on the surface of the second memory wafer 103 close to the circuit board 101, by disposing on the surface of the second memory wafer 103 away from the first memory wafer 102, it is possible to facilitate the extraction of the second bonding wire 106.
[0047] Compared with the case where the first bonding wire 105 is disposed on the surface of the first memory wafer 102 close to the circuit board 101 and the second bonding wire 106 is disposed on the surface of the second memory wafer 103 far from the circuit board 101, the stacked package structure provided in this embodiment can shorten the length difference between the first bonding wire 105 and the second bonding wire 106, so that the electrical signals transmitted by the redistribution layer can reach the first memory wafer 102 and the second memory wafer 103 substantially simultaneously.
[0048] Optionally, in one embodiment, the pins of the first memory wafer 102 connected to the first bonding wire 105 are located on the surface of the first memory wafer 102 far from the circuit board 101; the thickness of the second adhesive layer 108 can be increased so that the pins of the second memory wafer 103 connected to the second bonding wire 106 are located on the surface of the second memory wafer 103 close to the first memory wafer 102.
[0049] The stacked package structure provided by the present utility model, through a vertical stacking method, on the basis of doubling the storage capacity, makes the length and width dimensions of the stacked package structure consistent with those of the existing 8Gb DDR4 memory chip. It adopts a double-layer wafer stacking flip-chip technology with the second memory wafer 103, the second adhesive layer 108, the first memory wafer 102, the first adhesive layer 107, and the circuit board 101 from top to bottom, and is compatible with a general package structure with the same number of lead-out ends without changing the length and width dimensions of the package structure, the pitch, quantity, and arrangement of the lead-out ends. The package structure can be a Plastic Ball Grid Array (PBGA) package. Moreover, by optimizing the routing of the redistribution layer, the selection of packaging materials, etc., its operating efficiency and heat dissipation efficiency can be improved, its power consumption can be reduced, and the performance of the obtained 16Gb DDR4 memory can be ensured to be basically the same as that of the 8Gb DDR4 memory.
[0050] The present utility model also provides a chip, including the stacked package structure as described in any one of the above; and a housing for accommodating the stacked package structure.
[0051] The working principle and technical effects of the chip provided in this embodiment are basically the same as those of any one of the foregoing stacked package structures, and will not be elaborated herein.
[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.
Claims
1. A stacked package structure, characterized in that, It includes a circuit board, a first memory wafer, and a second memory wafer; The first side of the first memory wafer is fixed on the first surface of the circuit board, and the second memory wafer is fixed on the second side of the first memory wafer; the first side and the second side of the first memory wafer are opposite sides; wherein, the second memory wafer is aligned and fixed with the first memory wafer; The circuit board is provided with a redistribution layer, and the pins of the first memory wafer and the pins of the second memory wafer are respectively electrically connected to the redistribution layer, and the redistribution layer is used to electrically connect the first memory wafer and the second memory wafer; A plurality of functional pads are provided on the first surface of the circuit board, and each functional pad is respectively electrically connected to the redistribution layer; The pins of the first memory wafer and the pins of the second memory wafer are respectively electrically connected to the corresponding functional pads; A first bonding wire is provided between the pin of the first memory wafer and the corresponding functional pad; a second bonding wire is provided between the pin of the second memory wafer and the corresponding functional pad; A first adhesive layer is provided between the first side of the first memory wafer and the first surface of the circuit board, and a second adhesive layer is provided between the second memory wafer and the second side of the first memory wafer; The first bonding wire connected to the pin of the first memory wafer is at least partially located in the second adhesive layer; At least one functional pad is electrically connected to both the first bonding wire and the second bonding wire; The thickness of the first adhesive layer is less than the thickness of the second adhesive layer; The second adhesive layer is used to reduce the risk of physical damage to the first bonding wire near the pin portion of the first memory wafer or the pin portion of the first memory wafer.
2. The stacked package structure according to claim 1, wherein The first adhesive layer is a wafer bonding film, and the second adhesive layer is a wire-bonding film.
3. The stacked package structure according to claim 1, wherein Substrate pads are provided on the second surface of the circuit board, and solder balls are provided on the substrate pads.
4. The stacked package structure according to claim 1, wherein The pin of the first memory wafer connected to the first bonding wire is located on the surface of the first memory wafer away from the circuit board; the pin of the second memory wafer connected to the second bonding wire is located on the surface of the second memory wafer away from the circuit board.
5. A chip, characterized in that, It includes a stacked package structure according to any one of claims 1-4; and a housing for accommodating the stacked package structure.