Control circuit for equipment burning debugging

Abstract

The utility model provides a control circuit for burning debugging of equipment. The control circuit comprises a reset module, a burning debugging interface module, an electronic switch module and a level control module, the first input end of the electronic switch module is connected with the output end of the burning debugging interface module, the first output end of the electronic switch module is connected with the first input end of the reset module and one end of the level control module, and the second input end of the electronic switch module is connected with the first output end of the reset module. The burning debugging interface module is used for outputting a second voltage to the first input end of the electronic switch module; the level control module is used for outputting a high level signal to the first input end; and the electronic switch module is used for disconnecting the first output end and the second input end of the electronic switch module under the action of the second voltage, so that the reset module does not output the reset signal. The watchdog reset circuit is automatically switched and shielded through the electronic switch, and the watchdog reset circuit is prevented from interrupting burning debugging of equipment.

Description

Technical Field

[0001] The utility model relates to the technical field of power electronics, in particular to a control circuit for burning and debugging equipment. Background Art

[0002] For electronic equipment systems with microprocessors such as single-chip microcomputers or embedded systems, in order to improve the anti-interference and reliability of the electronic equipment system, a reset circuit is usually used during device burning and debugging to avoid reset interruption and ensure the normal operation of the device burning and debugging work.

[0003] Prior art methods for switching the reset circuit typically use jumpers, resistors, or a DIP switch to manually reset the pin. This disconnects the hardware reset function before program programming, testing, or debugging, preventing the central processing unit (CPU) from resetting during the program. Once the program is programming, testing, or debugging, a jumper cap is used to connect the reset circuit or a resistor is soldered to restore normal connection. While these methods address the issue of the reset circuit interrupting program programming to some extent, they all have limitations. Utility Model Content

[0004] The purpose of the present invention is to provide a control circuit for device programming and debugging in view of the above-mentioned deficiencies in the prior art, so as to solve the problem of limitations of the programming program of the reset circuit terminal in the prior art.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] The embodiment of the utility model provides a control circuit for burning and debugging a device, the control circuit comprising: a reset module, a burning and debugging interface module, an electronic switch module and a level control module;

[0007] The first input end of the electronic switch module is connected to the output end of the programming and debugging interface module, the first output end of the electronic switch module is connected to the first input end of the reset module and one end of the level control module, the second input end of the electronic switch module is connected to the first output end of the reset module, and the other end of the level control module is used to connect to a first power supply, and the voltage of the first power supply is a first voltage;

[0008] The burning and debugging interface module is used to output a second voltage to the first input terminal of the electronic switch module, and the first voltage is different from the second voltage;

[0009] The level control module is used to output a high level signal to the first input terminal of the reset module;

[0010] The electronic switch module is configured to disconnect the first output terminal of the electronic switch module from the second input terminal of the electronic switch module under the action of the second voltage, so that the reset module does not output a reset signal.

[0011] According to an embodiment of the present invention, a control circuit for device programming and debugging is provided. The control circuit includes: a reset module, a programming and debugging interface module, an electronic switch module, and a level control module. The first input end of the electronic switch module is connected to the output end of the programming and debugging interface module, the first output end of the electronic switch module is connected to the first input end of the reset module and one end of the level control module, the second input end of the electronic switch module is connected to the first output end of the reset module, and the other end of the level control module is used to connect to a first power supply, the voltage of the first power supply being a first voltage; the programming and debugging interface module is used to output a second voltage to the first input end of the electronic switch module, the first voltage being different from the second voltage; the level control module is used to output a high-level signal to the first input end of the reset module, and the electronic switch module is used to disconnect the first output end from the second input end of the electronic switch module under the action of the second voltage, so that the reset module does not output a reset signal. The present invention enables compatibility with devices connected via interfaces such as the Universal Serial Bus (USB), Joint Test Action Group (JTAG), Serial Wire (SW), and Universal Asynchronous Receiver / Transmitter (UART) for programming, testing, debugging, and upgrading, eliminating the need for developing additional programming adapter boards or reserving special interfaces. Furthermore, when the MCU or CPU is unprogrammed and connected to the device via interfaces such as USB, JTAG, SW, and UART for programming, testing, debugging, and upgrading, an electronic switch automatically switches to shield the reset circuit. During normal MCU or CPU operation, testing and debugging programs through the interfaces will not be reset by the watchdog, thereby impacting testing and debugging. Furthermore, after program programming, testing, and debugging are complete, there's no need for software to activate the watchdog; simply unplugging the interface automatically resumes normal operation. Furthermore, the watchdog reset circuit delay during the reset process is adjustable, ensuring a normal startup time for device system loading and self-testing. The entire control circuit design is simple and easy to understand, highly versatile, and easy to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of a control circuit for device programming and debugging provided by an embodiment of the present utility model is shown;

[0014] Figure 2 A schematic diagram of an electronic switch module provided by an embodiment of the present utility model is shown;

[0015] Figure 3 A schematic diagram of a watchdog reset circuit provided by an embodiment of the present utility model is shown;

[0016] Figure 4 A schematic diagram of a programming and debugging interface module provided by an embodiment of the present utility model is shown;

[0017] Figure 5 A schematic diagram of a control circuit provided by an embodiment of the present utility model is shown;

[0018] Figure 6 A schematic diagram of another control circuit provided by an embodiment of the present utility model is shown;

[0019] Figure 7 A schematic diagram of another control circuit provided by an embodiment of the present utility model is shown;

[0020] Figure 8 A schematic diagram of another control circuit provided by an embodiment of the present utility model is shown;

[0021] Figure 9 A schematic diagram of another control circuit provided by an embodiment of the present utility model is shown;

[0022] Figure 10 A schematic diagram of another control circuit provided by an embodiment of the present utility model is shown;

[0023] Figure 11 A schematic diagram of another control circuit provided by an embodiment of the present utility model is shown;

[0024] Figure 12 A schematic diagram of another control circuit provided by an embodiment of the present utility model is shown.

[0025] Icons: 10-reset module; 11-burning and debugging interface module; 12-electronic switch module; 13-level control module; 121-electronic switch unit; 122-first resistor; 123-second resistor; 124-first capacitor; 111-burning interface chip; nWDO-timeout output pin; nMR-reset input pin; CWD-timeout input pin; C4-second capacitor; WDI-watchdog feeding input pin; R5-third resistor; WDI CPU-peripheral circuit feeding signal pin; nRESET-reset signal output pin; R4-fourth resistor; RESET CPU-peripheral circuit reset pin; C3-third capacitor; C5-filter capacitor; ED1-static protection unit; R3-pull-up resistor; VBUS-interface power supply; U1-analog electronic switch device; GND-ground; U2-watchdog circuit reset monitoring chip. DETAILED DESCRIPTION

[0026] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are also within the scope of protection of the present invention.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0029] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the utility model product is typically placed when in use. These terms are intended solely to facilitate the description of this utility model and to simplify the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this utility model. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] Furthermore, terms such as "horizontal" and "vertical" do not necessarily mean that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0031] It should also be noted that, in the description of this utility model, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0032] Before introducing the present invention in detail, a brief introduction to the relevant background of the present invention is first given.

[0033] 1. In hardware design, the reset circuit is used in the MCU or CPU peripheral circuit to have the following functions:

[0034] (1) Prevent the MCU / CPU from running abnormally when the power supply voltage of the MCU / CPU fluctuates. When the voltage is lower than a certain value, the reset circuit can reset the MCU / CPU.

[0035] (2) The reset circuit includes a hardware watchdog function. When the program runs out of control and gets stuck at a certain address for a certain period of time, the hardware watchdog forces the MCU / CPU to reset.

[0036] 2. When writing low-level programs and applications, it is necessary to burn, test, debug, and upgrade the device through interfaces such as USB, JTAG, SW, and UART. Due to the existence of a hardware reset circuit, if the hardware watchdog detects that the feeding time exceeds a certain time, such as 2 seconds, it will trigger a reset, which will cause the above operations to fail. Specifically:

[0037] (1) During the program burning process, since there is no program in the MCU / CPU and no dog feeding action, the reset circuit causes the MCU / CPU to reset repeatedly after timeout, and the program cannot be burned successfully.

[0038] (2) During the device program startup process, since most SOC embedded system devices will have a complex and time-consuming power-on self-test when they are powered on, and the loading and startup process of complex systems (such as Linux) takes a long time, the CPU has not completed the startup and there is no watchdog feeding action. After the timeout, the watchdog outputs a reset signal and the device restarts. The restart process times out and the watchdog is fed again, which causes the CPU to restart repeatedly, and then the device cannot be started normally.

[0039] (3) During the development, testing and debugging phase, calling the third-party interface library routine generally fails to feed the dog normally. After the timeout, the reset signal is output, causing the CPU to restart, making it impossible to test, debug and develop normally.

[0040] During program burning, testing, and debugging, the MCU / CPU must continue to operate and not be reset midway. During this time, the watchdog should not output a reset signal. However, after program burning, testing, and debugging are complete, the MCU / CPU should be started and fed normally, allowing the watchdog to function normally. This allows the system to be reset by the watchdog in the event of a system freeze, ensuring normal system operation.

[0041] To this end, the existing watchdog reset switching control method mainly uses a jumper cap, a jumper resistor, or a DIP switch to manually disconnect the reset pin. Before program burning, testing, and debugging, the hardware reset function is disconnected to prevent the CPU from resetting during the program burning, testing, and debugging. After the program burning, testing, and debugging are completed, the reset circuit is reconnected using a jumper cap or a resistor. Although this method solves the problem of the reset circuit interrupting program burning to a certain extent, when the printed circuit board (PCB) is enclosed in the device housing, debugging or updating the program requires first opening the housing and then removing the jumper cap or switch before the program can be burned. This operation is very inconvenient. In addition, during mass production and debugging, the jumper or DIP switch requires frequent operation, which is tedious and time-consuming, resulting in very low program burning production efficiency. Furthermore, adding a jumper or DIP switch to the circuit is equivalent to an additional mechanical failure point. Due to long-term operation of the switch, the contacts are easily oxidized, resulting in a circuit disconnection, which in turn affects the normal operation of the watchdog reset circuit and the reliability of the device.

[0042] In addition, the prior art uses an additionally developed burning adapter board and a reserved special interface to switch and shield the watchdog reset signal, but this method has poor practicality. Alternatively, a gate circuit combination method is used to shield and control the watchdog reset signal, but this method is relatively complex. Alternatively, the watchdog is fed information through the clock signal of JTAG or SWD, but this method cannot be used when burning, debugging, or upgrading using USB or UART, that is, this method is not universal for different interface methods. Alternatively, the IO pin of the MCU / CPU is used to control whether the watchdog reset signal is connected to the MCU / CPU to cut off the control watchdog reset signal. Although this method is simple in circuit, due to the use of the IO pin of the MCU / CPU, when the MCU / CPU is abnormal, the IO pin of the MCU / CPU will directly cut off the watchdog reset signal. In this case, the MCU / CPU will not be able to reset and restart, and the watchdog reset circuit will lose its due function.

[0043] Given the limitations of the aforementioned watchdog reset switching control methods, the present invention relates to a control circuit for automatically switching the reset circuit during device programming and debugging. Specifically, it relates to a control circuit that automatically switches the watchdog reset circuit via an electronic switch, preventing it from interrupting device programming, testing, and debugging. This control circuit enables compatibility with devices connected via interfaces such as USB, JTAG, SW, and UART for programming, testing, debugging, and upgrading, without the need to develop additional programming adapter boards or reserve special interfaces. When the MCU or CPU is in an unprogrammed state and the device is connected via an interface such as USB, JTAG, SW, or UART for programming, testing, debugging, and upgrading, the electronic switch automatically switches to shield the reset circuit. When the MCU or CPU is operating normally, testing and debugging programs through the interface will prevent the watchdog reset from impacting testing and debugging. Furthermore, after program programming, testing, and debugging are complete, there's no need for software to control the watchdog's activation; unplugging the interface automatically resumes normal operation. Furthermore, the watchdog reset circuit's delay during the reset startup process is adjustable, ensuring a normal startup time for device system loading and self-testing. The design principle of the entire control circuit is simple to understand, highly versatile and easy to use.

[0044] Figure 1 The following is a schematic diagram showing a control circuit for device programming and debugging provided by the present invention. Figure 1As shown, the control circuit includes a reset module 10, a programming and debugging interface module 11, an electronic switch module 12, and a level control module 13. The first input of the electronic switch module 12 is connected to the output of the programming and debugging interface module 11. The first output of the electronic switch module 12 is connected to the first input of the reset module 10 and one end of the level control module 13. The second input of the electronic switch module 12 is connected to the first output of the reset module 10. The other end of the level control module 13 is connected to a first power supply, where the voltage of the first power supply is a first voltage. The programming and debugging interface module 11 is configured to output a second voltage to the first input of the electronic switch module 12, where the first voltage is different from the second voltage. The level control module 13 is configured to output a high-level signal to the first input of the reset module. Under the influence of the second voltage, the electronic switch module 12 is configured to disconnect the first output of the electronic switch module 12 from the second input of the electronic switch module 12, so that the reset module 10 does not output a reset signal.

[0045] Optionally, the electronic switch module 12 can determine whether to allow the reset signal to pass based on the state of the input signal. The level control module 13 is used to generate a stable reference level or perform level conversion on the input signal to make it suitable for the operating conditions of the reset module. Based on this, when the burning and debugging interface module 11 is connected to the electronic switch module 12 and the burning and debugging interface module 11 outputs a second voltage to the electronic switch module 12, the electronic switch module 12 responds to this second voltage by disconnecting the first output terminal and the second output terminal of the electronic switch module 12, thereby preventing the reset signal from being transmitted from the reset module 10. At the same time, the level control module 13 ensures that the first input terminal of the reset module 10 receives a high-level signal, thereby controlling the reset module 10 to maintain the reset state or prevent it from resetting.

[0046] Figure 2 A schematic diagram of an electronic switch module provided by the present invention is shown. As a possible implementation method, refer to Figure 2 As shown, the electronic switch module 12 includes an electronic switch unit 121, a first resistor 122, a second resistor 123, and a first capacitor 124. One end of the first resistor 122 is connected to the output of the programming and debugging interface module 11, the other end of the first resistor 122 is connected to one end of the second resistor 123 and the input of the electronic switch unit 121, and the other end of the second resistor 123 is grounded. One end of the first capacitor 124 is connected to the power supply and the power supply of the electronic switch unit 121, respectively, and the other end of the first capacitor 124 is grounded. The first output of the electronic switch unit 121 is connected to the first input of the reset module 10 and one end of the level control module 13, and the second input of the electronic switch unit 121 is connected to the first output of the reset module 10.

[0047] Optionally, when the programming and debugging interface module 11 outputs a signal, such as a second voltage, the voltage signal reaches the input terminal of the electronic switch unit 121 after passing through the first resistor 122. The electronic switch unit 121 will change its state, disconnecting the first output terminal from the second input terminal of the electronic switch unit 121, thereby preventing the reset signal from being output from the reset module 10. In addition, the first capacitor 124 is connected between the power supply and ground to filter out power supply fluctuations and ensure that the electronic switch unit 121 obtains a stable operating voltage. This ensures that when programming or debugging is performed, the behavior of the reset module can be controlled by the signal provided by the external interface, thereby achieving more flexible debugging and programming operations.

[0048] Optionally, the reset module 10 includes a watchdog reset circuit, a timeout output pin of the watchdog reset circuit serves as the first output terminal of the reset module 10 , and a reset input pin of the watchdog reset circuit serves as the first input terminal of the reset module 10 .

[0049] For example, referring to Figure 3 As shown, the timeout output pin nWDO of the watchdog reset circuit serves as the first output terminal of the reset module 10 , and the reset input pin nmr of the watchdog reset circuit serves as the first input terminal of the reset module 10 .

[0050] Optionally, the watchdog reset circuit also includes a timeout input pin, which is connected to one end of a second capacitor, and the other end of the second capacitor is grounded. The second capacitor is used to control the watchdog trigger delay after the watchdog reset circuit is reset.

[0051] For example, referring to Figure 3 As shown, the watchdog reset circuit further includes a timeout input pin CWD, which is connected to one end of the second capacitor C4, and the other end of the second capacitor C4 is grounded.

[0052] Optionally, the watchdog reset circuit also includes a watchdog feeding input pin, which is connected to one end of the third resistor, and the other end of the third resistor is connected to the dog feeding signal pin of the peripheral circuit; the watchdog reset circuit also includes a reset signal output pin, which is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the reset pin of the peripheral circuit, and the reset signal output pin is connected to one end of the third capacitor, and the other end of the third capacitor is grounded.

[0053] For example, referring to Figure 3 As shown, the watchdog reset circuit further includes a watchdog feeding input pin WDI, which is connected to one end of a third resistor R5, and the other end of the third resistor R5 is connected to a feeding signal pin WDI CPU of a peripheral circuit.

[0054] Exemplarily, the watchdog reset circuit also includes a reset signal output pin nRESET, the reset signal output pin nRESET is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the reset pin RESET CPU of the peripheral circuit, and the reset signal output pin nRESET is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is grounded.

[0055] Optionally, the programming and debugging interface module 11 includes a programming interface chip, a filter capacitor, and an electrostatic protection unit. The output end of the programming interface chip is connected to one end of the filter capacitor and one end of the electrostatic protection unit, respectively. The other ends of the filter capacitor and the electrostatic protection unit are grounded. The filter capacitor is used to filter high-frequency noise from the interface power supply of the programming and debugging interface module, and the electrostatic protection unit is used to reduce electrostatic discharge interference. One end of the filter capacitor or the electrostatic protection unit is connected to the input end of the electronic switch module.

[0056] Figure 4 The schematic diagram of a programming and debugging interface module provided by the present invention is shown. As a possible implementation method, refer to Figure 4 As shown, the programming and debugging interface module 11 includes a programming interface chip 111, a filter capacitor C5, and an electrostatic protection unit ED1, which can be an anti-static protection tube. The output terminal VBUS of the programming interface chip 111 is connected to one end of the filter capacitor C5 and one end of the anti-static protection tube, respectively. The other end of the filter capacitor C5 and the other end of the anti-static protection tube are grounded.

[0057] Optionally, the programming interface chip 111 includes any one of the following: Universal Serial Bus (USB), Joint Test Action Group (JTAG), Serial Wire (SW), Universal Asynchronous Receiver / Transmitter (UART).

[0058] For example, the programming debug interface uses the Universal Serial Bus (USB) for communication, offering high-speed transmission, wide support, and easy connectivity. The serial debug interface (SW), including Serial Wire Debug (SWD) or Serial Wire JTAG (SWJ), is a serial communication protocol that requires fewer pins and saves space. The Joint Test Group (JTAG) is a standard test access port with powerful functionality and support for a variety of operations. The Universal Asynchronous Receiver / Transmitter (UART) is used for asynchronous serial communication and is simple and easy to use.

[0059] Optionally, the electronic switch unit 121 includes an analog electronic switch, the input end of the analog electronic switch serves as the first input end of the electronic switch unit 121, the common end of the analog electronic switch serves as the second input end of the electronic switch unit 121, and the normally closed end of the analog electronic switch serves as the first output end of the electronic switch unit 121.

[0060] For example, the analog electronic switch can be an RS2057XC6 analog electronic switch device. The RS2057XC6 is a device used to switch signal paths within a circuit. It is typically a single-pole, double-throw (SPDT) switch with a common terminal (COM), an input terminal (IN), and two output terminals (NO and NC). Depending on the control signal, the COM terminal can be connected to either the NO terminal or the NC terminal to control the on / off state of the signal. The common terminal COM is the signal communication connection point, and the input terminal IN is used to receive the control signal and determine the switch state. When the normally closed terminal NC is connected to the COM terminal, the switch is inactive; when the normally open terminal NO is connected to the COM terminal, the switch is active.

[0061] For example, under normal circumstances, when the IN terminal receives a high-level signal, the analog electronic switch device switches to an active state, connecting the COM terminal to the NO terminal. When the IN terminal receives a low-level signal, the analog electronic switch device returns to an inactive state, connecting the COM terminal to the NC terminal. In other words, when the IN terminal is at a high level, the COM terminal and the NO terminal are connected, and the signal flows from the COM terminal to the NO terminal. When the IN terminal is at a low level, the COM terminal and the NC terminal are connected, and the signal flows from the COM terminal to the NC terminal.

[0062] Optionally, the electronic switch unit 121 includes a relay, the input end of the relay serves as the first input end of the electronic switch unit 121 , the common end of the relay serves as the second input end of the electronic switch unit 121 , and the normally closed end of the relay serves as the first output end of the electronic switch unit 121 .

[0063] For example, a relay is a switch that uses an electromagnet to control a circuit. It includes a coil for generating a magnetic field, an iron core that moves in response to the coil's magnetic field, two contacts (normally open and normally closed), and a common terminal for connecting the normally open and normally closed contacts. When the relay coil is de-energized, the normally closed contact (NC) is connected to the common terminal (COM), while the normally open contact (NO) is disconnected from the common terminal (COM). When the relay coil is energized, the normally closed contact (NC) is disconnected from the common terminal (COM), while the normally open contact (NO) is connected to the common terminal (COM). Based on this, a relay can be used to automatically switch the reset circuit on and off, and the relay can automatically select whether to connect the normally closed contact or the normally open contact based on the state of the control signal.

[0064] Figure 5As a possible implementation method, refer to Figure 5 As shown, the electronic switch module 12 is used to simulate the electronic switch device U1 (using RS2057XC6 as an example), and the debugging interface module 11 (ie Figure 5 J1 shown in FIG is a universal serial bus USB, and the reset module 10 is a watchdog circuit reset monitoring chip (eg Figure 5 Taking the SGM820B watchdog timer shown in the figure as an example, the level control module 13 is a pull-up resistor R3 (with a resistance of, for example, 10K), the universal serial bus USB includes an interface power supply VBUS and USB differential data signals USB_P and USB_N. The interface power supply VBUS is connected to the filter capacitor C5 and the electrostatic protection unit ED1. One end of the filter capacitor C5 and the electrostatic protection unit ED1 is connected to the common ground GND. The USB differential data signals USB_P and USB_N are connected to the MCU / CPU or CPU for program burning test and debugging.

[0065] For example, referring to Figure 5 As shown, the interface power supply VBUS is connected to the analog electronic switch device U1 through a resistor R2 (e.g., a 10K resistor). One end of resistor R2 is connected to the interface power supply VBUS, and the other end is connected to the digital control input pin IN of the analog electronic switch device U1 and resistor R1 (resistor R1 is a ground resistor). The other end of resistor R1 (e.g., a 10K resistor) is connected to ground GND. The COM pin of the analog electronic switch device U1 is connected to the timeout output pin nWDO of the watchdog circuit reset monitoring chip U2. The NC pin of the analog electronic switch device U1 is connected to a pull-up resistor R3 and the reset input pin nmr of the watchdog circuit reset monitoring chip U2. One end of the pull-up resistor R3 is connected to the motherboard power supply VDD_1V8, and the other end of the pull-up resistor R3 is connected to a resistor R6 and the reset input pin nmr of the watchdog circuit reset monitoring chip U2. The NO terminal pin of the analog electronic switching device U1 is vacant, the V+ terminal power supply pin of the analog electronic switching device U1 is connected to the 3V3 power supply, the V+ terminal power supply pin of the analog electronic switching device U1 is connected to a small-capacitance filter capacitor to the ground GND, and the GND terminal pin of the analog electronic switching device U1 is connected to the public ground GND.

[0066] For example, one end of resistor R6 is connected to the reset input pin nMR of the watchdog circuit reset monitoring chip U2. The other end of resistor R6 (also known as the fifth resistor) is connected to the reset button S1. The other end of reset button S1 is connected to the common ground GND. The adjustable watchdog timeout input pin CWD of the watchdog circuit reset monitoring chip U2 is connected to the timeout setting capacitor C4. The other end of timeout setting capacitor C4 is connected to the common ground GND. The watchdog feeding input pin WDI of the watchdog circuit reset monitoring chip U2 is connected to the dog feeding signal IO pin of the MCU / CPU through a resistor R5, the reset signal output pin nRESET of the watchdog circuit reset monitoring chip U2 is connected to a small filter capacitor to the common ground GND, and the reset signal output pin nRESET of the watchdog circuit reset monitoring chip U2 is connected to the reset pin of the MCU / CPU through a resistor R4; the VCC power supply pin of the watchdog circuit reset monitoring chip U2 is connected to the mainboard power supply VDD_1V8, the VCC power supply pin of the watchdog circuit reset monitoring chip U2 is connected to a small filter capacitor to the common ground GND, and the GND pin of the watchdog circuit reset monitoring chip U2 is connected to the common ground GND.

[0067] based on Figure 5 The control circuit shown, when connected to the mainboard device system through the USB interface for program burning, testing, debugging or updating, because the input voltage VBUS is at a high level, the digital control input pin IN of the analog electronic switch device U1 connected to VBUS through the resistor R2 (resistor R2 is a current limiting resistor) is pulled to a high level, triggering the internal conduction and disconnection of the COM terminal and the NC terminal of the analog electronic switch device U1, and the COM terminal is connected to the NO terminal. The watchdog circuit reset monitoring chip U2 is connected to the nmr pin of the NC end of the analog electronic switching device U1. Under the action of the pull-up resistor R3, the nmr pin remains at a high level, and the watchdog circuit reset monitoring chip U2 will not output a reset signal (usually a low level is valid). When the watchdog circuit reset monitoring chip U2 times out and takes effect, the nWDO end of the watchdog circuit reset monitoring chip U2 outputs a low-level signal. Because the connection between the nWDO end and the nmr end is disconnected, the voltage of the nMR end of the watchdog circuit reset monitoring chip U2 remains at a Vmr high level under the action of the pull-up resistor. Therefore, the nRESET end of the watchdog circuit reset monitoring chip U2 still maintains a high-level output. At this time, the "watchdog" reset signal is invalid, and the motherboard device system can be burned, tested, debugged or upgraded normally without being interrupted by the reset.

[0068] Furthermore, when the motherboard device system is completed from programming, testing, debugging, or upgrading and the interface cable is unplugged, the VBUS voltage of the programming and debugging interface module (J1) drops to zero. The digital control input pin IN of the analog electronic switch device U1, which is connected to VBUS via resistor R2, goes low, triggering the internal conduction connection between the COM terminal and the NC terminal of the analog electronic switch device U1. The timeout output pin nWDO of the watchdog circuit reset monitoring chip U2, switched by the analog electronic switch device U1, is then connected to the reset input pin nmr of the watchdog circuit reset monitoring chip U2. At this point, the timeout output pin nWDO of the watchdog circuit reset monitoring chip U2 is low, pulling down the reset input pin nmr of the watchdog circuit reset monitoring chip U2. This triggers the nRESET terminal of the watchdog circuit reset monitoring chip U2 to output a low level, causing the motherboard device system to automatically reset and restart, and the "watchdog" reset circuit to resume normal operation.

[0069] Furthermore, when the mainboard device system automatically resets and restarts, the timeout time of the CWD terminal of the watchdog circuit reset monitoring chip U2 can be adjusted according to the time it takes for the device system to load and start the self-test, and the size of the capacitor C4 can be set to configure the watchdog trigger delay after reset. The trigger delay time calculation formula is shown in the following formula (1):

[0070] tWD_extended (ms) = 78.3 × Ccwd (nF) + 51 (ms) (1)

[0071] Where tWD_extended represents the trigger delay time, and Ccwd represents the value of capacitor C4. This ensures sufficient waiting time for the device system to complete self-test loading and start normally, and then start sending the dog feeding and clearing signals after normal operation.

[0072] Figure 6 FIG. 1 shows a schematic diagram of another control circuit provided by the present invention. As a possible implementation method, refer to Figure 6 As shown, Figure 5 The difference of the control circuit shown is that the burning and debugging interface module 11 is a serial debugging interface SW, which includes an interface power supply VBUS and SW data SWDIO, a clock SWCLK, a debug SWO and a reset NRST signal. The interface power supply VBUS is connected to the filter capacitor C5 and the electrostatic protection unit ED1. One end of the filter capacitor C5 and the electrostatic protection unit ED1 is connected to the common ground GND. The SW data SWDIO, the clock SWCLK, the debug SWO and the reset NRST signal are connected to the MCU / CPU or the CPU for program burning test and debugging.

[0073] It should be noted that Figure 6 The control circuit shown is Figure 5 The functions of the control circuits shown are the same, and the process of automatic switching of the reset circuit is also basically the same, which will not be described in detail here.

[0074] Figure 7 FIG. 1 shows a schematic diagram of another control circuit provided by the present invention. As a possible implementation method, refer to Figure 7 As shown, Figure 5 The difference between the control circuit shown is that the burning and debugging interface module 11 is a joint test working group JTAG, which includes an interface power supply VBUS and JTAG data (TDI, TDO), a clock TCK, a switch TMS and a reset TRST, NRST signal. The interface power supply VBUS is connected to the filter capacitor C5 and the electrostatic protection unit ED1. One end of the filter capacitor C5 and the electrostatic protection unit ED1 is connected to the common ground GND. The JTAG data TDI, TDO, a clock TCK, a switch TMS and a reset TRST, NRST signal are connected to the MCU / CPU or CPU for program burning test and debugging.

[0075] It should be noted that Figure 7 The control circuit shown is Figure 5 The functions of the control circuits shown are the same, and the process of automatic switching of the reset circuit is also basically the same, which will not be described in detail here.

[0076] Figure 8 FIG. 1 shows a schematic diagram of another control circuit provided by the present invention. As a possible implementation method, refer to Figure 8 As shown, Figure 5 The difference of the control circuit shown is that the burning and debugging interface module 11 is a universal asynchronous receiver and transmitter UART, which includes an interface power supply VBUS and UART data UART_RX and UART_TX signals. The interface power supply VBUS is connected to the filter capacitor C5 and the electrostatic protection unit ED1. One end of the filter capacitor C5 and the electrostatic protection unit ED1 is connected to the common ground GND, and the UART data UART_RX and UART_TX signals are connected to the MCU / CPU or CPU for program burning, testing and debugging.

[0077] It should be noted that Figure 8 The control circuit shown is Figure 5 The functions of the control circuits shown are the same, and the process of automatic switching of the reset circuit is also basically the same, which will not be described in detail here.

[0078] Figure 9 FIG. 1 shows a schematic diagram of another control circuit provided by the present invention. As a possible implementation method, refer to Figure 9 As shown, Figure 5The difference of the control circuit shown is that the electronic switch module 12 takes a relay as an example, and by using a relay ( Figure 9 RE1) shown in FIG replaces the analog electronic switch U1 to implement automatic switching of the reset circuit.

[0079] Optionally, the interface power supply VBUS of the burning and debugging interface module (J1) is connected to the resistor R1 and one pin of the control end of the relay RE1 through the resistor R2, the other pin of the control end of the relay RE1 and the other end of the resistor R1 are connected to the common ground GND, the timeout output pin nWDO of the watchdog circuit reset monitoring chip U2 is connected to the common COM pin of the relay RE1, and the reset input pin nmr of the watchdog circuit reset monitoring chip U2 is connected to the NC pin of the relay RE1.

[0080] It should be noted that Figure 9 The control circuit shown is Figure 5 The functions of the control circuits shown are the same, and the process of automatic switching of the reset circuit is also basically the same, which will not be described in detail here.

[0081] Figure 10 FIG. 1 shows a schematic diagram of another control circuit provided by the present invention. As a possible implementation method, refer to Figure 10 As shown, Figure 6 The difference of the control circuit shown is that the electronic switch module 12 takes a relay as an example, and by using a relay ( Figure 10 RE1) shown in FIG replaces the analog electronic switch U1 to implement automatic switching of the reset circuit.

[0082] It should be noted that Figure 10 The control circuit shown is Figure 6 The functions of the control circuits shown are the same, and the process of automatic switching of the reset circuit is also basically the same, which will not be described in detail here.

[0083] Figure 11 FIG. 1 shows a schematic diagram of another control circuit provided by the present invention. As a possible implementation method, refer to Figure 11 As shown, Figure 7 The difference of the control circuit shown is that the electronic switch module 12 takes a relay as an example, and by using a relay ( Figure 11 RE1) shown in FIG replaces the analog electronic switch U1 to implement automatic switching of the reset circuit.

[0084] It should be noted that Figure 11 The control circuit shown is Figure 7 The functions of the control circuits shown are the same, and the process of automatic switching of the reset circuit is also basically the same, which will not be described in detail here.

[0085] Figure 12 FIG. 1 shows a schematic diagram of another control circuit provided by the present invention. As a possible implementation method, refer to Figure 12 As shown, Figure 8 The difference of the control circuit shown is that the electronic switch module 12 takes a relay as an example, and by using a relay ( Figure 12 RE1) shown in FIG replaces the analog electronic switch U1 to implement automatic switching of the reset circuit.

[0086] It should be noted that Figure 12 The control circuit shown is Figure 8 The functions of the control circuits shown are the same, and the process of automatic switching of the reset circuit is also basically the same, which will not be described in detail here.

[0087] Based on the control circuit for controlling the switching of the reset circuit for device programming and debugging provided by the utility model of the present application, the entire reset circuit switching process is fully automatic and has the following characteristics:

[0088] (1) No need to develop additional burning adapter boards and reserve special interfaces.

[0089] (2) Compatible with devices connected via USB, JTAG, SW, UART and other interfaces for programming, testing, debugging and upgrading.

[0090] (3) When the MCU / CPU or CPU is in the no-program state and is connected to the device through an interface such as USB, JTAG, SW, or UART for programming, debugging, upgrading, etc., the electronic switch automatically switches to shield the reset circuit.

[0091] (4) When the MCU / CPU or CPU is in normal operation, the watchdog will not reset the program when testing and debugging through the interface, which will affect the test and debugging.

[0092] (5) After the program is burned, tested and debugged, there is no need for software to control the watchdog to start. Unplug the interface line and the watchdog will automatically start working normally.

[0093] (6) During the reset startup process, the delay time of the watchdog reset circuit is adjustable to ensure the normal startup time of the equipment system loading and self-test.

[0094] (7) The circuit design principle is simple and easy to understand, highly versatile and easy to use.

[0095] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A control circuit for device burning and debugging, characterized in that: The control circuit includes: a reset module, a burning and debugging interface module, an electronic switch module and a level control module; The first input end of the electronic switch module is connected to the output end of the programming and debugging interface module, the first output end of the electronic switch module is connected to the first input end of the reset module and one end of the level control module, the second input end of the electronic switch module is connected to the first output end of the reset module, and the other end of the level control module is used to connect to a first power supply, and the voltage of the first power supply is a first voltage; The burning and debugging interface module is used to output a second voltage to the first input terminal of the electronic switch module, and the first voltage is different from the second voltage; The level control module is used to output a high level signal to the first input terminal of the reset module; The electronic switch module is configured to disconnect the first output terminal of the electronic switch module from the second input terminal of the electronic switch module under the action of the second voltage, so that the reset module does not output a reset signal.

2. The control circuit according to claim 1, wherein: The electronic switch module includes: an electronic switch unit, a first resistor, a second resistor and a first capacitor; One end of the first resistor is connected to the output end of the programming and debugging interface module, and the other end of the first resistor is connected to one end of the second resistor and the input end of the electronic switch unit; The other end of the second resistor is grounded; one end of the first capacitor is respectively connected to the power supply and the power supply end of the electronic switch unit, and the other end of the first capacitor is grounded; The first output end of the electronic switch unit is connected to the first input end of the reset module and one end of the level control module, and the second input end of the electronic switch unit is connected to the first output end of the reset module.

3. The control circuit according to claim 2, characterized in that: The electronic switch unit includes an analog electronic switch, the input end of the analog electronic switch serves as the first input end of the electronic switch unit, the common end of the analog electronic switch serves as the second input end of the electronic switch unit, and the normally closed end of the analog electronic switch serves as the first output end of the electronic switch unit.

4. The control circuit according to claim 2, characterized in that: The electronic switch unit includes a relay, an input end of the relay serves as a first input end of the electronic switch unit, a common end of the relay serves as a second input end of the electronic switch unit, and a normally closed end of the relay serves as a first output end of the electronic switch unit.

5. The control circuit according to claim 1, wherein: The programming and debugging interface module includes: a programming interface chip, a filter capacitor and an electrostatic protection unit; The output end of the programming interface chip is respectively connected to one end of the filter capacitor and one end of the electrostatic protection unit, and the other end of the filter capacitor and the other end of the electrostatic protection unit are respectively grounded. The filter capacitor is used to filter out high-frequency noise in the interface power supply of the programming and debugging interface module, and the electrostatic protection unit is used to reduce electrostatic discharge interference; One end of the filter capacitor or the electrostatic protection unit is connected to the first input end of the electronic switch module.

6. The control circuit according to claim 5, characterized in that: The burning interface chip includes any one of the following: universal serial bus, serial debug interface, joint test working group, universal asynchronous receiver and transmitter.

7. The control circuit according to claim 1, wherein: The reset module includes a watchdog reset circuit, a timeout output pin of the watchdog reset circuit serves as a first output end of the reset module, and a reset input pin of the watchdog reset circuit serves as a first input end of the reset module.

8. The control circuit according to claim 7, characterized in that: The watchdog reset circuit also includes a timeout input pin, which is connected to one end of a second capacitor, the other end of which is grounded, and the second capacitor is used to control the watchdog trigger delay after the watchdog reset circuit is reset.

9. The control circuit according to claim 7, characterized in that: The watchdog reset circuit further includes a watchdog feeding input pin, wherein the watchdog feeding input pin is connected to one end of a third resistor, and the other end of the third resistor is connected to a feeding signal pin of a peripheral circuit; The watchdog reset circuit also includes a reset signal output pin, which is connected to one end of a fourth resistor, the other end of the fourth resistor is connected to the reset pin of the peripheral circuit, and the reset signal output pin is connected to one end of a third capacitor, the other end of the third capacitor is grounded.

10. The control circuit according to claim 1, wherein: The control circuit also includes a reset button, one end of which is grounded, and the other end of which is connected to one end of a fifth resistor, and the other end of which is respectively connected to the first input end of the reset module and one end of the level control module.

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