Raised cosine pulse forming circuit

Abstract

The utility model discloses a raised cosine pulse forming circuit which comprises a pulse shaping circuit, the output end of the pulse shaping circuit is respectively connected with a rising edge oscillating circuit and a falling edge discharging circuit, and the output end of the rising edge oscillating circuit and the output end of the falling edge discharging circuit are jointly connected with a high-voltage large-current driving circuit. And the rising edge oscillating circuit is connected with the falling edge discharging circuit. According to the raised cosine pulse forming circuit disclosed by the utility model, the problem of deformation of pulse waveform output in the prior art is solved.

Description

Technical Field

[0001] The utility model belongs to the technical field of aviation radio navigation and ranging equipment, and particularly relates to a raised cosine pulse forming circuit. Background Art

[0002] In aviation radio navigation and measurement systems, transponders, ADS-B receivers, and rangefinders all operate on radio signals with frequencies around 1 GHz. This frequency is crucial for the entire aviation sector. Furthermore, 1 GHz signals have long transmission distances and are less susceptible to interference from sky and ground waves. Based on the wavelength principle, these transmitting and receiving antennas are compact and highly efficient, making them widely used on civil and general aviation aircraft. Traditional radio navigation equipment typically generates modulated pulses by controlling digital-to-analog converter chips, resulting in complex circuitry and high costs. The output pulse waveform can only be pre-configured in software, making it impossible to adaptively optimize and improve subsequent distortion caused by environmental changes. This, in practice, affects the measurement accuracy of the navigation equipment.

[0003] The current mainstream approach is to use a digital processing chip to drive a parallel DA conversion chip to generate a fixed-shape raised cosine pulse signal. The problem with this approach is that the pulse is fixed. During debugging, the pulse shape generated by the DA will be deformed after passing through the subsequent driver. Since the subsequent driver circuit has a certain degree of discreteness, the final output pulse consistency is poor. In addition, this approach has high requirements for the DA chip, and the cost of the entire circuit cannot be controlled. Utility Model Content

[0004] The purpose of the utility model is to provide a raised cosine pulse forming circuit, which solves the problem of deformation of pulse waveform output in the prior art.

[0005] The technical solution adopted by the utility model is that the raised cosine pulse forming circuit includes a pulse shaping circuit, the output end of the pulse shaping circuit is respectively connected to a rising edge oscillation circuit and a falling edge discharge circuit, the output ends of the rising edge oscillation circuit and the falling edge discharge circuit are commonly connected to a high voltage and high current driving circuit, and the rising edge oscillation circuit is connected to the falling edge discharge circuit.

[0006] The utility model is also characterized in that:

[0007] The pulse shaping circuit includes a filter capacitor and a level logic conversion circuit. The level logic conversion circuit includes a first inverter. The output end of the filter capacitor is connected to the input end of the first inverter. The output end of the first inverter is respectively connected to the second inverter and the third inverter. The output end of the second inverter is connected to the rising edge oscillation circuit, and the third inverter is connected to the falling edge discharge circuit.

[0008] The filter capacitor uses the ceramic capacitor CT41-0402-X7R-50V-104-M, and the level logic conversion circuit uses the chip SN74HC14DR.

[0009] The rising edge oscillation circuit includes a bias resistor, an input end of the bias resistor is connected to the output end of the second inverter, an output end of the bias resistor is connected to a variable resistor, a fixed end of the variable resistor is sequentially connected to a first resistor and a power supply VCC, the bias resistor is also connected to a first transistor, an input end of the bias resistor is connected to the base of the first transistor, an output end of the bias resistor is connected to the collector of the first transistor, an emitter of the first transistor is connected to a ground end via a second resistor, an emitter of the first transistor is also connected to an oscillation inductor, an output end of the oscillation inductor is connected to an oscillation capacitor, an output end of the oscillation capacitor is connected to the collector of the first transistor, and an output end of the oscillation inductor is respectively connected to a falling edge discharge circuit and a high voltage and high current drive circuit.

[0010] The first transistor uses the 2N4917 transistor, the oscillation inductor uses the CDRH63-471K inductor, and the oscillation capacitor uses the CC41-0805-CG-200V-560-J capacitor.

[0011] The falling edge discharge circuit includes a capacitor and a third resistor, the output end of the third inverter is respectively connected to the capacitor and the input end of the third resistor, the output end of the capacitor and the third resistor is commonly connected to a second transistor, the emitter of the second transistor is connected to the ground end, the collector of the second transistor is respectively connected to the output end of the oscillating inductor and the high-voltage and high-current drive circuit, the output end of the third resistor and the base of the second transistor are commonly connected to a fourth resistor, and the output end of the fourth resistor is connected to the ground end.

[0012] The second transistor is MMBT5550.

[0013] The high-voltage and high-current driving circuit includes a MOS tube, the gate of the MOS tube is respectively connected to the output end of the oscillation inductor and the collector of the second transistor, the drain of the MOS tube is connected to the high-voltage power supply, the electrode of the MOS tube outputs a pulse signal, and the collector of the second transistor and the gate of the MOS tube are commonly connected to a fifth resistor.

[0014] The MOS tube is IRF540NSPBF.

[0015] The beneficial effects of the utility model are:

[0016] (1) The raised cosine pulse forming circuit and rectangular pulse shaping circuit provided by the present invention adopt high-speed integrated circuits, which reduce the circuit volume and power consumption, and have better shaping and burr elimination functions for rectangular pulses of different pulse widths.

[0017] (2) The raised cosine pulse forming circuit provided by the present invention utilizes a design method combining a transistor and an LC circuit. By adjusting the specific parameters of the LC circuit, different raised cosine pulse widths can be achieved. While achieving the required functions, this reduces circuit design costs, simplifies circuit principles and device types, improves the overall operational reliability of the circuit, and provides good circuit environmental adaptability.

[0018] (3) The raised cosine pulse forming circuit provided by the present invention and the high voltage and high current driving circuit use a new type of high current MOS tube design, which ensures the demand for high current driving capability in the subsequent circuit use. The MOS tube has a small on-resistance, which ensures that the circuit has low energy consumption and low heat generation when working for a long time. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic structural diagram of the raised cosine pulse forming circuit of the utility model;

[0020] Figure 2 This is a circuit diagram of a raised cosine pulse forming circuit of the utility model;

[0021] Figure 3 This is a working diagram of the pulse shaping circuit of the utility model;

[0022] Figure 4 This is a working diagram of the rising edge oscillation circuit and the falling edge discharge circuit of the utility model;

[0023] Figure 5 This is a working flow chart of the high voltage and high current drive circuit of the utility model.

[0024] In the figure, 10. Pulse shaping circuit, 101, filter capacitor, 102, first inverter, 103, second inverter, 104, third inverter; 20. Rising edge oscillation circuit, 201, bias resistor, 202, variable resistor, 203, first resistor, 204, first transistor, 205. Second resistor, 206, oscillation inductor, 207, oscillation capacitor; 30. Falling edge discharge circuit, 301, capacitor, 302, third resistor, 303, second transistor, 304, fourth resistor; 40. High voltage and high current drive circuit, 401, MOS tube, 402, fifth resistor. DETAILED DESCRIPTION

[0025] The present invention will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0026] The utility model provides a raised cosine pulse forming circuit, such as Figure 1As shown, it includes a pulse shaping circuit 10, the output end of the pulse shaping circuit 10 is connected to a rising edge oscillation circuit 20 and a falling edge discharge circuit 30 respectively, the output end of the rising edge oscillation circuit 20 and the falling edge discharge circuit 30 are commonly connected to a high voltage and high current drive circuit 40, the rising edge oscillation circuit 20 is connected to the falling edge discharge circuit 30, as shown in FIG. Figure 2 and Figure 3 As shown, the pulse shaping circuit 10 includes a filter capacitor 101 and a level logic conversion circuit, the level logic conversion circuit includes a first inverter 102, the output end of the filter capacitor 101 is connected to the input end of the first inverter 102, the output end of the first inverter 102 is connected to the second inverter 103 and the third inverter 104 respectively, the output end of the second inverter 103 is connected to the rising edge oscillation circuit 20, and the third inverter 104 is connected to the falling edge discharge circuit 30; Figure 2 and Figure 4 As shown, the rising edge oscillation circuit 20 includes a bias resistor 201, the input end of the bias resistor 201 is connected to the output end of the second inverter 103, the output end of the bias resistor 201 is connected to the variable resistor 202, the fixed end of the variable resistor 202 is sequentially connected to the first resistor 203 and the power supply VCC, the bias resistor 201 is further connected to the first transistor 204, the input end of the bias resistor 201 is connected to the base of the first transistor 204, the output end of the bias resistor 201 is connected to the collector of the first transistor 204, the emitter of the first transistor 204 is connected to the ground terminal 50 through the second resistor 205, the emitter of the first transistor 204 is further connected to the oscillation inductor 206, the output end of the oscillation inductor 206 is connected to the oscillation capacitor 207, the output end of the oscillation capacitor 207 is connected to the first transistor 204. The collector of the first transistor 204 is connected, the output end of the oscillating inductor 206 is connected to the falling edge discharge circuit 30 and the high voltage and high current drive circuit 40 respectively, the falling edge discharge circuit 30 includes a capacitor 301 and a third resistor 302, the output end of the third inverter 104 is connected to the input end of the capacitor 301 and the third resistor 302 respectively, the output end of the capacitor 301 and the third resistor 302 are commonly connected to the second transistor 303, the emitter of the second transistor 303 is connected to the ground terminal 50, the collector of the second transistor 303 is respectively connected to the output end of the oscillating inductor 206 and the high voltage and high current drive circuit 40, the output end of the third resistor 302 and the base of the second transistor 303 are commonly connected to the fourth resistor 304, and the output end of the fourth resistor 304 is connected to the ground terminal 50. Figure 2 and Figure 5 As shown, the high-voltage and high-current driving circuit 40 includes a MOS transistor 401. The gate of the MOS transistor 401 is respectively connected to the output end of the oscillating inductor 206 and the collector of the second transistor 303. The drain of the MOS transistor 401 is connected to a high-voltage power supply. The gate of the MOS transistor 401 outputs a pulse signal. The collector of the second transistor 303 and the gate of the MOS transistor 401 are commonly connected to a fifth resistor 402.

[0027] The working principle of the raised cosine pulse forming circuit provided in this embodiment is as follows:

[0028] The input rectangular pulse signal enters the pulse shaping circuit 10, which performs de-grossing filtering and level conversion control on the rectangular pulse signal. The processed rectangular pulse signal is divided into two paths. One path enters the rising edge oscillator circuit 20, where the pulse level is controlled and the time constant of the rising cosine pulse leading edge is controlled according to the rectangular pulse leading edge. The other path of processed rectangular pulse passes through the falling edge discharge circuit 30, where the rectangular pulse is used to control the operation of the transistors in the discharge circuit and the time constant of the falling edge of the raised cosine pulse. After the output signal of the rising edge oscillator circuit 20 and the output signal of the falling edge discharge circuit 30 are merged, a complete raised cosine pulse signal is formed. This signal is then sent to the high voltage and high current drive circuit 40 to enhance the drive capability, thereby increasing the output raised cosine pulse voltage and current drive capability to meet the requirements of subsequent circuits.

[0029] Example 1

[0030] This embodiment provides a raised cosine pulse forming circuit, such as Figure 1-5 As shown, it includes a pulse shaping circuit 10, the output end of the pulse shaping circuit 10 is respectively connected to a rising edge oscillation circuit 20 and a falling edge discharge circuit 30, the output ends of the rising edge oscillation circuit 20 and the falling edge discharge circuit 30 are commonly connected to a high voltage and high current drive circuit 40, and the rising edge oscillation circuit 20 is connected to the falling edge discharge circuit 30.

[0031] Example 2

[0032] This embodiment provides a raised cosine pulse forming circuit, such as Figure 1-5As shown, it includes a pulse shaping circuit 10, the output end of the pulse shaping circuit 10 is connected to the rising edge oscillation circuit 20 and the falling edge discharge circuit 30 respectively, the output end of the rising edge oscillation circuit 20 and the falling edge discharge circuit 30 are commonly connected to the high voltage and high current drive circuit 40, the rising edge oscillation circuit 20 is connected to the falling edge discharge circuit 30, the pulse shaping circuit 10 includes a filter capacitor 101 and a level logic conversion circuit, the level logic conversion circuit includes a first inverter 102, the output end of the filter capacitor 101 is connected to the input end of the first inverter 102, the first inverter 1 The output end of the second inverter 102 is connected to the second inverter 103 and the third inverter 104 respectively. The output end of the second inverter 103 is connected to the rising edge oscillation circuit 20. The third inverter 104 is connected to the falling edge discharge circuit 30. The rising edge oscillation circuit 20 includes a bias resistor 201. The input end of the bias resistor 201 is connected to the output end of the second inverter 103. The output end of the bias resistor 201 is connected to a variable resistor 202. The fixed end of the variable resistor 202 is sequentially connected to the first resistor 203 and the power supply VCC. The bias resistor 201 is also connected to a first transistor 204. The bias resistor The input end of the resistor 201 is connected to the base of the first transistor 204, the output end of the bias resistor 201 is connected to the collector of the first transistor 204, the emitter of the first transistor 204 is connected to the ground terminal 50 through the second resistor 205, the emitter of the first transistor 204 is also connected to the oscillation inductor 206, the output end of the oscillation inductor 206 is connected to the oscillation capacitor 207, the output end of the oscillation capacitor 207 is connected to the collector of the first transistor 204, the output end of the oscillation inductor 206 is connected to the falling edge discharge circuit 30 and the high voltage and high current drive circuit 40 respectively, the falling edge discharge circuit 30 The circuit includes a capacitor 301 and a third resistor 302. The output end of the third inverter 104 is connected to the input end of the capacitor 301 and the input end of the third resistor 302 respectively. The output ends of the capacitor 301 and the third resistor 302 are commonly connected to a second transistor 303. The emitter of the second transistor 303 is connected to the ground terminal 50. The collector of the second transistor 303 is respectively connected to the output end of the oscillating inductor 206 and the high-voltage and high-current driving circuit 40. The output end of the third resistor 302 and the base of the second transistor 303 are commonly connected to a fourth resistor 304. The output end of the fourth resistor 304 is connected to the ground terminal 50.

[0033] Example 3

[0034] This embodiment provides a raised cosine pulse forming circuit, such as Figure 1-5As shown, it includes a pulse shaping circuit 10, the output end of the pulse shaping circuit 10 is respectively connected to the rising edge oscillation circuit 20 and the falling edge discharge circuit 30, the output ends of the rising edge oscillation circuit 20 and the falling edge discharge circuit 30 are commonly connected to the high voltage and high current drive circuit 40, the rising edge oscillation circuit 20 is connected to the falling edge discharge circuit 30, the pulse shaping circuit 10 includes a filter capacitor 101 and a level logic conversion circuit, the level logic conversion circuit includes a first inverter 102, the output end of the filter capacitor 101 is connected to the input end of the first inverter 102, the output end of the first inverter 102 is respectively connected to the second inverter 103 and the third inverter 104, the second inverter The output end of the bias resistor 201 is connected to the rising edge oscillation circuit 20, the third inverter 104 is connected to the falling edge discharge circuit 30, the rising edge oscillation circuit 20 includes a bias resistor 201, the input end of the bias resistor 201 is connected to the output end of the second inverter 103, the output end of the bias resistor 201 is connected to the variable resistor 202, the fixed end of the variable resistor 202 is sequentially connected to the first resistor 203 and the power supply VCC, the bias resistor 201 is also connected to the first transistor 204, the input end of the bias resistor 201 is connected to the base of the first transistor 204, the output end of the bias resistor 201 is connected to the collector of the first transistor 204, and the emitter of the first transistor 204 is connected to the second resistor 205. The first transistor 204 is connected to the ground terminal 50. The emitter of the first transistor 204 is also connected to the oscillating inductor 206. The output end of the oscillating inductor 206 is connected to the oscillating capacitor 207. The output end of the oscillating capacitor 207 is connected to the collector of the first transistor 204. The output end of the oscillating inductor 206 is connected to the falling edge discharge circuit 30 and the high voltage and high current drive circuit 40 respectively. The falling edge discharge circuit 30 includes a capacitor 301 and a third resistor 302. The output end of the third inverter 104 is connected to the input end of the capacitor 301 and the third resistor 302 respectively. The output end of the capacitor 301 and the third resistor 302 is commonly connected to the second transistor 303. The emitter of the second transistor 303 is connected to the ground terminal 50. The collector of the second transistor 303 is connected to the output end of the oscillating inductor 206 and the high-voltage and high-current driving circuit 40, respectively. The output end of the third resistor 302 and the base of the second transistor 303 are commonly connected to the fourth resistor 304. The output end of the fourth resistor 304 is connected to the ground terminal 50. The high-voltage and high-current driving circuit 40 includes a MOS transistor 401. The gate of the MOS transistor 401 is respectively connected to the output end of the oscillating inductor 206 and the collector of the second transistor 303. The drain of the MOS transistor 401 is connected to a high-voltage power supply. The gate of the MOS transistor 401 outputs a pulse signal. The collector of the second transistor 303 and the gate of the MOS transistor 401 are commonly connected to the fifth resistor 402.

[0035] After the pulse shaping circuit 10, the filter capacitor 101 adopts the CT41-0402-X7R-50V-104-M model, and the gross profit filtering is processed, the signal is converted by the level logic conversion circuit and the pulse signal is output. The level logic conversion circuit adopts the chip SN74HC14DR. The pulse signal is input to the rising edge oscillation circuit 20. The first transistor in the rising edge oscillation circuit 20 uses the 2N4917 model, the oscillation inductor 206 uses the CDRH63-471K model, and the oscillation capacitor 207 uses

[0036] Model CC41-0805-CG-200V-560-J, rising edge oscillator circuit 20 generates a leading edge time constant of a raised cosine pulse.

[0037] Another input pulse signal is input into the falling edge discharge circuit 30 and passes through the RC delay circuit. The RC delay circuit mainly consists of a third resistor 302 using RⅡ-15(0805)-0.1W-202-F and a capacitor 301 using CC41-0603-CG-50V-682-J. The delay is about 2 microseconds. The delayed signal controls the conduction of the second transistor MMBT5550 to form a pressure relief loop, controlling the time of the falling edge of the pulse. The output of the rising edge oscillation circuit 20 and the output of the falling edge discharge circuit 30 are mixed and sent to the high-voltage and high-current drive circuit 40. The high-voltage and high-current drive circuit mainly uses the control MOS tube IRF540NSPBF to increase the pulse voltage and drive current without deforming the raised cosine pulse.

[0038] In addition to the models listed in Example 3, the raised cosine pulse forming circuit provided by the present invention can also utilize other models of circuits available in the prior art that can achieve the functions described in the present invention. For example, the inductance and capacitance values of the rising-edge oscillator circuit can be selected to control the rise time of the raised cosine pulse, and the resistance and capacitance of the RC circuit in the falling-edge discharge circuit can be modified to adjust the fall time of the raised cosine pulse and control the width of the raised cosine pulse.

Claims

1. A raised cosine pulse forming circuit, characterized in that: The invention comprises a pulse shaping circuit (10), wherein the output end of the pulse shaping circuit (10) is respectively connected to a rising edge oscillation circuit (20) and a falling edge discharge circuit (30), the output ends of the rising edge oscillation circuit (20) and the falling edge discharge circuit (30) are commonly connected to a high voltage and high current drive circuit (40), and the rising edge oscillation circuit (20) is connected to the falling edge discharge circuit (30).

2. The raised cosine pulse forming circuit according to claim 1, wherein: The pulse shaping circuit (10) comprises a filter capacitor (101) and a level logic conversion circuit, wherein the level logic conversion circuit comprises a first inverter (102), an output end of the filter capacitor (101) is connected to an input end of the first inverter (102), an output end of the first inverter (102) is respectively connected to a second inverter (103) and a third inverter (104), an output end of the second inverter (103) is connected to a rising edge oscillation circuit (20), and the third inverter (104) is connected to a falling edge discharge circuit (30).

3. The raised cosine pulse forming circuit according to claim 2, wherein: The filter capacitor is a ceramic capacitor CT41-0402-X7R-50V-104-M, and the level logic conversion circuit is a chip SN74HC14DR.

4. The raised cosine pulse forming circuit according to claim 2, wherein: The rising edge oscillation circuit (20) comprises a bias resistor (201), the input end of the bias resistor (201) is connected to the output end of the second inverter (103), the output end of the bias resistor (201) is connected to a variable resistor (202), the fixed end of the variable resistor (202) is sequentially connected to a first resistor (203) and a power supply VCC, the bias resistor (201) is further connected to a first triode (204), the input end of the bias resistor (201) is connected to the base of the first triode (204), and the output end of the bias resistor (201) is connected to the base of the first triode (204). The collector of the first transistor (204) is connected, the emitter of the first transistor (204) is connected to the ground terminal (50) via the second resistor (205), the emitter of the first transistor (204) is further connected to an oscillating inductor (206), the output end of the oscillating inductor (206) is connected to an oscillating capacitor (207), the output end of the oscillating capacitor (207) is connected to the collector of the first transistor (204), and the output end of the oscillating inductor (206) is respectively connected to a falling edge discharge circuit (30) and a high voltage and high current drive circuit (40).

5. The raised cosine pulse forming circuit according to claim 4, wherein: The first triode (204) is a 2N4917 transistor, the oscillation inductor (206) is a CDRH63-471K inductor, and the oscillation capacitor (207) is a CC41-0805-CG-200V-560-J capacitor.

6. The raised cosine pulse forming circuit according to claim 4, wherein: The falling edge discharge circuit (30) comprises a capacitor (301) and a third resistor (302); the output end of the third inverter (104) is respectively connected to the input ends of the capacitor (301) and the third resistor (302); the output ends of the capacitor (301) and the third resistor (302) are commonly connected to a second triode (303); the emitter of the second triode (303) is connected to the ground end (50); the collector of the second triode (303) is respectively connected to the output end of the oscillating inductor (206) and the high voltage and high current driving circuit (40); the output end of the third resistor (302) and the base of the second triode (303) are commonly connected to a fourth resistor (304); the output end of the fourth resistor (304) is connected to the ground end (50).

7. The raised cosine pulse forming circuit according to claim 6, wherein: The second transistor (303) is a MMBT5550 transistor.

8. The raised cosine pulse forming circuit according to claim 6, wherein: The high-voltage and high-current driving circuit (40) comprises a MOS transistor (401), the gate of the MOS transistor (401) being connected to the output end of the oscillating inductor (206) and the collector of the second triode (303), the drain of the MOS transistor (401) being connected to a high-voltage power supply, the source of the MOS transistor (401) outputting a pulse signal, and the collector of the second triode (303) and the gate of the MOS transistor (401) being commonly connected to a fifth resistor (402).

9. The raised cosine pulse forming circuit according to claim 8, wherein: The MOS tube (401) is of the IRF540NSPBF model.

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