Thermal control circuit of satellite load integrated management system

Abstract

The utility model provides a thermal control circuit of a satellite load integrated management system. The thermal control circuit comprises an interface circuit, an optical coupling circuit, a triode Q1, a PMOS tube Q2, an NMOS tube Q3 electrically connected with the optical coupling circuit, a heating sheet electrically connected with the PMOS tube Q2 and the NMOS tube Q3, and a fuse F1 electrically connected with the PMOS tube Q2, wherein the interface circuit, the optical coupling circuit, the triode Q1, the PMOS tube Q2, the NMOS tube Q3, the heating sheet and the fuse F1 are electrically connected in sequence. According to the utility model, the output of a thermal control signal is realized through the thermal control circuit, so that other load products of a satellite are ensured to work at a proper temperature. In the thermal control circuit, MOS tubes are subjected to backup design and are divided into an upper PMOS tube and a lower NMOS tube, the NMOS tubes are directly controlled through optocoupler output signals, and the PMOS tubes are indirectly controlled through signals adjusted by triodes. When the two MOS tubes are opened, the heating sheet and the thermal control power supply form a loop. Even if one of the PMOS transistor and the NMOS transistor is damaged, the thermal control circuit can still work normally, the satellite safety is guaranteed to the maximum extent, and the reliability of in-orbit autonomous operation of the satellite is effectively improved.

Description

Technical Field

[0001] The utility model relates to the technical field, in particular to a thermal control circuit of a satellite payload integrated management system. Background Art

[0002] In recent years, the demand for low-orbit small satellite applications has increased rapidly, and the number of satellites being developed has increased rapidly. Therefore, both ground-based satellite development and on-orbit operation management must improve the automation level and reliability of satellite operation control and reduce human intervention.

[0003] In the existing satellite payload integrated management system, the heating plate is only controlled by the MOS tube. Once the MOS is damaged, the thermal control circuit will be broken, and the heating plate will continue to heat, which cannot ensure the safety of the satellite and greatly reduces the reliability of the satellite payload integrated management system.

[0004] Therefore, a high-reliability thermal control circuit for a satellite payload integrated management system is needed. Summary of the Invention

[0005] The present invention aims to solve the problem of low reliability of thermal control circuits and provides a thermal control circuit for a satellite payload integrated management system. The present invention outputs thermal control signals through the thermal control circuit, thereby ensuring that other satellite payload products operate at an appropriate temperature. A backup design is provided for MOS tubes in the thermal control circuit, which are divided into an upper tube PMOS and a lower tube NMOS. The NMOS tube is directly controlled by an optocoupler output signal, while the PMOS tube is indirectly controlled by a signal adjusted by a transistor. When both MOS tubes are turned on, a loop is formed between the heater and the thermal control power supply. Even if one of the PMOS or NMOS tubes is damaged, the thermal control circuit can still operate normally, maximizing satellite safety and effectively improving the reliability of the satellite's autonomous operation in orbit.

[0006] The utility model provides a thermal control circuit for a satellite payload integrated management system, comprising an interface circuit, an optocoupler circuit, a triode Q1, a PMOS tube Q2, which are electrically connected in sequence, an NMOS tube Q3 electrically connected to the optocoupler circuit, a heating plate electrically connected to both the PMOS tube Q2 and the NMOS tube Q3, and a fuse F1 electrically connected to the PMOS tube Q2;

[0007] The interface circuit performs level conversion, the optocoupler circuit performs optical isolation and outputs a pull-up signal at the collector and a pull-down signal at the emitter. The base of the transistor Q1 and the gate of the NMOS transistor Q3 are both connected to the emitter of the optocoupler circuit. The collector and emitter of the transistor Q1 are both connected to the gate of the PMOS transistor Q2. The drain of the PMOS transistor Q2 and the drain of the NMOS transistor Q3 are both connected to the heating plate. One end of the fuse F1 is connected to the collector of the optocoupler circuit, and the other end is connected to the collector of the transistor Q1 and the source of the PMOS transistor Q2.

[0008] The thermal control circuit of a satellite payload integrated management system described in the present invention is, as a preferred embodiment, an interface circuit converts a 3.5V input voltage into N 5V output voltages and outputs them to an optocoupler circuit. The optocoupler circuit includes N sub-circuits, and the number of transistors Q1, PMOS tubes Q2, NMOS tubes Q3, heating plates and fuses F1 is N, and N≥2.

[0009] In the thermal control circuit of the satellite payload integrated management system described in the present invention, N is preferably 4.

[0010] In the thermal control circuit of the satellite payload integrated management system described in the utility model, as an optimal mode, a voltage divider resistor and a filter capacitor are connected in the optical coupling circuit.

[0011] The utility model discloses a thermal control circuit for a satellite payload integrated management system. As a preferred embodiment, a resistor R1 is connected between the pull-down signal output end of the optocoupler circuit and the base of the transistor Q1. One end of the fuse F1 is connected to the +42V thermal control input voltage, and the other end is connected to the collector of the transistor Q1 in sequence with resistors R2 and R3. A resistor R4 is connected between the resistors R2 and R3. The other end of the resistor R4 is connected to the resistor R5 and the gate of the PMOS transistor Q2. The emitter of the transistor Q1 is connected to the resistor R6. The other end of the resistor R6 is connected to the resistor R5, the end of the resistor R1 connected to the pull-down signal is also connected to the resistor R7, the other end of the resistor R7 is connected to the resistor R8 and the gate of the NMOS tube Q3, the other end of the resistor R8 is connected to the source of the resistor R6 and the NMOS tube Q3 and are all grounded, the source of the PMOS tube Q2 is connected to the fuse F1, the resistor R2, and the resistor R9, the drain of the PMOS tube Q2 is connected to the other end of the resistor R9 and then connected to the heating plate, and the drain of the NMOS tube Q3 is connected to the other end of the heating plate.

[0012] The thermal control circuit of the satellite payload integrated management system described in the present invention is preferably configured such that a resistor R10 is connected between the pull-up signal and the input end of the fuse F1, and a resistor R11 is further connected to the connection end of the resistor R10 and the pull-up signal, and the other end of the resistor R11 is grounded.

[0013] In the thermal control circuit of the satellite payload integrated management system described in the present invention, as an optimal mode, a resistor R12 is connected between the pull-down signal and the resistor R1, and the other end of the resistor R12 is grounded.

[0014] In the thermal control circuit of the satellite payload integrated management system described in the present invention, as an optimal mode, the source of the NMOS tube Q3 is connected to one end of the thermal control power supply negative voltage.

[0015] The thermal control circuit of the satellite payload integrated management system described in the present invention, as an optimal embodiment, further comprises an FPGA circuit that outputs a thermal control signal to the interface circuit.

[0016] The utility model has the following advantages:

[0017] This utility model uses a thermal control circuit to output thermal control signals, thereby ensuring that other satellite payloads operate at an appropriate temperature. The thermal control circuit incorporates a backup MOS transistor design, consisting of an upper PMOS transistor and a lower NMOS transistor. The NMOS transistor is directly controlled by an optocoupler output signal, while the PMOS transistor is indirectly controlled by a signal regulated by a transistor. When both MOS transistors are turned on, a loop is formed between the heater and the thermal control power supply. Even if either the PMOS or NMOS transistor fails, the thermal control circuit remains operational, maximizing satellite safety and effectively improving the reliability of the satellite's autonomous in-orbit operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The figure is a schematic diagram of a thermal control circuit for a satellite payload integrated management system;

[0019] Figure 2 This is an optocoupler circuit diagram for a thermal control circuit of a satellite payload integrated management system;

[0020] Figure 3 This is a connection circuit diagram of the transistor Q1, PMOS tube Q2, NMOS tube Q3, heating plate and fuse in the thermal control circuit of a satellite payload integrated management system.

[0021] Reference numerals:

[0022] 1. Interface circuit; 2. Optocoupler circuit; 3. Heating plate; 4. FPGA circuit. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0024] Example 1

[0025] like Figures 1 to 3 As shown, a thermal control circuit of a satellite payload integrated management system includes an interface circuit 1, an optocoupler circuit 2, a transistor Q1, and a PMOS transistor Q2 electrically connected in sequence, an NMOS transistor Q3 electrically connected to the optocoupler circuit 2, a heating plate 3 electrically connected to both the PMOS transistor Q2 and the NMOS transistor Q3, and a fuse F1 electrically connected to the PMOS transistor Q2;

[0026] The interface circuit 1 performs level conversion, the optocoupler circuit 2 performs optical isolation and outputs a pull-up signal at the collector and a pull-down signal at the emitter. The base of the transistor Q1 and the gate of the NMOS transistor Q3 are both connected to the emitter of the optocoupler circuit 2. The collector and emitter of the transistor Q1 are both connected to the gate of the PMOS transistor Q2. The drain of the PMOS transistor Q2 and the drain of the NMOS transistor Q3 are both connected to the heater 3. One end of the fuse F1 is connected to the collector of the optocoupler circuit 2, and the other end is connected to the collector of the transistor Q1 and the source of the PMOS transistor Q2.

[0027] Interface circuit 1 converts 3.5V input voltage into N-channel 5V output voltage and outputs it to optocoupler circuit 2. Optocoupler circuit 2 includes four sub-circuits, including four transistors Q1, four PMOS transistors Q2, four NMOS transistors Q3, four heaters 3, and four fuses F1.

[0028] Connect the voltage divider resistor and filter capacitor to the optocoupler circuit 2;

[0029] Resistor R1 is connected between the pull-down signal output end of the optocoupler circuit 2 and the base of the transistor Q1. One end of the fuse F1 is connected to the +42V thermal control input voltage, and the other end is connected to the collector of the transistor Q1, with resistors R2 and R3 connected in sequence. Resistor R4 is connected between resistors R2 and R3. The other end of resistor R4 is connected to resistor R5 and the gate of the PMOS transistor Q2. The emitter of the transistor Q1 is connected to resistor R6. The other end of resistor R6 is connected to resistor R5. The end of resistor R1 connected to the pull-down signal is also connected to resistor R7. The other end of resistor R7 is connected to resistor R8 and the gate of the NMOS transistor Q3. The other end of resistor R8 is connected to the source of resistor R6 and the source of the NMOS transistor Q3 and is grounded. The source of the PMOS transistor Q2 is connected to the fuse F1, resistor R2, and resistor R9. The drain of the PMOS transistor Q2 is connected to the other end of resistor R9 and then to the heater 3. The drain of the NMOS transistor Q3 is connected to the other end of the heater 3.

[0030] A resistor R10 is connected between the pull-up signal and the input end of the fuse F1. The connection end of the resistor R10 and the pull-up signal is also connected to a resistor R11. The other end of the resistor R11 is grounded.

[0031] A resistor R12 is connected between the pull-down signal and the resistor R1, and the other end of the resistor R12 is grounded;

[0032] The source of the NMOS tube Q3 is connected to the negative voltage terminal of the thermal control power supply;

[0033] It also includes an FPGA circuit 4 that outputs a thermal control signal to the interface circuit 1 .

[0034] In this embodiment, the model of the transistor Q1 is 3DK104C, the model of the PMOS transistor Q2 is LCS7382U3RH, the model of the NMOS transistor Q3 is LCS7591U3RH, the rated current of the fuse F1 is 2.1A, and the rated voltage is 125V. The resistance values ​​of the resistors R1, R3, R4, and R7 are all 10 ohms, the resistance value of the resistor R2 is 22,000 ohms, the resistance value of the resistor R5 is 1000 kiloohms, the resistance value of the resistor R6 is 30 kiloohms, the resistance value of the resistor R7 is 10 ohms, the resistance value of the resistor R8 is 20 kiloohms, the resistance value of the resistor R9 is an RMZ2012BH20 resistor, the resistance value of the resistor R10 is 30 kiloohms, the resistance value of the resistor R11 is 20 kiloohms, and the resistance value of the resistor R12 is 56 kiloohms.

[0035] The present invention provides a thermal control circuit for a satellite payload integrated management system. The circuit primarily includes an interface circuit 1, an optocoupler circuit 2, a MOS transistor Q1, a PMOS transistor Q2, an NMOS transistor Q3, a heater 3, an FPGA circuit 4, and peripheral driver circuits. Each thermal control circuit has an independent fuse for isolation protection. During thermal control operation, the FPGA 4 outputs a thermal control signal for the satellite payload integrated management system. This signal is converted by the interface chip 1 and then input into the optocoupler circuit 2. The optocoupler 2 isolates the control power from the thermal control power. The signal output from the optocoupler 2 is used to control the subsequent MOS transistors to turn on or off. The MOS transistors are designed as backup devices and are divided into an upper PMOS transistor and a lower NMOS transistor. The NMOS transistor Q3 is directly controlled by the output signal of the optocoupler 2, while the PMOS transistor Q2 is indirectly controlled by a signal adjusted by the transistor. When both MOS transistors are turned on, the heater 3 and the thermal control power supply form a loop.

[0036] The above is only a preferred specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any technician familiar with the technical field within the technical scope disclosed by the present invention can make equivalent replacements or changes based on the technical solution and utility model concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A thermal control circuit for a satellite payload integrated management system, characterized by: It comprises an interface circuit (1), an optocoupler circuit (2), a triode Q1, a PMOS tube Q2, which are electrically connected in sequence, an NMOS tube Q3 electrically connected to the optocoupler circuit (2), a heating plate (3) electrically connected to both the PMOS tube Q2 and the NMOS tube Q3, and a fuse F1 electrically connected to the PMOS tube Q2; The interface circuit (1) performs level conversion, the optocoupler circuit (2) performs optical isolation and outputs a pull-up signal at the collector and a pull-down signal at the emitter, the base of the transistor Q1 and the gate of the NMOS transistor Q3 are both connected to the emitter of the optocoupler circuit (2), the collector and emitter of the transistor Q1 are both connected to the gate of the PMOS transistor Q2, the drain of the PMOS transistor Q2 and the drain of the NMOS transistor Q3 are both connected to the heating plate (3), one end of the fuse F1 is connected to the collector of the optocoupler circuit (2), and the other end is connected to the collector of the transistor Q1 and the source of the PMOS transistor Q2.

2. The thermal control circuit of the satellite payload integrated management system according to claim 1, characterized in that: The interface circuit (1) converts a 3.5V input voltage into N 5V output voltages and outputs them to the optocoupler circuit (2). The optocoupler circuit (2) includes N sub-circuits, and the number of transistors Q1, PMOS transistors Q2, NMOS transistors Q3, the heating plates (3) and fuses F1 is N, and N≥2.

3. The thermal control circuit of the satellite payload integrated management system according to claim 2, characterized in that: N is 4.

4. The thermal control circuit of the satellite payload integrated management system according to claim 1, characterized in that: The optical coupling circuit (2) is connected to a voltage dividing resistor and a filter capacitor.

5. The thermal control circuit of the satellite payload integrated management system according to claim 1, characterized in that: A resistor R1 is connected between the pull-down signal output end of the optical coupler circuit (2) and the base of the transistor Q1; one end of the fuse F1 is connected to the +42V thermal control input voltage; the other end is connected to the collector of the transistor Q1; resistors R2 and R3 are connected in sequence; resistor R4 is connected between resistors R2 and R3; the other end of resistor R4 is connected to resistor R5 and the gate of the PMOS transistor Q2; the emitter of the transistor Q1 is connected to resistor R6; the other end of resistor R6 is connected to resistor R5; the end of resistor R1 connected to the pull-down signal is also connected to resistor R7; the other end of resistor R7 is connected to resistor R8 and the gate of the NMOS transistor Q3; the other end of resistor R8 is connected to the source of resistor R6 and the source of the NMOS transistor Q3 and is grounded; the source of the PMOS transistor Q2 is connected to the fuse F1, resistor R2, and resistor R9; the drain of the PMOS transistor Q2 is connected to the other end of resistor R9 and then connected to the heating plate (3); the drain of the NMOS transistor Q3 is connected to the other end of the heating plate (3).

6. The thermal control circuit of the satellite payload integrated management system according to claim 5, characterized in that: A resistor R10 is connected between the pull-up signal and the input end of the fuse F1 . The connection end of the resistor R10 and the pull-up signal is further connected to a resistor R11 , and the other end of the resistor R11 is grounded.

7. The thermal control circuit of the satellite payload integrated management system according to claim 1, characterized in that: A resistor R12 is connected between the pull-down signal and the resistor R1 , and the other end of the resistor R12 is grounded.

8. The thermal control circuit of the satellite payload integrated management system according to claim 1, characterized in that: The source of the NMOS tube Q3 is connected to one end of the thermal control power supply negative voltage.

9. The thermal control circuit of the satellite payload integrated management system according to claim 1, characterized in that: It also includes an FPGA circuit (4) that outputs a thermal control signal to the interface circuit (1).

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