Output stage circuit and driving circuit

Abstract

The utility model discloses an output stage circuit and a drive circuit, the output stage circuit comprises a first output tube, a second output tube, a first transistor and a second transistor, the control end of the first transistor is used for receiving a first drive signal, and the control end of the second output tube is used for receiving a second drive signal. The first end of the first transistor and the second end of the first output tube are connected with a power supply voltage, the second end of the first transistor is connected with the second end of the second transistor, the control end of the second transistor and the control end of the first output tube, and the first end of the first output tube is connected with the second end of the second output tube to generate an output signal; the first end of the second transistor is used for receiving output signals, and the first end of the second output tube is connected with ground voltage. According to the output stage circuit and the driving circuit, the first end of the second transistor is connected with the output signal, so that the load response speed can be improved, and the output stage circuit and the driving circuit have higher response speed.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuits, and in particular relates to an output stage circuit and a driving circuit. Background Art

[0002] Traditional driver circuits use a combination of a PMOS top transistor and an NMOS bottom transistor as the output stage to source or sink current to the load. However, due to process characteristics, the conduction capability of a PMOS transistor is only half that of an NMOS transistor. To achieve the same driving capability, a PMOS transistor occupies twice the area of ​​an NMOS transistor. Furthermore, the input operational amplifiers of traditional driver circuits often use a PMOS pair input to reduce input noise, and are combined with a folded cascode amplifier circuit to achieve higher DC gain. However, due to the low carrier mobility of PMOS transistors, PMOS differential pair input transistors exhibit lower transconductance. Furthermore, for the same transconductance, PMOS transistors require a much larger width-to-length ratio than NMOS transistors. To achieve a smaller offset voltage, this requires a relatively large layout area, which increases design costs.

[0003] The information disclosed in this background technology section is only intended to increase the understanding of the overall background of the present invention, and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to those skilled in the art. Utility Model Content

[0004] The purpose of the utility model is to provide an output stage circuit and a driving circuit, which can have the capability of pulling up and down currents and have a large driving capability and a small layout area.

[0005] To achieve the above-mentioned objectives, a technical solution provided in a specific embodiment of the present invention is as follows: an output stage circuit, comprising a first output tube, a second output tube, a first transistor, and a second transistor, wherein the control end of the first transistor is used to receive a first drive signal, and the control end of the second output tube is used to receive a second drive signal, the first end of the first transistor and the second end of the first output tube are connected to a power supply voltage, the second end of the first transistor is connected to the second end of the second transistor, the control end of the second transistor, and the control end of the first output tube, the first end of the first output tube is connected to the second end of the second output tube to generate an output signal, the first end of the second transistor is used to receive the output signal, and the first end of the second output tube is connected to a ground voltage.

[0006] In one or more embodiments of the present invention, the output stage circuit also includes a voltage raising unit, which is connected to the second end of the first transistor, the second end of the second transistor, the control end of the second transistor and the control end of the first output tube, and the voltage raising unit is used to raise the control end voltage of the second transistor and the control end voltage of the first output tube.

[0007] In one or more embodiments of the present invention, the voltage raising unit includes a first resistor, the first end of the first resistor is connected to the second end of the first transistor, the control end of the second transistor and the control end of the first output tube, and the second end of the first resistor is connected to the second end of the second transistor.

[0008] In one or more embodiments of the present invention, the output stage circuit further includes a voltage regulating circuit connected to the second drive signal and the control end of the second output tube, and the voltage regulating circuit is used to regulate the second drive signal and transmit it to the control end of the second output tube.

[0009] In one or more embodiments of the present invention, the voltage regulating circuit includes a third transistor and a second resistor, the second end of the third transistor is connected to the power supply voltage, the first end of the third transistor and the first end of the second resistor are connected to the control end of the second output tube, the control end of the third transistor is connected to the drive control module to receive the second drive signal, and the second end of the second resistor is connected to the ground voltage.

[0010] A specific embodiment of the present invention also provides a driving circuit, characterized in that it includes the above-mentioned output stage circuit, input stage circuit and intermediate stage circuit, the input stage circuit is connected to the intermediate stage circuit, the intermediate stage circuit is connected to the output stage circuit, and the input stage circuit is used to generate a first driving signal and a second driving signal on the intermediate stage circuit based on the input signal.

[0011] In one or more embodiments of the present invention, the input stage circuit includes an input pair of transistors, the control ends of the input pair of transistors are respectively used to receive input signals and output signals, or the control ends of the input pair of transistors are respectively used to receive differential input signals.

[0012] In one or more embodiments of the present invention, the input pair transistors are intrinsic transistors.

[0013] In one or more embodiments of the present invention, the intermediate stage circuit includes a connected folded cascode circuit and a linear transconductance ring.

[0014] In one or more embodiments of the present invention, the driving circuit further includes a bias circuit connected to the input stage circuit and the intermediate stage circuit, and the bias circuit is used to provide a bias for the input stage circuit and the intermediate stage circuit.

[0015] Compared to the prior art, the output stage circuit and both output transistors of the driver circuit of the present invention can utilize NMOS transistors, which improves driving capability while reducing footprint and simplifying the circuit structure. By connecting the first terminal of the second transistor to the output signal, load response speed can be improved, resulting in a higher response speed. The input pair uses intrinsic transistors, achieving greater gain and smaller output-input voltage deviation. A linear transconductance loop is provided to reduce static power consumption in the output stage circuit, effectively preventing crosstalk between the first and second output transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 1 is a circuit schematic diagram of a driving circuit in one embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the following will be combined with the drawings of the embodiments of the present invention to clearly and completely describe the technical solutions of the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0019] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0020] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed in a limiting sense.

[0021] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0022] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0023] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element referred to in the singular form may include multiple such elements according to the teachings of this document.

[0024] The specification uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," which can each refer to one or more of the same or different embodiments. In addition, the terms "including," "comprising," "having," etc. used with respect to the embodiments of the present disclosure are synonymous.

[0025] like Figure 1 As shown, the driving circuit in one embodiment of the present invention includes a bias circuit 10 , an input stage circuit 20 , an intermediate stage circuit 30 and an output stage circuit 40 .

[0026] The bias circuit 10 is connected to the input stage circuit 20 and the intermediate stage circuit 30. The bias circuit 10 is used to provide bias for the input stage circuit 20 and the intermediate stage circuit 30. The input stage circuit 20 is connected to the intermediate stage circuit 30, and the intermediate stage circuit 30 is connected to the output stage circuit 40. The input stage circuit 20 is used to generate a first drive signal VA and a second drive signal VB for the intermediate stage circuit 30 based on the input signal VIP.

[0027] like Figure 1As shown, the bias circuit 10 includes a current source IBIAS, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a third resistor R3 and a fourth resistor R4.

[0028] A first terminal of the current source IBIAS is connected to the power supply voltage VCC, and a second terminal of the current source IBIAS is connected to the second terminal of the fourth transistor M4, the control terminal of the fourth transistor M4, the control terminal of the fifth transistor M5, and the control terminal of the sixth transistor M6. The current source IBIAS is used to generate a bias current. A first terminal of the fourth transistor M4, a first terminal of the fifth transistor M5, and a first terminal of the sixth transistor M6 are connected to the ground voltage GND.

[0029] A first end of the seventh transistor M7 is connected to the power supply voltage VCC, a second end of the seventh transistor M7 is connected to the first end of the eighth transistor M8, a control end of the seventh transistor M7 and a second end of the eighth transistor M8 are connected to the first end of the third resistor R3, and a control end of the eighth transistor M8 and a second end of the fifth transistor M5 are connected to the second end of the third resistor R3.

[0030] A first end of the ninth transistor M9 is connected to the power supply voltage VCC, a second end of the ninth transistor M9 is connected to the first end of the tenth transistor M10, a control end of the ninth transistor M9 and a second end of the tenth transistor M10 are connected to the first end of the fourth resistor R4, and a control end of the tenth transistor M10 and a second end of the sixth transistor M6 are connected to the second end of the fourth resistor R4.

[0031] In the bias circuit 10, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 form a current mirror. The mirrored current passes through the seventh transistor M7, the eighth transistor M8, and the third resistor R3, generating a first bias voltage V1 at the control terminal of the seventh transistor M7 and a second bias voltage V2 at the control terminal of the eighth transistor M8. Similarly, a third bias voltage V3 is generated at the control terminal of the ninth transistor M9, and a fourth bias voltage V4 is generated at the control terminal of the eighth transistor M8.

[0032] A set of bias voltages is provided respectively through the seventh transistor M7, the eighth transistor M8, and the fifth transistor M5 branch, as well as the ninth transistor M9, the tenth transistor M10, and the sixth transistor M6 branch, to facilitate debugging of subsequent circuits and parameter differentiation design. In other embodiments, only one seventh transistor M7, an eighth transistor M8, and a fifth transistor M5 branch may be provided, and the first bias voltage V1 replaces the third bias voltage V3, and the second bias voltage V2 replaces the fourth bias voltage V4.

[0033] like Figure 1As shown, the input stage circuit 20 includes an input pair of transistors, namely an eleventh transistor M11 and a twelfth transistor M12, and a thirteenth transistor M13. The input pair of transistors comprises an eleventh transistor M11 and a twelfth transistor M12. The control terminal of the thirteenth transistor M13 is connected to the control terminal of the sixth transistor M6. A first terminal of the thirteenth transistor M13 is connected to the ground voltage GND. A second terminal of the thirteenth transistor M13 is connected to the first terminal of the eleventh transistor M11 and the first terminal of the twelfth transistor M12. The control terminal of the eleventh transistor M11 is configured to receive the output signal VOUT, and the control terminal of the twelfth transistor M12 is configured to receive the input signal VIP. The second terminals of the eleventh transistor M11 and the twelfth transistor M12 are connected to the intermediate stage circuit 30.

[0034] The control terminal of the eleventh transistor M11 forms the inverting input terminal of the amplifier formed by the input stage circuit 20 and the intermediate stage circuit 30, and the control terminal of the twelfth transistor M12 forms the non-inverting input terminal of the amplifier. The thirteenth transistor M13 and the sixth transistor M6 together form a current mirror, which determines the tail current flowing through the eleventh transistor M11 and the twelfth transistor M12.

[0035] In one embodiment, the eleventh transistor M11 and the twelfth transistor M12 are intrinsic transistors, preferably intrinsic NMOS transistors. Because the threshold voltage of intrinsic NMOS transistors is very small, a wider common-mode input range can be achieved. Furthermore, due to their process characteristics, the NMOS input transistor pair has a larger transconductance under the same bias current conditions, which can provide greater gain. This allows the output signal VOUT to more accurately approach the input voltage VIP at the positive input terminal when connected to the reverse input terminal. Furthermore, due to their process characteristics, intrinsic transistors provide better matching, which can reduce the deviation of the output from the input, further improving the accuracy of the output signal VOUT.

[0036] like Figure 1 As shown, the intermediate stage circuit 30 includes a connected folded cascode circuit 31 and a linear transconductance loop 32. The folded cascode circuit 31 includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19.

[0037] A first terminal of the fourteenth transistor M14 and a first terminal of the fifteenth transistor M15 are connected to the power supply voltage VCC. The control terminal of the fourteenth transistor M14 and the control terminal of the fifteenth transistor M15 are connected to the control terminal of the ninth transistor M9. A second terminal of the fourteenth transistor M14 and a first terminal of the sixteenth transistor M16 are connected to the second terminal of the eleventh transistor M11. A second terminal of the fifteenth transistor M15 and a first terminal of the seventeenth transistor M17 are connected to the second terminal of the twelfth transistor M12. The control terminals of the sixteenth transistor M16 and the seventeenth transistor M17 are connected to the control terminal of the tenth transistor M10. A second terminal of the sixteenth transistor M16 is connected to the second terminal of the eighteenth transistor M18, the control terminal of the eighteenth transistor M18, and the control terminal of the nineteenth transistor M19. A second terminal of the seventeenth transistor M17 and a second terminal of the nineteenth transistor M19 are connected to the linear transconductance loop 32. A first terminal of the eighteenth transistor M18 and a first terminal of the nineteenth transistor M19 are connected to the ground voltage GND.

[0038] Under the action of the third bias voltage V3 , the currents on the fourteenth transistor M14 and the fifteenth transistor M15 are determined.

[0039] like Figure 1 As shown, the linear transconductance loop 32 includes a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

[0040] A first end of the twentieth transistor M20 is connected to the power supply voltage VCC, a second end of the twentieth transistor M20 and a control end of the twentieth transistor M20 are connected to a first end of a twenty-first transistor M21, a control end of the twenty-first transistor M21 and a second end of the twenty-first transistor M21 are connected to a second end of a twenty-second transistor M22 to generate a first clamping voltage VL, a first end of the twenty-second transistor M22 is connected to a ground voltage GND, and a control end of the twenty-second transistor M22 is connected to the control end of the thirteenth transistor M13.

[0041] A first end of the twenty-third transistor M23 is connected to the power supply voltage VCC, a control end of the twenty-third transistor M23 is used to receive the first bias voltage V1, a second end of the twenty-third transistor M23 is connected to the first end of the twenty-fourth transistor M24, a control end of the twenty-fourth transistor M24 is used to receive the second bias voltage V2, a second end of the twenty-fourth transistor M24 is connected to the second end of the twenty-fifth transistor M25 and the control end of the twenty-fifth transistor M25 to generate the second clamping voltage VH, a first end of the twenty-fifth transistor M25 is connected to the second end of the twenty-sixth transistor M26 and the control end of the twenty-sixth transistor M26, and a first end of the twenty-sixth transistor M26 is connected to the ground voltage GND.

[0042] The control end of the twenty-seventh transistor M27 is used to receive the second clamping voltage VH, the control end of the twenty-eighth transistor M28 is used to receive the first clamping voltage VL, the second end of the twenty-seventh transistor M27, the first end of the twenty-eighth transistor M28, and the second end of the seventeenth transistor M17 are connected to the output stage circuit 40 to generate the first drive signal VA, and the first end of the twenty-seventh transistor M27, the second end of the twenty-eighth transistor M28, and the second end of the nineteenth transistor M19 are connected to the output stage circuit 40 to generate the second drive signal VB.

[0043] like Figure 1 As shown, the output stage circuit 40 includes a first output tube Q1 , a second output tube Q2 , a first transistor M1 , a second transistor M2 , a voltage boosting unit and a voltage regulating circuit 41 .

[0044] The control terminal of the first transistor M1 is connected to the second terminal of the twenty-seventh transistor M27 and the first terminal of the twenty-eighth transistor M28 to receive the first drive signal VA. The voltage regulating circuit 41 is connected to the first terminal of the twenty-seventh transistor M27 and the second terminal of the twenty-eighth transistor M28 to receive the second drive signal VB. The voltage regulating circuit 41 is connected to the control terminal of the second output transistor Q2. The voltage regulating circuit is configured to regulate the second drive signal VB and transmit it to the control terminal of the second output transistor Q2. The first terminal of the second output transistor Q2 is connected to the ground voltage GND.

[0045] The first end of the first transistor M1 is connected to the power supply voltage VCC, the second end of the first output transistor Q1 is connected to the power supply voltage VIN, and the second end of the first transistor M1, the second end of the second transistor M2, the control end of the second transistor M2, and the control end of the first output transistor Q1 are connected to a voltage raising unit, which is used to raise the voltage at the control end of the second transistor M2 and the control end of the first output transistor Q1. The first end of the first output transistor Q1 is connected to the second end of the second output transistor Q2 to generate an output signal VOUT, and the first end of the second transistor M2 is used to receive the output signal VOUT.

[0046] like Figure 1 As shown, the voltage raising unit includes a first resistor R1, a first end of the first resistor R1 is connected to the second end of the first transistor M1, the control end of the second transistor M2 and the control end of the first output tube Q1, and a second end of the first resistor R1 is connected to the second end of the second transistor M2.

[0047] The voltage regulating circuit 41 includes a third transistor M3 and a second resistor R2. The second end of the third transistor M3 is connected to the power supply voltage VCC. The first end of the third transistor M3 and the first end of the second resistor R2 are connected to the control end of the second output transistor Q2. The control end of the third transistor M3 is connected to the first end of the twenty-seventh transistor M27 and the second end of the twenty-eighth transistor M28 to receive the second drive signal VB. The second end of the second resistor R2 is connected to the ground voltage GND.

[0048] In one embodiment, the first output tube Q1 and the second output tube Q2 are both high-power NMOS tubes. Compared with the traditional circuit that uses a PMOS tube as the upper output tube and an NMOS tube as the lower output tube, they occupy a smaller area while achieving the same driving capability, and are suitable for use scenarios with large driving current requirements.

[0049] By increasing the gate voltage of the second transistor M2 and the gate voltage of the first output transistor Q1 through the first resistor R1, the driving capability of the first output transistor Q1 can be further improved. By connecting the first terminal of the second transistor M2 to the output signal VOUT, the load response speed can be improved. At the same time, the second transistor M2 and the first output transistor Q1 have the same Vgs, and the output of the first output transistor Q1 can be directly adjusted by adjusting the gate voltage of the second transistor M2.

[0050] By providing a voltage regulating circuit, the driving capability of the second driving signal VB is improved to meet the driving requirement of the high-power second output tube Q2.

[0051] In one embodiment, the power supply voltage VCC is a general operating voltage, and the power supply voltage VIN is a driving voltage for driving an external load. In other embodiments, only one power supply voltage of the same magnitude may be used.

[0052] In one embodiment, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the eighteenth transistor M18, the nineteenth transistor M19, the twenty-second transistor M22, the twenty-fifth transistor M25, the twenty-sixth transistor M26, and the twenty-seventh transistor M27 are NMOS transistors, and the first transistor M1, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the twentieth transistor M20, the twenty-first transistor M21, the twenty-third transistor M23, the twenty-fourth transistor M24, and the twenty-eighth transistor M28 are PMOS transistors. In other embodiments, the channel types of the aforementioned transistors may be changed, and other types of devices may be used, and the connection method of the transistors may be adaptively adjusted.

[0053] In this embodiment, the first end of each output tube and transistor refers to the source, the second end refers to the drain, and the control end refers to the gate.

[0054] In actual applications, when the load driven by the output signal VOUT draws current, the output signal VOUT decreases, and the current I2 flowing through the eleventh transistor M11 decreases. Since the current I1 flowing through the fourteenth transistor M14 remains unchanged, the current I3 flowing through the sixteenth transistor M16 and the eighteenth transistor M18 increases. The nineteenth transistor M19 and the eighteenth transistor M18 form a current mirror, and the current flowing through the nineteenth transistor M19 also increases. Similarly, the current flowing through the seventeenth transistor M17 decreases, so both the first drive signal VA and the second drive signal VB decrease. The decrease in the second drive signal VB turns off the third transistor M3, and the second output transistor Q2 is simultaneously pulled down by the second resistor R2 and turned off. The decrease in the first drive signal VA increases the Vsg of the first transistor M1, increasing the current flowing through the first transistor M1, which in turn increases the gate voltage of the second transistor M2. This also increases the gate voltage of the first output transistor Q1, increasing the current flowing through the first output transistor Q1, thereby achieving regulation of the output signal VOUT.

[0055] When current is fed into the load, the output signal VOUT increases, increasing the current I2 flowing through the eleventh transistor M11. Since the current I1 flowing through the fourteenth transistor M14 remains unchanged, the current I3 flowing through the sixteenth and eighteenth transistors M16 and M18 decreases, and the current flowing through the nineteenth transistor M19 also decreases. Similarly, the current flowing through the seventeenth transistor M17 increases. Consequently, both the first drive signal VA and the second drive signal VB increase. The decrease in the first drive signal VA lowers the Vsg of the first transistor M1, reducing the current flowing through the first transistor M1. This, in turn, lowers the gate voltage of the second transistor M2 and the gate voltage of the first output transistor Q1, cutting off the current flowing through the first output transistor Q1. The increase in the second drive signal VB turns on the third transistor M3, and the second output transistor Q2 is pulled up by the third transistor M3, drawing current from the load, thereby regulating the output signal VOUT.

[0056] The linear transconductance loop 32 can control the first drive signal VA and the second drive signal VB, thereby determining the quiescent current of the output stage circuit 40 to meet the design requirements of low quiescent power consumption. At the same time, because the total current flowing through the twenty-seventh transistor M27 and the twenty-eighth transistor M28 remains unchanged, an increase in current in one transistor will cause a decrease in current in the other transistor. This causes the source voltage of the twenty-seventh transistor M27 and the source voltage of the twenty-eighth transistor M28 (i.e., the first drive signal VA and the second drive signal VB) to increase or decrease simultaneously, thereby preventing the first output transistor Q1 and the second output transistor Q2 in the output stage circuit 40 from being connected in series.

[0057] In other embodiments, the control end of the eleventh transistor M11 and the control end of the twelfth transistor M12 may also receive differential input signals respectively, and the driving circuit generates the output signal VOUT based on the differential input signals.

[0058] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed within the present invention. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0059] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. An output stage circuit, characterized in that: The device includes a first output tube, a second output tube, a first transistor, and a second transistor. The control end of the first transistor is used to receive a first drive signal, and the control end of the second output tube is used to receive a second drive signal. The first end of the first transistor and the second end of the first output tube are connected to a power supply voltage. The second end of the first transistor is connected to the second end of the second transistor, the control end of the second transistor, and the control end of the first output tube. The first end of the first output tube is connected to the second end of the second output tube to generate an output signal. The first end of the second transistor is used to receive the output signal, and the first end of the second output tube is connected to a ground voltage.

2. The output stage circuit according to claim 1, characterized in that The output stage circuit also includes a voltage raising unit, which is connected to the second end of the first transistor, the second end of the second transistor, the control end of the second transistor and the control end of the first output tube. The voltage raising unit is used to raise the control end voltage of the second transistor and the control end voltage of the first output tube.

3. The output stage circuit according to claim 2, characterized in that: The voltage raising unit includes a first resistor, a first end of the first resistor is connected to the second end of the first transistor, the control end of the second transistor and the control end of the first output tube, and a second end of the first resistor is connected to the second end of the second transistor.

4. The output stage circuit according to claim 1, wherein: The output stage circuit further includes a voltage regulating circuit connected to the second driving signal and the control end of the second output tube, wherein the voltage regulating circuit is used to regulate the second driving signal and transmit the voltage to the control end of the second output tube.

5. The output stage circuit according to claim 4, characterized in that: The voltage regulating circuit includes a third transistor and a second resistor, the second end of the third transistor is connected to the power supply voltage, the first end of the third transistor and the first end of the second resistor are connected to the control end of the second output tube, the control end of the third transistor is connected to the drive control module to receive the second drive signal, and the second end of the second resistor is connected to the ground voltage.

6. A driving circuit, characterized in that: The device comprises an output stage circuit, an input stage circuit and an intermediate stage circuit according to any one of claims 1 to 5, wherein the input stage circuit is connected to the intermediate stage circuit, the intermediate stage circuit is connected to the output stage circuit, and the input stage circuit is used to generate a first drive signal and a second drive signal on the intermediate stage circuit based on an input signal.

7. The driving circuit according to claim 6, wherein: The input stage circuit includes an input pair of transistors, and the control ends of the input pair of transistors are respectively used to receive input signals and output signals, or the control ends of the input pair of transistors are respectively used to receive differential input signals.

8. The driving circuit according to claim 7, wherein: The input pair transistors are intrinsic transistors.

9. The driving circuit according to claim 6, wherein: The intermediate stage circuit includes a connected folded cascode circuit and a linear transconductance ring.

10. The driving circuit according to claim 6, wherein: The driving circuit further includes a bias circuit connected to the input stage circuit and the intermediate stage circuit, and the bias circuit is used to provide a bias for the input stage circuit and the intermediate stage circuit.

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