BCD device
By integrating superjunction VDMOS units and planar transistor units in BCD devices and connecting them using isolation island structures and back metal layers, the problems of high BCD device packaging cost and low reliability are solved, and higher current capability and reliability are achieved.
Patent Information
- Application Number
- CN202422654234.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-09-19
- Estimated Expiration
- 2034-10-31
AI Technical Summary
Existing BCD device packaging has high cost and low reliability, and the super-junction VDMOS unit has poor compatibility with traditional BCD processes, resulting in increased chip area and reduced reliability.
The superjunction VDMOS unit and the planar transistor unit are integrated on the same substrate. By introducing the first and second doping types of medium-voltage wells in the substrate and epitaxial layer, an isolation island structure is formed to avoid the influence of the high potential of the substrate on the planar transistor unit. The structure is electrically connected to the substrate through the back metal layer as a drain electrode.
The current capability and reliability of BCD devices are improved, the chip area is reduced, the packaging cost is reduced, and the system efficiency is improved.
Smart Images
Figure CN223364474U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a BCD device. Background Art
[0002] BCD (Bipolar-CMOS-DMOS) technology is a monolithic integration process that enables the fabrication of bipolar diodes, CMOS (Complementary Metal Oxide Semiconductor), and DMOS (Double-diffused Metal Oxide Semiconductor) on the same chip, hence the abbreviation BCD technology.
[0003] BCD devices, operating in the 45V to 100V range, are widely used in automotive electronics such as DC-DC power supplies and motor drives. LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) cells are widely used in BCD processes due to their planar structure and excellent compatibility. However, their current capability is limited, limiting their use to low-power scenarios. Compared to LDMOS cells, VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) cells offer higher reliability and lower specific on-resistance due to their internal voltage-resistant junction and vertical on-current path. Superjunction VDMOS cells, based on traditional VDMOS cells, incorporate a superjunction structure. This combines the VDMOS cell's high input impedance, fast switching speed, high operating frequency, voltage control, excellent thermal stability, and simple drive circuitry, while overcoming the VDMOS cell's drawback of a sharp increase in on-resistance with breakdown voltage, thereby improving system efficiency.
[0004] However, super-junction VDMOS cells have poor compatibility with traditional BCD processes. Currently, in BCD devices that use super-junction VDMOS cells, independent super-junction VDMOS cells are usually packaged together with chips made with the BCD process. Sealing the VDMOS cells increases the chip area, increases packaging costs, and also reduces reliability. Utility Model Content
[0005] The purpose of the utility model is to provide a BCD device to solve the problems of high packaging cost and low reliability of existing BCD devices.
[0006] In order to achieve the above object, the utility model provides a BCD device, comprising:
[0007] substrate;
[0008] an epitaxial layer located on the first surface of the substrate, wherein the epitaxial layer has a first region and at least one second region, and the second region has at least one first medium-voltage well;
[0009] a super junction VDMOS unit, wherein a portion of the structure of the super junction VDMOS unit is located in the first region, and the super junction VDMOS unit further includes a back metal layer, the back metal layer is located on the second surface of the substrate and is electrically connected to the substrate;
[0010] a plurality of planar transistor units, wherein partial components of the planar transistor units are respectively located in corresponding first medium voltage wells in the second region; and
[0011] The substrate and the epitaxial layer have a first doping type, and the first medium voltage well has a second doping type.
[0012] Optionally, the super junction VDMOS unit includes:
[0013] at least two second medium-pressure wells, the second medium-pressure wells being laterally spaced apart and arranged within the first region;
[0014] at least two first low-pressure wells, each of the first low-pressure wells being located on and in contact with a corresponding second medium-pressure well;
[0015] A first body contact region and a first source contact region are arranged side by side in each of the first low voltage wells; and
[0016] The first gate structure is located on the epitaxial layer between two adjacent first source contact regions and partially covers the two adjacent first source contact regions.
[0017] Optionally, the super junction VDMOS unit further includes:
[0018] a dielectric layer, located on the epitaxial layer;
[0019] a first interconnect structure, located on the dielectric layer and electrically connected to the first body contact region and the first source contact region in the corresponding first low-voltage well; and
[0020] The second interconnect structure is located on the dielectric layer and is electrically connected to the corresponding first gate structure.
[0021] Optionally, the epitaxial layer has at least a first sub-epitaxial layer and a second sub-epitaxial layer stacked in sequence from bottom to top, the first medium-pressure well and the second medium-pressure well are both located in the first sub-epitaxial layer and part of the second sub-epitaxial layer, and the bottom of the first medium-pressure well and the second medium-pressure well are located in the first sub-epitaxial layer.
[0022] Optionally, the first source contact region has the first doping type, and the second medium voltage well, the first low voltage well and the first body contact region all have the second doping type.
[0023] Optionally, the plurality of planar transistor units include at least one of a MOS unit, a triode unit and a diode unit.
[0024] Optionally, the MOS cell includes at least one of a CMOS cell, an NMOS cell and a PMOS cell.
[0025] Optionally, the transistor unit includes at least one of a longitudinal / transverse NPN transistor unit and a longitudinal / transverse PNP transistor unit.
[0026] Optionally, the diode unit includes at least one of a conventional diode unit and a Zener diode unit.
[0027] Optionally, the CMOS unit includes:
[0028] A second low-pressure well and a third low-pressure well are arranged side by side within the corresponding first medium-pressure well;
[0029] A second source contact region and a first drain contact region are located in the second low-voltage well;
[0030] A third source contact region and a second drain contact region are located in the third low-voltage well; and
[0031] a second gate structure located on the epitaxial layer between the second source contact region and the first drain contact region and covering a portion of the second source contact region and the first drain contact region; and
[0032] A third gate structure is located on the epitaxial layer between the third source contact region and the second drain contact region and covers a portion of the third source contact region and the second drain contact region.
[0033] Optionally, the CMOS unit further includes:
[0034] a dielectric layer, located on the epitaxial layer;
[0035] a third interconnect structure and a fourth interconnect structure, located on the dielectric layer and electrically connected to the second source contact region and the first drain contact region, respectively; and
[0036] a fifth interconnect structure and a sixth interconnect structure, located on the dielectric layer and electrically connected to the third source contact region and the second drain contact region, respectively; and
[0037] The seventh interconnection structure and the eighth interconnection structure are located on the dielectric layer and are electrically connected to the second gate structure and the third gate structure respectively.
[0038] Optionally, the third low-voltage well, the second source contact region and the first drain contact region all have the first doping type, and the second low-voltage well, the third source contact region and the second drain contact region all have the second doping type.
[0039] Optionally, the NMOS unit includes:
[0040] a fourth low-pressure well and a fifth low-pressure well, arranged side by side within the corresponding first medium-pressure well;
[0041] The second body contact region and the fourth source contact region are arranged side by side in the fourth low voltage well;
[0042] a third drain contact region located in the fifth low-voltage well, a portion of the fifth low-voltage well and a portion of the corresponding first medium-voltage well between the fourth source contact region and the third drain contact region being covered by a field oxide layer; and
[0043] A fourth gate structure is located on the epitaxial layer between the fourth source contact region and the third drain contact region and on a portion of the surface of the field oxide layer covering a portion of the fourth source contact region, a portion of the fourth low-voltage well, and the fifth low-voltage well.
[0044] Optionally, the NMOS unit further includes:
[0045] a dielectric layer, located on the epitaxial layer;
[0046] a ninth interconnect structure, located on the dielectric layer and electrically connected to the second body contact region and the fourth source contact region; and
[0047] a tenth interconnect structure, located on the dielectric layer and electrically connected to the third drain contact region; and
[0048] An eleventh interconnection structure is located on the dielectric layer and electrically connected to the fourth gate structure.
[0049] Optionally, the fifth low-voltage well, the fourth source contact region, and the third drain contact region all have the first doping type, and the fourth low-voltage well and the second body contact region all have the second doping type.
[0050] Optionally, the PMOS unit includes:
[0051] A sixth low-pressure well and a seventh low-pressure well are arranged side by side in the corresponding first medium-pressure well, or the sixth low-pressure well is located outside the first medium-pressure well and extends from the surface of the epitaxial layer to the corresponding first medium-pressure well, and the seventh low-pressure well is located in the first medium-pressure well;
[0052] A third body contact region and a fifth source contact region are arranged side by side in each of the sixth low-voltage wells;
[0053] a fourth drain contact region, located in the seventh low-voltage well, the seventh low-voltage well between the fifth source contact region and the fourth drain contact region being covered by a field oxide layer; and
[0054] A fifth gate structure is located on the epitaxial layer between the fifth source contact region and the fourth drain contact region and on a portion of the surface of the field oxide layer covering a portion of the fifth source contact region and the seventh low-voltage well.
[0055] Optionally, the PMOS unit further includes:
[0056] a dielectric layer, located on the epitaxial layer;
[0057] a twelfth interconnect structure, located on the dielectric layer and electrically connected to the third body contact region and the fifth source contact region;
[0058] a thirteenth interconnect structure, located on the dielectric layer and electrically connected to the fourth drain contact region; and
[0059] A fourteenth interconnection structure is located on the dielectric layer and is electrically connected to the fifth gate structure.
[0060] Optionally, the seventh low-voltage well and the third body contact region both have the first doping type, and the sixth low-voltage well, the fifth source contact region and the fourth drain contact region all have the second doping type.
[0061] Optionally, the triode unit includes:
[0062] an eighth low-pressure well, a ninth low-pressure well, and a tenth low-pressure well, arranged side by side within the corresponding first medium-pressure well; and
[0063] The emitter contact region, the base contact region and the collector contact region are respectively located in the eighth low-voltage well, the ninth low-voltage well and the tenth low-voltage well.
[0064] Optionally, the triode unit further includes:
[0065] a dielectric layer, located on the epitaxial layer;
[0066] The fifteenth interconnection structure, the sixteenth interconnection structure, and the seventeenth interconnection structure are all located on the dielectric layer and are electrically connected to the emitter contact region, the base contact region, and the collector contact region, respectively.
[0067] Optionally, the ninth low-voltage well and the base contact region both have the first doping type, and the eighth low-voltage well, the tenth low-voltage well, the emitter contact region and the collector contact region all have the second doping type; or, the ninth low-voltage well and the base contact region both have the second doping type, and the eighth low-voltage well, the tenth low-voltage well, the emitter contact region and the collector contact region all have the first doping type.
[0068] Optionally, the epitaxial layer further includes a third region, and the third region is covered by a field oxide layer. The BCD device further includes a polysilicon diode unit, and the polysilicon diode unit is located on the field oxide layer covering the third region.
[0069] Optionally, the polysilicon diode unit includes:
[0070] a polysilicon layer located on the field oxide layer covering the third region; and
[0071] The anode contact region and the cathode contact region are respectively located at two ends of the polysilicon layer.
[0072] Optionally, the anode contact region has the first doping type, and the cathode contact region has the second doping type.
[0073] Optionally, the polysilicon diode unit further includes:
[0074] a dielectric layer, located on the epitaxial layer;
[0075] an eighteenth interconnect structure, located on the dielectric layer and electrically connected to the anode contact region; and
[0076] A nineteenth interconnect structure is located on the dielectric layer and is electrically connected to the cathode contact region.
[0077] Optionally, the BCD device further includes a passive device, and the passive device is located in the first area and / or the second area.
[0078] The BCD device provided by the present invention includes a substrate, an epitaxial layer, a superjunction VDMOS unit, and several planar transistor units. The epitaxial layer is located on the first surface of the substrate and has a first region and at least one second region within the epitaxial layer. The second region has at least one first medium-voltage well. Part of the superjunction VDMOS unit's structure is located within the first region. The superjunction VDMOS unit also includes a back metal layer located on the second surface of the substrate and electrically connected to the substrate. Part of the structure of the several planar transistor units is located within the first medium-voltage well within the corresponding second region. The present invention integrates the superjunction VDMOS unit into the BCD device. Compared to conventional LDMOS units, the superjunction VDMOS unit has better current capability, less area occupancy, and higher reliability, thereby improving the performance and reliability of the BCD device. Moreover, after the back metal layer and the substrate are electrically connected, they can serve as the drain electrode of the super junction VDMOS unit. In the working state, the drain electrode of the super junction VDMOS unit will be connected to a high potential. Since the substrate and the epitaxial layer have a first doping type and the first medium voltage well has a second doping type, the several planar transistor units are made in the first medium voltage well. The epitaxial layer, the substrate and the first medium voltage well are reverse biased to form an isolation island, so as to avoid adverse effects on the several planar transistor units when the substrate is connected to a high potential. BRIEF DESCRIPTION OF THE DRAWINGS
[0079] Figures 1 to 5 A schematic structural diagram corresponding to the corresponding steps of the method for preparing a BCD device provided in Example 1 of the present utility model;
[0080] Figure 6 A schematic structural diagram of a BCD device provided in Example 1 of the present utility model;
[0081] Figure 7 A schematic structural diagram of a BCD device provided in Example 2 of the present utility model;
[0082] Wherein, the accompanying drawings are marked as follows:
[0083] 100 - substrate; 101 - epitaxial layer; 1011 - first sub-epitaxial layer; 1012 - second sub-epitaxial layer; 101a - first region; 101b, 101c, 101d, 101e - second region; 101f - third region; 11-1 - second medium-pressure well; 11-2, 11-3, 11-4, 11-5 - first medium-pressure well; 120 - first low-pressure well; 121 - second low-pressure well; 122 - third low-pressure well; 123 - fourth low-pressure well; 124 - fifth low-pressure well; 125 - sixth low-pressure well ; 126-seventh low-voltage well; 127-eighth low-voltage well; 128-ninth low-voltage well; 129-tenth low-voltage well; 130-first body contact region; 131-first source contact region; 132-second source contact region; 133-first drain contact region; 134-third source contact region; 135-second drain contact region; 136-second body contact region; 137-fourth source contact region; 138-third drain contact region; 139-third body contact region; 140-fifth source contact region; 141-fourth drain contact region ; 142-emitter contact region; 143-base contact region; 144-collector contact region; 145-anode contact region; 146-cathode contact region; 201-first gate structure; 202-second gate structure; 203-third gate structure; 204-fourth gate structure; 205-fifth gate structure; 206-polysilicon layer; 301-first interconnect structure; 302-second interconnect structure; 303-third interconnect structure; 304-seventh interconnect structure; 305-fourth interconnect structure; 306-fifth interconnect structure structure; 307-eighth interconnect structure; 308-sixth interconnect structure; 309-ninth interconnect structure; 310-eleventh interconnect structure; 311-tenth interconnect structure; 312-twelfth interconnect structure; 313-fourteenth interconnect structure; 314-thirteenth interconnect structure; 315-fifteenth interconnect structure; 316-sixteenth interconnect structure; 317-seventeenth interconnect structure; 318-eighteenth interconnect structure; 319-nineteenth interconnect structure; 400-dielectric layer; 500-back metal layer; 600-field oxide layer. DETAILED DESCRIPTION
[0084] The following is a more detailed description of the specific embodiments of the present invention, with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.
[0085] Figure 6 This is a schematic diagram of the structure of the BCD device provided in this embodiment. Figure 6 As shown, the BCD device includes a substrate 100 , an epitaxial layer 101 , a super junction VDMOS unit, a plurality of planar transistor units and a field oxide layer 600 .
[0086] The substrate 100 has a first surface and a second surface. Figure 6 In the embodiment, the first surface of the substrate 100 is its upper surface, and the second surface of the substrate 100 is its lower surface. In this embodiment, the substrate 100 has a first doping type, and the first doping type is N-type. In some embodiments, the first doping type may also be P-type.
[0087] The epitaxial layer 101 is located on the first surface of the substrate 100. The epitaxial layer 101 includes a first region 101a and at least one second region. The first region 101a and the second region are different regions within the epitaxial layer 101 and are used to form various units. In this embodiment, there are four second regions. For ease of description, the four second regions are referred to as the second region 101b, the second region 101c, the second region 101d, and the second region 101e.
[0088] In this embodiment, the epitaxial layer 101 also has the first doping type. The epitaxial layer 101 is a single-layer structure, and the thickness may be, for example, 4 um to 12 um.
[0089] Furthermore, part of the structure of the superjunction VDMOS cell is located within the first region 101a. Specifically, the superjunction VDMOS cell includes a second medium-voltage well 11-1, a first low-voltage well 120, a first body contact region 130, a first source contact region 131, and a first gate structure 201. There are at least two second medium-voltage wells 11-1, which are laterally spaced apart within the first region 101a. The second medium-voltage wells 11-1 and the epitaxial layer 101 are laterally spaced apart and repeatedly arranged to form a superjunction structure. The top of the second medium-pressure well 11-1 is a certain distance from the surface of the epitaxial layer 101. There are also at least two first low-pressure wells 120, and each first low-pressure well 120 corresponds one-to-one with each second medium-pressure well 11-1. Each first low-pressure well 120 is located above a corresponding second medium-pressure well 11-1. The first low-pressure well 120 extends from the surface of the epitaxial layer 101 into the epitaxial layer 101 and contacts the corresponding second medium-pressure well 11-1. The first source contact region 131 and the first body contact region 130 are arranged side by side within each first low-pressure well 120. The first gate structure 201 is located on the epitaxial layer 101 and covers portions of two adjacent first source contact regions 131, covers portions of the surfaces of two adjacent first low-pressure wells 120, and covers the epitaxial layer 101 between the two adjacent first low-pressure wells 120.
[0090] Optionally, the depth of the second medium-pressure well 11 - 1 may be 2-8 μm.
[0091] In some embodiments, the second medium-pressure well 11 - 1 may also extend from the surface of the epitaxial layer 101 to the inside of the epitaxial layer 101 . In this case, the first low-pressure well 120 is at least partially located in the second medium-pressure well 11 - 1 .
[0092] In this embodiment, the first source contact region 131 has the first doping type, and the second medium voltage well 11-1, the first low voltage well 120 and the first body contact region 130 all have the second doping type, and the second doping type is P type, but should not be limited to this. In some embodiments, the second doping type may also be N type.
[0093] The superjunction VDMOS cell also includes a first interconnect structure 301, a second interconnect structure 302, and a back metal layer 500. The first interconnect structure 301 and the second interconnect structure 302 are located on the dielectric layer 400, and the back metal layer 500 is located on the second surface of the substrate 100. The first interconnect structure 301 corresponds one-to-one with each first low-voltage well 120 and is electrically connected to the first source contact region 131 and the first body contact region 130 in the corresponding first low-voltage well 120. Voltage is applied to the corresponding first low-voltage well 120 and the second medium-voltage well 11-1 through the first source contact region 131 and the first body contact region 130, thereby serving as the source electrode and body electrode of the superjunction VDMOS cell. The second interconnect structure 302 corresponds one-to-one with each first gate structure 201 and is electrically connected to the corresponding first gate structure 201. Voltage is applied to the first gate structure 201, thereby serving as the gate electrode of the superjunction VDMOS cell. The back metal layer 500 is electrically connected to the substrate 100 and is used to apply a voltage to the substrate 100 to serve as a drain electrode of the super junction VDMOS cell.
[0094] In some embodiments, the material of the back metal layer 500 can be Ti / Ni / Ag, etc.
[0095] In this embodiment, the super junction VDMOS unit is a medium voltage unit, and its operating voltage may be 20V to 100V, but it should not be limited thereto. The super junction VDMOS unit may also be a high voltage unit or a low voltage unit.
[0096] Please continue reading Figure 6In this embodiment, each second region has a first medium-voltage well. The first medium-voltage well extends from the surface of the epitaxial layer 101 into the epitaxial layer 101. Each second region is used to form one planar transistor unit. Partial components of the planar transistor unit are located in the corresponding first medium-voltage well within the second region. In this embodiment, the first medium-voltage well has the second doping type.
[0097] It can be understood that after the back metal layer 500 and the substrate 100 are electrically connected, they serve as the drain electrode of the super junction VDMOS unit. In the working state, the drain electrode of the super junction VDMOS unit will be connected to a high potential. Therefore, the planar transistor unit is made in the first medium voltage well, and the substrate 100, the epitaxial layer 101 and the first medium voltage well are reverse biased to form an isolation island to avoid adverse effects on the planar transistor unit when the substrate 100 is connected to a high potential.
[0098] Optionally, the planar transistor structure can be at least one of a MOS unit, a transistor unit and a diode unit, wherein the MOS unit can include at least one of a CMOS unit, an NMOS unit and a PMOS unit, the transistor unit can include at least one of a vertical / lateral NPN transistor unit and a vertical / lateral PNP transistor unit, and the diode unit includes at least one of a conventional diode unit and a Zener diode unit.
[0099] For ease of description, the first medium-voltage wells in the second region 101b, the second region 101c, the second region 101d, and the second region 101e are referred to as the first medium-voltage well 11-2, the first medium-voltage well 11-3, the first medium-voltage well 11-4, and the first medium-voltage well 11-5, respectively. In this embodiment, the second region 11-2 is used to fabricate a CMOS cell, at least part of which is located within the first medium-voltage well 11-2; the second region 101c is used to fabricate an NMOS cell, at least part of which is located within the first medium-voltage well 11-3; the second region 101d is used to fabricate a PMOS cell, at least part of which is located within the first medium-voltage well 11-4; and the second region 101e is used to fabricate a lateral PNP transistor cell, at least part of which is located within the first medium-voltage well 11-5.
[0100] Optionally, the depth of each of the first medium-pressure wells may be 2-8 um.
[0101] Specifically, the CMOS cell includes a second low-voltage well 121, a third low-voltage well 122, a second source contact region 132, a first drain contact region 133, a third source contact region 134, a second drain contact region 135, a second gate structure 202, and a third gate structure 203. The second low-voltage well 121 and the third low-voltage well 122 are arranged side by side within the first medium-voltage well 11-2, and both extend from the surface of the epitaxial layer 101 into the first medium-voltage well 11-2. The second source contact region 132 and the first drain contact region 133 are located within the second low-voltage well 121 and extend from the surface of the epitaxial layer 101 into the second low-voltage well 121. The third source contact region 134 and the second drain contact region 135 are located within the third low-voltage well 122 and extend from the surface of the epitaxial layer 101 into the third low-voltage well 122. The second gate structure 202 and the third gate structure 203 are both located on the epitaxial layer 101. The second gate structure 202 is located between the second source contact region 132 and the first drain contact region 133, covering a portion of the epitaxial layer 101 between the second source contact region 132 and the first drain contact region 133. The third gate structure 203 is located between the third source contact region 134 and the second drain contact region 135, covering a portion of the epitaxial layer 101 between the third source contact region 134 and the second drain contact region 135. The epitaxial layer 101 between the first drain contact region 133 and the third source contact region 134 is covered by the field oxide layer 600, which can isolate the NMOS transistor and the PMOS transistor in the CMOS cell.
[0102] In this embodiment, the third low voltage well 122 , the second source contact region 132 and the first drain contact region 133 all have the first doping type, and the second low voltage well 121 , the third source contact region 134 and the second drain contact region 135 all have the second doping type.
[0103] The CMOS cell further includes a third interconnect structure 303, a fourth interconnect structure 305, a fifth interconnect structure 306, a sixth interconnect structure 308, a seventh interconnect structure 304, and an eighth interconnect structure 307. The third interconnect structure 303, the fourth interconnect structure 305, the fifth interconnect structure 306, the sixth interconnect structure 308, the seventh interconnect structure 304, and the eighth interconnect structure 307 are all located on the dielectric layer 400. The third interconnect structure 303, the fourth interconnect structure 305, and the seventh interconnect structure 304 are electrically connected to the second source contact region 132, the first drain contact region 133, and the second gate structure 202, respectively, and serve as the source electrode, drain electrode, and gate electrode of a MOS transistor (an NMOS transistor in this embodiment) in the CMOS cell. The fifth interconnect structure 306, the sixth interconnect structure 308 and the eighth interconnect structure 307 are electrically connected to the third source contact region 134, the second drain contact region 135 and the third gate structure 203, respectively, and serve as the source electrode, drain electrode and gate electrode of another MOS transistor (PMOS transistor in this embodiment) in the CMOS unit.
[0104] In this embodiment, the CMOS unit is a low-voltage unit, and its operating voltage may be 3V to 5V, but it should not be limited thereto. The CMOS unit may also be a high-voltage unit or a medium-voltage unit.
[0105] Please continue reading Figure 6The NMOS cell includes a fourth low-voltage well 123, a fifth low-voltage well 124, a second body contact region 136, a fourth source contact region 137, a third drain contact region 138, and a fourth gate structure 204. The fourth low-voltage well 123 and the fifth low-voltage well 124 are arranged side by side within the first medium-voltage well 11-3, and both extend from the surface of the epitaxial layer 101 into the first medium-voltage well 11-3. The second body contact region 136 and the fourth source contact region 137 are arranged side by side within the fourth low-voltage well 123 and extend from the surface of the epitaxial layer 101 into the fourth low-voltage well 123. The third drain contact region 138 is located within the fifth low-voltage well 124 and extends from the surface of the epitaxial layer 101 into the fifth low-voltage well 124. A portion of the fifth low-voltage well 124 and a portion of the corresponding first medium-voltage well 11-3 between the fourth source contact region 137 and the third drain contact region 138 are covered by the field oxide layer 600. The field oxide layer 600 reduces the surface electric field of the fifth low-voltage well 124, thereby increasing the withstand voltage of the NMOS cell. The fourth gate structure 204 is located on a portion of the epitaxial layer 101 between the fourth source contact region 137 and the third drain contact region 138, and on a portion of the surface of the field oxide layer 600 on the fifth low-voltage well 124. It covers portions of the fourth and fifth low-voltage wells 123 and 124, the epitaxial layer 101 between the fourth and fifth low-voltage wells 123 and 124, and the portion of the surface of the field oxide layer 600 covering the fifth low-voltage well 124.
[0106] In this embodiment, the fifth low-voltage well 124 , the fourth source contact region 137 , and the third drain contact region 138 all have the first doping type, and the fourth low-voltage well 123 and the second body contact region 136 all have the second doping type.
[0107] The NMOS cell further includes a ninth interconnect structure 309, a tenth interconnect structure 311, and an eleventh interconnect structure 310, all of which are located on the epitaxial layer 101. The ninth interconnect structure 309 is electrically connected to the second body contact region 136 and the fourth source contact region 137, and serves as the source electrode and body electrode of the NMOS cell. The tenth interconnect structure 311 is electrically connected to the third drain contact region 138, and serves as the drain electrode of the NMOS cell. The eleventh interconnect structure 310 is electrically connected to the fourth gate structure 204, and serves as the gate electrode of the NMOS cell.
[0108] In this embodiment, the NMOS unit is a medium voltage unit, and its operating voltage may be 20V to 100V, but it should not be limited thereto. The NMOS unit may also be a high voltage unit or a low voltage unit.
[0109] Please continue reading Figure 6 The PMOS cell includes a sixth low-voltage well 125, a seventh low-voltage well 126, a third body contact region 139, a fifth source contact region 140, a fourth drain contact region 141, and a fifth gate structure 205. The sixth low-voltage well 125 is located in the epitaxial layer 101 outside the first medium-voltage well 11-4. The seventh low-voltage well 126 is located within the first medium-voltage well 11-4. Both the sixth low-voltage well 125 and the seventh low-voltage well 126 extend from the surface of the epitaxial layer 101 into the first medium-voltage well 11-4. The third body contact region 139 and the fifth source contact region 140 are located within the sixth low-voltage well 125 and extend from the surface of the epitaxial layer 101 into the sixth low-voltage well 125. The fourth drain contact region 141 is located within the seventh low-voltage well 126 and extends from the surface of the epitaxial layer 101 into the seventh low-voltage well 126. The seventh low-voltage well 126 between the fifth source contact region 140 and the fourth drain contact region 141 is covered by the field oxide layer 600. The field oxide layer 600 reduces the surface electric field of the seventh low-voltage well 126, thereby increasing the withstand voltage of the PMOS cell. The fifth gate structure 205 is located on the epitaxial layer 101 between the fifth source contact region 140 and the fourth drain contact region 141, and on the portion of the field oxide layer 600 covering the seventh low-voltage well 126. It also covers portions of the sixth and seventh low-voltage wells 125 and 126, the epitaxial layer 101 between the sixth and seventh low-voltage wells 125 and 126, and a portion of the field oxide layer 600 on the seventh low-voltage well 126.
[0110] It should be noted that Figure 6 In the embodiment, the sidewalls of the sixth low-pressure well 125 and the seventh low-pressure well 126 are in direct contact, so the fifth gate structure 205 only covers part of the surface of the sixth low-pressure well 125 and the seventh low-pressure well 126 and part of the surface of the field oxide layer 600 on the seventh low-pressure well 126.
[0111] In some embodiments, the sixth low-pressure well 125 and the seventh low-pressure well 126 may also be arranged side by side in the first medium-pressure well 11 - 4 .
[0112] In this embodiment, the seventh low-voltage well 126 and the third body contact region 139 both have the first doping type, and the sixth low-voltage well 125 , the fifth source contact region 140 , and the fourth drain contact region 141 all have the second doping type.
[0113] The PMOS cell further includes a twelfth interconnect structure 312, a thirteenth interconnect structure 314, and a fourteenth interconnect structure 313, all of which are located on the epitaxial layer 101. The twelfth interconnect structure 312 is electrically connected to the third body contact region 139 and the fifth source contact region 140, and serves as the source electrode and body electrode of the PMOS cell. The thirteenth interconnect structure 314 is electrically connected to the fourth drain contact region 141, and serves as the drain electrode of the PMOS cell. The fourteenth interconnect structure 313 is electrically connected to the fifth gate structure 205, and serves as the gate electrode of the PMOS cell.
[0114] In this embodiment, the PMOS unit is a medium voltage unit, and its operating voltage may be 20V to 100V, but it should not be limited thereto. The PMOS unit may also be a high voltage unit or a low voltage unit.
[0115] Please continue reading Figure 6 The lateral PNP transistor unit includes an eighth low-voltage well 127, a ninth low-voltage well 128, a tenth low-voltage well 129, an emitter contact region 142, a base contact region 143, and a collector contact region 144. The eighth low-voltage well 127, the ninth low-voltage well 128, and the tenth low-voltage well 129 are arranged side by side within the first medium-voltage well 11-5, and the eighth low-voltage well 127, the ninth low-voltage well 128, and the tenth low-voltage well 129 all extend from the surface of the epitaxial layer 101 into the first medium-voltage well 11-5. The emitter contact region 142 is located in the eighth low-pressure well 127 and extends from the surface of the epitaxial layer 101 to the eighth low-pressure well 127; the base contact region 143 is located in the ninth low-pressure well 128 and extends from the surface of the epitaxial layer 101 to the ninth low-pressure well 128; the collector contact region 144 is located in the tenth low-pressure well 129 and extends from the surface of the epitaxial layer 101 to the tenth low-pressure well 129.
[0116] In this embodiment, the ninth low-voltage well 128 and the base contact region 143 have the first doping type, and the eighth low-voltage well 127, the tenth low-voltage well 129, the emitter contact region 142, and the collector contact region 144 all have the second doping type. In some embodiments, the ninth low-voltage well 128 and the base contact region 143 have the second doping type, and the eighth low-voltage well 127, the tenth low-voltage well 129, the emitter contact region 142, and the collector contact region 144 all have the first doping type, thereby forming a lateral NPN transistor cell.
[0117] The lateral PNP transistor unit further includes a fifteenth interconnect structure 315, a sixteenth interconnect structure 316, and a seventeenth interconnect structure 317, all of which are located on the epitaxial layer 101. The fifteenth interconnect structure 315 is electrically connected to the emitter contact region 142 and serves as the emitter electrode of the lateral PNP transistor unit. The sixteenth interconnect structure 316 is electrically connected to the base contact region 143 and serves as the base electrode of the lateral PNP transistor unit. The seventeenth interconnect structure 317 is electrically connected to the collector contact region 144 and serves as the collector electrode of the lateral PNP transistor unit.
[0118] As an optional embodiment, a diode unit may be further provided in the second region. The diode unit may be formed, for example, by utilizing two well regions with different doping types in the second region, which will not be elaborated herein.
[0119] Please continue reading Figure 6 The epitaxial layer 101 further includes a third region 101f, which is covered by the field oxide layer 600. The BCD device further includes a polysilicon diode unit. The polysilicon diode unit in the third region 101f is located on the field oxide layer 600 covering the third region 101f. In this embodiment, the polysilicon diode unit is used to collect temperature.
[0120] Specifically, the polysilicon diode unit includes an anode contact area 145, a polysilicon layer 206 and a cathode contact area 146. The polysilicon layer 206 is located on the field oxide layer 600 covering the third region 101f. The anode contact area 145 and the cathode contact area 146 are respectively located at both ends of the polysilicon layer 206.
[0121] In this embodiment, the anode contact region 145 has the first doping type, and the cathode contact region 146 has the second doping type.
[0122] The polysilicon diode unit further includes an eighteenth interconnect structure 318 and a nineteenth interconnect structure 319. The eighteenth interconnect structure 318 is electrically connected to the anode contact region 145 and serves as the anode of the polysilicon diode unit. The nineteenth interconnect structure 319 is electrically connected to the cathode contact region 146 and serves as the cathode of the polysilicon diode unit.
[0123] Furthermore, the field oxide layer 600 is also located on the epitaxial layer 101 between two adjacent devices to isolate the two adjacent devices. For example, in this embodiment, the field oxide layer 600 is also located on the epitaxial layer 101 between the super-junction VDMOS unit and the CMOS unit, on the epitaxial layer 101 between the CMOS unit and the NMOS unit, on the epitaxial layer 101 between the NMOS unit and the PMOS unit, on the epitaxial layer 101 between the PMOS unit and the lateral PNP transistor unit, and on the epitaxial layer 101 between the lateral PNP transistor unit and the polysilicon diode unit. The field oxide layer 600 can extend from the surface of the epitaxial layer 101 into the epitaxial layer 101, and the top of the field oxide layer 600 can also be higher than the surface of the epitaxial layer 101.
[0124] In this embodiment, the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204, and the fifth gate structure 205 have similar structures and can include a gate oxide layer, a gate electrode layer, and a gate dielectric layer 400. The gate oxide layer and the gate electrode layer are stacked sequentially from bottom to top to form a stacked structure, and the gate dielectric layer 400 covers the sidewalls and top of the stacked structure. The portion of the gate electrode layer covering the epitaxial layer 101 is used to form a device channel, and the portion of the gate electrode layer covering the field oxide layer 600 forms a field plate, which helps optimize the surface electric field and improve the device's withstand voltage.
[0125] Optionally, the thickness of the field oxide layer 600 may be
[0126] Please continue reading Figure 6The BCD device further includes a dielectric layer 400 that completely covers the epitaxial layer 101. The first interconnect structure 301, the second interconnect structure 302, the third interconnect structure 303, the fourth interconnect structure 305, the fifth interconnect structure 306, the sixth interconnect structure 308, the seventh interconnect structure 304, the eighth interconnect structure 307, the ninth interconnect structure 309, the tenth interconnect structure 311, the eleventh interconnect structure 310, the twelfth interconnect structure 312, the thirteenth interconnect structure 314, the fourteenth interconnect structure 313, the fifteenth interconnect structure 315, the sixteenth interconnect structure 316, the seventeenth interconnect structure 317, the eighteenth interconnect structure 318, and the nineteenth interconnect structure 319 are all located on the dielectric layer 400, and each has at least a portion of its top surface exposed above the dielectric layer 400. The first interconnect structure 301, the second interconnect structure 302, the third interconnect structure 303, the fourth interconnect structure 305, the fifth interconnect structure 306, the sixth interconnect structure 308, the seventh interconnect structure 304, the eighth interconnect structure 307, the ninth interconnect structure 309, the tenth interconnect structure 311, the eleventh interconnect structure 310, the twelfth interconnect structure 312, the thirteenth interconnect structure 314, the fourteenth interconnect structure 313, the fifteenth interconnect structure 315, the sixteenth interconnect structure 316, the seventeenth interconnect structure 317, the eighteenth interconnect structure 318, and the nineteenth interconnect structure 319 may each include electrically connected plugs and interconnect metal layers, wherein the plugs are located in the dielectric layer 400, and at least a portion of the top surface of the interconnect metal layer is exposed above the dielectric layer 400.
[0127] Furthermore, the dielectric layer 400 may be a single-layer structure or a multi-layer structure. For example, the material of the dielectric layer 400 may be at least one of silicon oxide and silicon nitride.
[0128] Optionally, the BCD device can be applied to the fields of new energy vehicles and photovoltaics, used in power supplies and motor drive products, and its operating voltage can be 45V to 120V.
[0129] In some embodiments, the BCD device may further include a passive device, which may be located on at least one of the first region 101a, the second region and the third region 101f, thereby forming an ESD structure with the super junction VDMOS unit or the planar transistor unit.
[0130] Based on this, this embodiment provides a method for preparing the BCD device. Figures 1 to 5 The structural diagram corresponding to the corresponding steps of the preparation method of the BCD device provided in this embodiment is shown below. Figures 1 to 5 The preparation method of the BCD device provided in this embodiment is described in detail.
[0131] like Figure 1 As shown, the substrate 100 is provided, and the epitaxial layer 101 of the same doping type is epitaxially grown on the substrate 100 . The epitaxial layer 101 includes the first region 101 a , at least one second region, and the third region 101 f .
[0132] like Figure 2 As shown, the field oxide layer 600 is formed on the epitaxial layer 101. For example, the field oxide layer 600 can be formed by thermal oxidation.
[0133] like Figure 3 As shown, all the first medium-voltage wells (including the first medium-voltage wells 11-2, 11-3, 11-4, and 11-5) and the second medium-voltage well 11-1 are formed in the epitaxial layer 101 through an ion implantation process and a high-temperature push-up process. All the first medium-voltage wells are located in the second region, and the second medium-voltage well 11-1 is located in the first region 101a. The specific process for forming the first medium-voltage well and the second medium-voltage well 11-1 can be: using a photolithography process to locate the regions of the first medium-voltage well and the second medium-voltage well 11-1, then performing high-energy ion implantation in the located regions, and then performing a high-temperature push-up process to form the first medium-voltage well and the second medium-voltage well 11-1.
[0134] Optionally, when high-energy ion implantation is performed on the positioning area, ion implantation can be performed multiple times at different depths of the positioning area, thereby improving the uniformity of doped ions in the first medium-pressure well and the second medium-pressure well 11-1. For example: ion implantation can be performed six times at different depths of the positioning area, and the positioning area is divided into the first sub-region, the second sub-region, the third sub-region, the fourth sub-region, the fifth sub-region and the sixth sub-region along the depth direction. The first sub-region, the second sub-region, the third sub-region, the fourth sub-region, the fifth sub-region and the sixth sub-region are arranged in sequence from bottom to top, and there is a boundary between two adjacent sub-regions; the first ion implantation process implants ions into the first sub-region, and the implantation energy range is preferably 100keV to 600keV; the second ion implantation process implants ions into the second sub-region, and the implantation energy range is preferably 100keV to 600keV. It is preferably 300keV~900keV. The third ion implantation process performs ion implantation on the third sub-region, and the implantation energy range is preferably 600keV~1200keV. The fourth ion implantation process performs ion implantation on the fourth sub-region, and the implantation energy range is preferably 1100keV~1700keV. The fifth ion implantation process performs ion implantation on the fifth sub-region, and the implantation energy range is preferably 1500keV~2100keV. The sixth ion implantation process performs ion implantation on the sixth sub-region, and the implantation energy range is preferably 1900keV~2500keV.
[0135] Please continue reading Figure 3 The first low-pressure well 120 is formed on each of the second medium-pressure wells 11-1 through ion implantation and high-temperature push-in junction processes, and the second low-pressure well 121 and the third low-pressure well 122 are formed in the first medium-pressure well 11-2, the fourth low-pressure well 123 and the fifth low-pressure well 124 are formed in the first medium-pressure well 11-3, the sixth low-pressure well 125 is formed in the epitaxial layer 101, the seventh low-pressure well 126 is formed in the first medium-pressure well 11-4, and the eighth low-pressure well 127, the ninth low-pressure well 128 and the tenth low-pressure well 129 are formed in the first medium-pressure well 11-5.
[0136] like Figure 4 As shown, the first gate structure 201 , the second gate structure 202 , the third gate structure 203 , the fourth gate structure 204 and the fifth gate structure 205 are formed on the epitaxial layer 101 , and the polysilicon layer 206 is also formed at the same time. The method for forming the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204, the fifth gate structure 205 and the polysilicon layer 206 may include: forming gate oxide layers of the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204 and the fifth gate structure 205 on the epitaxial layer 101 using a thermal oxidation method; depositing polysilicon on the epitaxial layer 101, the gate oxide layer and the field oxide layer 600, then removing part of the polysilicon and retaining the polysilicon on each gate oxide layer to form gate electrodes of the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204 and the fifth gate structure 205, retaining the polysilicon on the field oxide layer 600 on the surface of the third region 101f to form the polysilicon layer 206; and forming a gate dielectric layer 400 on the top and sidewalls of each gate electrode.
[0137] like Figure 5As shown, the first body contact region 130 and the first source contact region 131 are formed in the first low-pressure well 120 through ion implantation and activation processes, the second source contact region 132 and the first drain contact region 133 are formed in the second low-pressure well 121, the third source contact region 134 and the second drain contact region 135 are formed in the third low-pressure well 122, the second body contact region 136 and the fourth source contact region 137 are formed in the fourth low-pressure well 123, the third drain contact region 138 is formed in the fifth low-pressure well 124, the third body contact region 139 and the fifth source contact region 140 are formed in the sixth low-pressure well 125, the fourth drain contact region 141 is formed in the seventh low-pressure well 126, and the emitter contact region 142, the base contact region 143 and the collector contact region 144 are formed in the eighth low-pressure well 127, the ninth low-pressure well 128 and the tenth low-pressure well 129, respectively. All contact areas can be formed simultaneously.
[0138] like Figure 6 As shown, a dielectric layer 400 is formed on the epitaxial layer 101. The dielectric layer 400 entirely covers the epitaxial layer 101, the field oxide layer 600, the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204, the fifth gate structure 205, and the polysilicon layer 206.
[0139] The dielectric layer 400 is etched to form a plurality of contact holes, which are then filled with conductive material to form the first interconnect structure 301, the second interconnect structure 302, the third interconnect structure 303, the fourth interconnect structure 305, the fifth interconnect structure 306, the sixth interconnect structure 308, the seventh interconnect structure 304, the eighth interconnect structure 307, the ninth interconnect structure 309, the tenth interconnect structure 311, the eleventh interconnect structure 310, the twelfth interconnect structure 312, the thirteenth interconnect structure 314, the fourteenth interconnect structure 313, the fifteenth interconnect structure 315, the sixteenth interconnect structure 316, the seventeenth interconnect structure 317, the eighteenth interconnect structure 318, and the nineteenth interconnect structure 319.
[0140] Next, the second surface of the substrate 100 is ground to thin the substrate 100 , and the back metal layer 500 is evaporated on the second surface of the substrate 100 .
[0141] It should be noted that the above-mentioned method for preparing the BCD device integrates the super junction VDMOS unit, CMOS unit, NMOS unit, PMOS unit, lateral PNP transistor unit and polysilicon diode unit in the BCD device. However, those skilled in the art will understand that, depending on the type of device, the above-mentioned method can be slightly modified to integrate other different types of devices in the BCD device.
[0142] The preparation method of the BCD device provided in this embodiment is simple and controllable, has a simple process, low cost, and high reliability, and improves the compatibility of the traditional BCD process with the super-junction VDMOS unit. Conventional transistor units such as NMOS units, PMOS units, CMOS units, triode units, and diode units can be integrated into the BCD device, and the super-junction VDMOS unit can also be integrated into the BCD device at a relatively low cost.
[0143] Example 2
[0144] Figure 2 This is a schematic diagram of the structure of the BCD device provided in this embodiment. Figure 2 As shown, the difference from the first embodiment is that in this embodiment, the epitaxial layer 101 has at least two sub-epitaxial layers, and each of the sub-epitaxial layers has a portion of the first medium-pressure well and the second medium-pressure well 11 - 1 .
[0145] Specifically, the epitaxial layer 101 includes a first sub-epitaxial layer 1011 and a second sub-epitaxial layer 1012. The first sub-epitaxial layer 1011 and the second sub-epitaxial layer 1012 are formed by two epitaxy processes. The first sub-epitaxial layer 1011 and the second sub-epitaxial layer 1012 are arranged sequentially from bottom to top. A portion of the first medium-pressure well 11-1 and the second medium-pressure well 11-1 are located in the first sub-epitaxial layer 1011, and the other portion is located in the second sub-epitaxial layer 1012. That is, the first medium-pressure well 11-1 and the second medium-pressure well 11-1 are both located in the first sub-epitaxial layer 1011 and a portion of the second sub-epitaxial layer 1012, with the bottoms of the first medium-pressure well and the second medium-pressure well 11-1 located in the first sub-epitaxial layer 1012.
[0146] Compared with the single-layer epitaxial layer 101, the multi-layer epitaxial layer 101 formed by multiple epitaxy can improve the breakdown voltage of the super junction VDMOS unit and improve the isolation voltage between the substrate 100 and the first medium voltage well and the second medium voltage well 11-1.
[0147] During the fabrication of the BCD device, the epitaxial layer 101 is formed by at least two epitaxial processes, each forming a sub-epitaxial layer. After each sub-epitaxial layer is formed, an ion implantation process is performed to form a portion of the first medium-voltage well and the second medium-voltage well 11-1. The thickness of each sub-epitaxial layer can be 3um to 6um, and the total thickness of the epitaxial layer 101 formed can be 6um to 12um. The depth of the portions of the first medium-voltage well and the second medium-voltage well 11-1 located in the first sub-epitaxial layer 1011 or the second sub-epitaxial layer 1012 can be 1um to 4um. The two portions of the first medium-voltage well or the second medium-voltage well 11-1 are connected vertically, forming a first medium-voltage well or the second medium-voltage well 11-1 with a total depth of 2um to 4um.
[0148] In the example of the present invention, a two-epitaxy method is used to form the epitaxial layer 101, and ion implantation is performed after each epitaxy to form the first medium-voltage well or the second medium-voltage well 11-1, thereby reducing the difficulty of preparing the first medium-voltage well or the second medium-voltage well 11-1 and forming the first medium-voltage well or the second medium-voltage well 11-1 with a deeper junction depth, thereby improving the isolation voltage between the first medium-voltage well or the second medium-voltage well 11-1 and the substrate 100.
[0149] In summary, the BCD device provided in the embodiment of the present invention includes a substrate, an epitaxial layer, a superjunction VDMOS unit, and several planar transistor units. The epitaxial layer is located on the first surface of the substrate, and the epitaxial layer has a first region and at least one second region, and the second region has at least one first medium-voltage well. Part of the component structure of the superjunction VDMOS unit is located in the first region. The superjunction VDMOS unit also includes a back metal layer, which is located on the second surface of the substrate and electrically connected to the substrate. Part of the component structure of the several planar transistor units is respectively located in the corresponding first medium-voltage wells in the second region. The present invention integrates the superjunction VDMOS unit into the BCD device. Compared with conventional LDMOS units, the superjunction VDMOS unit has better current capability, less area occupancy, and higher reliability, which can improve the performance and reliability of the BCD device. Moreover, after the back metal layer and the substrate are electrically connected, they serve as the drain electrode of the super junction VDMOS unit. In the working state, the drain electrode of the super junction VDMOS unit will be connected to a high potential. Since the substrate and the epitaxial layer have a first doping type and the first medium voltage well has a second doping type, the several planar transistor units are made in the first medium voltage well. The epitaxial layer, the substrate and the first medium voltage well are reverse biased to form an isolation island, so as to avoid adverse effects on the several planar transistor units when the substrate is connected to a high potential.
[0150] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.
[0151] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. Any person skilled in the art can utilize the above-disclosed technical content to make many possible changes and modifications to the present invention without departing from the scope of the present invention, or to modify the present invention into equivalent embodiments with equivalent variations. Therefore, any simple modifications, equivalent variations, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention are still within the scope of protection of the present invention.
[0152] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0153] It should also be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the present invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.
Claims
1. A BCD device, characterized in that: include: substrate; an epitaxial layer located on the first surface of the substrate, wherein the epitaxial layer has a first region and at least one second region, and the second region has at least one first medium-voltage well; a super junction VDMOS unit, wherein a portion of the structure of the super junction VDMOS unit is located in the first region, and the super junction VDMOS unit further includes a back metal layer, the back metal layer is located on the second surface of the substrate and is electrically connected to the substrate; a plurality of planar transistor units, wherein partial components of the planar transistor units are respectively located in corresponding first medium voltage wells in the second region; and The substrate and the epitaxial layer have a first doping type, and the first medium voltage well has a second doping type.
2. The BCD device according to claim 1, wherein: The super junction VDMOS unit comprises: at least two second medium-pressure wells, the second medium-pressure wells being laterally spaced apart and arranged within the first region; at least two first low-pressure wells, each of the first low-pressure wells being located on and in contact with a corresponding second medium-pressure well; A first body contact region and a first source contact region are arranged side by side in each of the first low voltage wells; and The first gate structure is located on the epitaxial layer between two adjacent first source contact regions and partially covers the two adjacent first source contact regions.
3. The BCD device according to claim 2, wherein: The super junction VDMOS unit further includes: a dielectric layer, located on the epitaxial layer; a first interconnect structure, located on the dielectric layer and electrically connected to the first body contact region and the first source contact region in the corresponding first low-voltage well; and The second interconnect structure is located on the dielectric layer and is electrically connected to the corresponding first gate structure.
4. The BCD device according to claim 2, wherein: The epitaxial layer has at least a first sub-epitaxial layer and a second sub-epitaxial layer stacked in sequence from bottom to top, the first medium-pressure well and the second medium-pressure well are both located in the first sub-epitaxial layer and part of the second sub-epitaxial layer, and the bottoms of the first medium-pressure well and the second medium-pressure well are located in the first sub-epitaxial layer.
5. The BCD device according to claim 2, wherein: The first source contact region has the first doping type, and the second medium voltage well, the first low voltage well, and the first body contact region all have the second doping type.
6. The BCD device according to claim 1, wherein: The planar transistor unit includes at least one of a MOS unit, a triode unit and a diode unit.
7. The BCD device according to claim 6, wherein: The MOS cell includes at least one of a CMOS cell, an NMOS cell, and a PMOS cell.
8. The BCD device according to claim 6, wherein: The transistor unit includes at least one of a vertical / horizontal NPN transistor unit and a vertical / horizontal PNP transistor unit.
9. The BCD device according to claim 6, wherein: The diode unit includes a Zener diode unit.
10. The BCD device according to claim 7, wherein: The CMOS unit comprises: A second low-pressure well and a third low-pressure well are arranged side by side within the corresponding first medium-pressure well; A second source contact region and a first drain contact region are located in the second low-voltage well; A third source contact region and a second drain contact region are located in the third low-voltage well; and a second gate structure located on the epitaxial layer between the second source contact region and the first drain contact region and covering a portion of the second source contact region and the first drain contact region; and A third gate structure is located on the epitaxial layer between the third source contact region and the second drain contact region and covers a portion of the third source contact region and the second drain contact region.
11. The BCD device according to claim 10, wherein: The CMOS unit further comprises: a dielectric layer, located on the epitaxial layer; a third interconnect structure and a fourth interconnect structure, located on the dielectric layer and electrically connected to the second source contact region and the first drain contact region, respectively; and a fifth interconnect structure and a sixth interconnect structure, located on the dielectric layer and electrically connected to the third source contact region and the second drain contact region, respectively; and The seventh interconnection structure and the eighth interconnection structure are located on the dielectric layer and are electrically connected to the second gate structure and the third gate structure respectively.
12. The BCD device according to claim 10, wherein: The third low voltage well, the second source contact region and the first drain contact region all have the first doping type, and the second low voltage well, the third source contact region and the second drain contact region all have the second doping type.
13. The BCD device according to claim 7, wherein: The NMOS unit includes: a fourth low-pressure well and a fifth low-pressure well, arranged side by side within the corresponding first medium-pressure well; The second body contact region and the fourth source contact region are arranged side by side in the fourth low voltage well; a third drain contact region located in the fifth low-voltage well, a portion of the fifth low-voltage well and a portion of the corresponding first medium-voltage well between the fourth source contact region and the third drain contact region being covered by a field oxide layer; and A fourth gate structure is located on the epitaxial layer between the fourth source contact region and the third drain contact region and on a portion of the surface of the field oxide layer covering a portion of the fourth source contact region, a portion of the fourth low-voltage well, and the fifth low-voltage well.
14. The BCD device according to claim 13, wherein: The NMOS unit further includes: a dielectric layer, located on the epitaxial layer; a ninth interconnect structure, located on the dielectric layer and electrically connected to the second body contact region and the fourth source contact region; and a tenth interconnect structure, located on the dielectric layer and electrically connected to the third drain contact region; and An eleventh interconnection structure is located on the dielectric layer and electrically connected to the fourth gate structure.
15. The BCD device according to claim 13, wherein: The fifth low-voltage well, the fourth source contact region, and the third drain contact region all have the first doping type, and the fourth low-voltage well and the second body contact region all have the second doping type.
16. The BCD device according to claim 7, wherein: The PMOS unit includes: A sixth low-pressure well and a seventh low-pressure well are arranged side by side in the corresponding first medium-pressure well, or the sixth low-pressure well is located outside the first medium-pressure well and extends from the surface of the epitaxial layer to the corresponding first medium-pressure well, and the seventh low-pressure well is located in the first medium-pressure well; A third body contact region and a fifth source contact region are arranged side by side in each of the sixth low-voltage wells; a fourth drain contact region, located in the seventh low-voltage well, the seventh low-voltage well between the fifth source contact region and the fourth drain contact region being covered by a field oxide layer; and A fifth gate structure is located on the epitaxial layer between the fifth source contact region and the fourth drain contact region and on a portion of the surface of the field oxide layer covering a portion of the fifth source contact region and the seventh low-voltage well.
17. The BCD device according to claim 16, wherein: The PMOS unit further includes: a dielectric layer, located on the epitaxial layer; a twelfth interconnect structure, located on the dielectric layer and electrically connected to the third body contact region and the fifth source contact region; a thirteenth interconnect structure, located on the dielectric layer and electrically connected to the fourth drain contact region; and A fourteenth interconnection structure is located on the dielectric layer and is electrically connected to the fifth gate structure.
18. The BCD device according to claim 16, wherein: The seventh low-voltage well and the third body contact region both have the first doping type, and the sixth low-voltage well, the fifth source contact region, and the fourth drain contact region all have the second doping type.
19. The BCD device according to claim 7, wherein: The triode unit comprises: an eighth low-pressure well, a ninth low-pressure well, and a tenth low-pressure well, arranged side by side within the corresponding first medium-pressure well; and The emitter contact region, the base contact region and the collector contact region are respectively located in the eighth low-voltage well, the ninth low-voltage well and the tenth low-voltage well.
20. The BCD device according to claim 19, wherein The triode unit further includes: a dielectric layer, located on the epitaxial layer; The fifteenth interconnection structure, the sixteenth interconnection structure, and the seventeenth interconnection structure are all located on the dielectric layer and are electrically connected to the emitter contact region, the base contact region, and the collector contact region, respectively.
21. The BCD device according to claim 19, wherein: The ninth low-voltage well and the base contact region both have the first doping type, and the eighth low-voltage well, the tenth low-voltage well, the emitter contact region and the collector contact region all have the second doping type; or, the ninth low-voltage well and the base contact region both have the second doping type, and the eighth low-voltage well, the tenth low-voltage well, the emitter contact region and the collector contact region all have the first doping type.
22. The BCD device according to claim 1, wherein: The epitaxial layer further includes a third region, which is covered by a field oxide layer. The BCD device further includes a polysilicon diode unit, which is located on the field oxide layer covering the third region.
23. The BCD device according to claim 22, wherein: The polysilicon diode unit comprises: a polysilicon layer located on the field oxide layer covering the third region; and The anode contact region and the cathode contact region are respectively located at two ends of the polysilicon layer.
24. The BCD device according to claim 23, wherein: The anode contact region has the first doping type, and the cathode contact region has the second doping type.
25. The BCD device according to claim 23, wherein: The polysilicon diode unit further includes: a dielectric layer, located on the epitaxial layer; an eighteenth interconnect structure, located on the dielectric layer and electrically connected to the anode contact region; and A nineteenth interconnect structure is located on the dielectric layer and is electrically connected to the cathode contact region.
26. The BCD device according to claim 1, wherein: The BCD device further includes a passive device, and the passive device is located on the first area and / or the second area.