Integrated device
By introducing a denser insertion layer between the passivation layer and the channel layer, the problems of material mixing and gas diffusion are solved, thereby improving transistor performance and process efficiency.
Patent Information
- Application Number
- CN202422421464.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-20
- Filing Date
- 2024-10-08
- Publication Date
- 2025-11-11
- Estimated Expiration
- 2034-10-08
AI Technical Summary
In existing technologies, the mixing of materials between the passivation layer and the channel layer leads to a decrease in transistor performance, and common materials are difficult to effectively block the diffusion of ambient gases, increasing material costs and processing time.
An insertion layer is introduced between the passivation layer and the channel layer. The material density of the insertion layer is greater than that of the passivation layer, forming a physical isolation that slows down material mixing and blocks gas diffusion.
It effectively reduces the impact of passivation layer material on the channel layer, maintains transistor performance, reduces the impact of material mixing, reduces the diffusion of ambient gas into the channel layer, and improves channel performance.
Smart Images
Figure CN223540867U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to an integrated device. Background Technology
[0002] Most modern electronic devices include multiple transistors. Multiple transistors have multiple source / drain regions, a gate, and channels extending between these source / drain regions. Based on the gate bias, conductive paths are formed between the multiple source / drain regions through these channels. Multiple transistors can be fabricated using either front-end of line (FEOL) or back-end of line (BEOL) processes. Utility Model Content
[0003] This invention provides an integrated device including a substrate; a gate covering the substrate; a channel layer that spaced the gates apart via a dielectric and covering the gates; a plurality of source / drain regions located on the channel layer, the gates extending between the plurality of source / drain regions; an insertion layer conformally to the upper surface of the channel layer and comprising a first material; and a passivation layer conformally to the upper surface of the insertion layer and comprising a second material different from the first material; wherein the passivation layer has a greater density than the insertion layer, such that the passivation layer slows the diffusion of a plurality of ambient materials into the channel layer, and wherein the insertion layer slows the diffusion of the second material from the passivation layer into the channel layer.
[0004] An integrated device according to the present invention includes a gate covering a substrate; a dielectric surrounding an upper surface and a plurality of outer sidewalls of the gate; a channel layer surrounding a plurality of upper surfaces and a plurality of outer sidewalls of the dielectric; an insertion layer surrounding a plurality of upper surfaces and a plurality of outer sidewalls of the channel layer; and a passivation layer surrounding a plurality of upper surfaces and a plurality of outer sidewalls of the insertion layer, wherein the passivation layer and the dielectric extend through a plurality of outermost outer sidewalls of the insertion layer, and wherein the insertion layer spacees the outermost surface of the channel layer from the passivation layer.
[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description
[0006] When with the attached Figure 1 When reading this work, the figures or the present invention can be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.
[0007] Figure 1The diagram shows a cross-sectional view of some transistor embodiments with an insertion layer between the channel and the passivation layer.
[0008] Figure 2 The diagram shows a cross-sectional view of some transistor embodiments with an insertion layer formed by a back-end process between the channel and the passivation layer.
[0009] Figure 3 The diagram shows cross-sectional views of some alternative transistor embodiments with an insertion layer between the channel and the passivation layer.
[0010] Figure 4 The diagram is a cross-sectional view showing a mixture of multiple elements from the channel layer, passivation layer, and surrounding environment.
[0011] Figure 5 The diagram illustrates the spectral intensities corresponding to aluminum and gallium at the surface of the channel layer in some embodiments.
[0012] Figure 6 The diagram illustrates the normalized absolute intensity of the spectra for various elements in the substrate, dielectric, channel layer, insertion layer, and passivation layer in some embodiments.
[0013] Figures 7 to 14 The diagram shows cross-sectional views of some method embodiments of a transistor having an insertion layer formed between a channel and a passivation layer.
[0014] Figures 15-16 The diagram illustrates cross-sectional views of some alternative method embodiments for forming a channel layer and an insertion layer above the gate.
[0015] Figure 17 The diagram illustrates some method embodiments of a transistor having an insertion layer formed between a channel and a passivation layer.
[0016] Explanation of reference numerals in the attached figures
[0017] 100, 200, 300, 400, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600: Sectional View
[0018] 102: Substrate
[0019] 104: Gate
[0020] 106: Dielectric
[0021] 108, 802: Channel layer
[0022] 108s: outermost wall
[0023] 109: Multiple source / drain regions
[0024] 110, 902: Insertion layer
[0025] 111: Active Zone
[0026] 112: Passivation layer
[0027] 114: Source / Drain Contact Window
[0028] 116: Interval
[0029] 118: Transistor
[0030] 202: Interlayer dielectric
[0031] 204: Line Layer
[0032] 206: Perforated layer
[0033] 208: Semiconductor Devices
[0034] 402: Atmospheric gas
[0035] 404, 406: Materials
[0036] 500, 600: Spectral Intensity Chart
[0037] 502, 602: Part 1
[0038] 504, 604: Part Two
[0039] 506, 508, 510, 512, 610, 612, 614, 616, 618, 620: lines
[0040] 606: Part Three
[0041] 608: Part Four
[0042] 702: Bottom Layer
[0043] 1002: Etching process
[0044] 1004: First mask layer
[0045] 1302: Second etching process
[0046] 1304: Second mask layer
[0047] 1306: Opening
[0048] 1502: Third Etching Process
[0049] 1504: Third mask layer
[0050] 1700: Method
[0051] 1702, 1704, 1706, 1708, 1710, 1712, 1714: Actions Detailed Implementation
[0052] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. As illustrated by example, the formation of a first or second feature in the following description may include embodiments in which the first and second features are directly formed in contact, and may also include embodiments in which an additional feature may be formed between the first and second features, such that the first and second features are not directly in contact. Additionally, in various examples, the present invention may use repeated reference numerals and / or letters. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or architectures discussed.
[0053] Furthermore, for ease of description, this document may use spatially relative terms such as “below,” “under,” “down,” “above,” “up,” and similar terms to describe the relationship of one component or feature to another component or feature(s), as shown in the figure. Spatially relative terms are intended to cover different orientations of components in use or operations other than those depicted in the figure. Devices may be oriented in other ways (rotated 90° or otherwise) and the spatially relative descriptors used herein will be interpreted accordingly.
[0054] Random-access-memory (RAM) devices consist of selector transistors and capacitors. Three-dimensional stacked dynamic RAM devices typically arrange multiple selector transistors in layers, with multiple capacitors vertically offset from the layers. Multiple transistors can be formed using either front-end online (FEOL) or back-end online (BEOL) processes. Applying a bias voltage to the multiple transistors causes charge to be transferred to or from the multiple capacitors, creating a device with multiple states that can be read later.
[0055] In some selector transistors, a passivation layer covers the channel layer, protecting it from diffusion of various gases from the surrounding environment (e.g., hydrogen (H2), oxygen (O2), and water vapor (H2O)) into the device. This diffusion can degrade channel performance by increasing channel resistance or unintendedly altering the transistor's threshold voltage. However, some problems arise when common materials such as silicon dioxide and alumina are used for the passivation layer.
[0056] When silicon dioxide is used as a passivation layer, ambient gases can easily permeate through it because the density of silicon dioxide is lower than that of metal oxides. This permeation necessitates a thick passivation layer to substantially slow the diffusion of gas into the channel layer. This increased thickness increases material costs and the time required to form the apparatus.
[0057] When alumina or other metal oxides are used as passivation layers, a thinner layer than silicon dioxide can be used to slow gas diffusion into the channel layer. This is partly because alumina has a higher density than silicon dioxide. However, the direct interface between the alumina passivation layer and the channel layer causes the aluminum in the passivation layer to intermix with various materials in the channel layer, altering several properties of the channel layer and degrading transistor performance. This problem also occurs with other metal oxides that have a direct interface between the metal oxide passivation layer and the channel layer. Transistors that, as in the metal oxide embodiments, restrict the diffusion of surrounding gases while also mitigating material diffusion from the metal oxide to the channel layer are desirable.
[0058] This invention provides a transistor having an insertion layer between a passivation layer and a channel layer. The insertion layer significantly reduces material mixing between the passivation layer and the channel layer, while the passivation layer slows down the diffusion of gases from the surrounding environment into the channel layer. The reduction in impurities from atmospheric gases and the passivation layer in the channel layer results in less change in the properties of the channel layer and improves the performance of the channel.
[0059] Figure 1 A cross-sectional view 100 is shown of some transistor embodiments having an insertion layer between the channel and the passivation layer.
[0060] A gate 104 overlie a substrate 102. A dielectric 106 covers the substrate 104, extending across the upper surface of the substrate 102. A channel layer 108 covers the dielectric 106. The channel layer 108 extends over the gate 104 and has an uppermost surface covering the gate 104. In some embodiments, the channel layer 108 has two additional upper surfaces extending at substantially equal depths below the uppermost surface of the channel layer 108. The channel layer 108 further includes a plurality of source / drain regions 109 on a plurality of opposite sides of the gate 104. A plurality of source / drain contact windows 114 are coupled to the plurality of source / drain regions 109. And an active region 111 of the channel layer 108 extends between the plurality of source / drain regions 109.
[0061] During operation, when the device is in the "ON" state, current flows through the multiple source / drain regions 109 and the active region 111 between the multiple source / drain contact windows; and when the device is in the "OFF" state, current does not flow through the active region 111. The bias voltage of the gate 104 determines the state of the device based on a threshold voltage. In some embodiments, the device is in the "ON" state when the bias voltage is greater than the threshold voltage; and the device is in the "OFF" state when the bias voltage is less than the threshold voltage. The threshold voltage is affected by the composition and properties of the channel layer in the active region 111.
[0062] An insertion layer 110 covers multiple upper surfaces of the channel layer, and is referred to in some cases as a first insulating layer. In some embodiments, the insertion layer 110 is or comprises an insulating material such as silicon dioxide. A passivation layer 112 covers the insertion layer 110 and the transistor 118. In some embodiments, the passivation layer 112 is or comprises a metal oxide such as aluminum oxide, hafnium oxide, or the like. The material of the passivation layer 112 has a higher density than the material of the insertion layer 110; in other words, the insertion layer 110 comprises a first material with a first density and the passivation layer 112 comprises a second material with a second density, wherein the first density is less than the second density, causing the passivation layer 112 to more effectively block atmospheric gases (hydrogen, oxygen, and water vapor) from reaching the channel layer 108 and altering the channel properties. However, the material of the passivation layer 112 may also be mixed with the material of the channel layer 108, wherein the passivation layer 112 contacts the channel layer 108, thereby altering the channel properties. The insert layer 110 is located directly between the channel layer 108 and the multiple upper surfaces of the passivation layer 112, reducing the amount of mixing between the material of the passivation layer 112 and the material of the channel layer 108. Mixing is reduced through the physical separation of the channel layer 108 and the passivation layer 112. In some embodiments, the material properties of the insert layer 110 further reduce mixing.
[0063] In some embodiments, the channel layer 108 is in direct contact with the passivation layer on a plurality of outermost walls 108s, and the plurality of outermost walls 108s of the channel layer 108 are aligned with a plurality of outermost walls of the insert layer 110. While passivation layer 112 material may diffuse from the plurality of outermost walls 108s into the channel layer 108, the plurality of outermost walls 108s are spaced 116 away from the active region 111, thereby reducing the amount of material that may diffuse into the active region 111. The active region 111 is the component most sensitive to changes caused by mixing of the passivation layer material, and it is spaced away from the plurality of outermost walls 108s of the channel layer 108. Therefore, although mixing may occur in the outer regions of the outermost walls 108s, and multiple portions of the channel layer 108 may have higher passivation layer 112 material concentrations, the active region maintains a substantially lower passivation layer 112 material concentration. In other words, the channel layer 108 includes active regions extending between multiple source / drain contact windows, wherein the active regions have a first concentration of material from the passivation layer 112, and the outer regions of the channel layer 108 on multiple outermost walls 108s of the channel layer 108 have a second concentration of material from the passivation layer 112, and the second concentration is greater than the first concentration. The lower concentration further mitigates the potential effects of mixing on the device because the multiple portions of the channel layer with the highest concentration of passivation layer 112 material are spaced apart from the active regions 111.
[0064] Figure 2 The diagram 200 illustrates a cross-sectional view of some transistor embodiments having an insertion layer formed by a back-end process between the channel and the passivation layer.
[0065] In some embodiments, a plurality of interlayer dielectrics 202 space the transistors 118 from the substrate 102. One or more circuit layers 204 and one or more via layers 206 extend through the plurality of interlayer dielectrics 202 and the passivation layer 112. In more embodiments, a plurality of semiconductor devices 208 are located on the substrate 102 and coupled to one or more circuit layers 204. The insertion layer 110 may conform to the plurality of transistors 118 on or above the interlayer dielectrics 202 on the substrate 102.
[0066] Figure 3 Cross-sectional view 300 illustrates some alternative transistor embodiments with an insertion layer between the channel and the passivation layer.
[0067] In some embodiments, the insert layer 110 extends through a plurality of outermost walls 108s of the channel layer 108. The insert layer 110 spaces the plurality of outermost walls 108s of the channel layer 108 from the passivation layer 112 and extends across the upper surface of the dielectric 106. Spacing the channel layer 108 from the passivation layer 112 further reduces the material concentration of the passivation layer 112 in the channel layer 108, further mitigating the effects of mixing by reducing the amount of mixing. Furthermore, the passivation layer 112 is spaced from the dielectric 106 via the insert layer 110.
[0068] Insertion layer 110 has a first thickness on the measurement side between its lower surface and its upper surface directly above the lower surface. In some embodiments, the first thickness is between about 10 angstroms and 200 angstroms, between about 15 angstroms and 250 angstroms, between about 5 angstroms and 120 angstroms, or in another similar range. Passivation layer 112 has a second thickness on the measurement side between its lower surface directly above the uppermost surface of insertion layer 110 and its uppermost surface. In some embodiments, the second thickness is between about 10 angstroms and 1000 angstroms, between about 15 angstroms and 1250 angstroms, between about 5 angstroms and 800 angstroms, or in another similar range.
[0069] Figure 4 A cross-sectional view 400 is shown as a mixture of multiple elements from the channel layer, passivation layer and surrounding environment.
[0070] As shown, atmospheric gas 402 (e.g., hydrogen, oxygen, water vapor, or the like) enters the passivation layer 112 from an exposed surface or subsequently added layer. Because the density of the various materials 404 (e.g., metal oxides) in the passivation layer 112 creates a medium that atmospheric gas does not easily penetrate, the diffusion of atmospheric gas 402 through the passivation layer 112 to the channel layer 108 is significantly reduced compared to a passivation layer of similar thickness, such as silicon dioxide.
[0071] The material 404 of the passivation layer 112 is further mixed with the material 406 of the insertion layer 110. The insertion layer 110, by being spaced apart from the two layers and acting as a transport barrier for the materials 404 and 406, slows down the mixing of the material 404 of the passivation layer 112 with the material 406 of the channel layer 108. Furthermore, when the insertion layer 110 comprises silicon dioxide, it has a stabilizing effect on the materials 404 and 406 (e.g., various metals) mixed within it. This stabilizing effect further slows down the mixing of the material 406 of the channel layer 108 with the material 404 of the passivation layer 112.
[0072] Figure 5 The graph of intensity of the spectra at the surface of the channel layer is shown in some embodiments 500.
[0073] The spectral intensity graph 500 is divided into a first part 502 and a second part 504. The second part 504 corresponds to the channel layer (see...). Figure 1 (108). The first part 502 corresponds to the channel layer (see 108). Figure 1 The layer directly above (108). Line 506 corresponds to the spectral intensity corresponding to aluminum in the embodiment, wherein the passivation layer ( Figure 1 112) and channel layer ( Figure 1 108) is in direct contact. Line 508 corresponds to the spectral intensity corresponding to gallium in the embodiment, wherein the passivation layer ( Figure 1 112) and channel layer ( Figure 1 (108) direct contact. Line 510 corresponds to the spectral intensity corresponding to aluminum in the embodiment, wherein the intercalation layer (see Figure 1 110) is located in the passivation layer ( Figure 1 112) and channel layer ( Figure 1 Between 108). Line 512 corresponds to the spectral intensity corresponding to gallium in the embodiment, wherein the intercalation layer (see 108) Figure 1 110) is located in the passivation layer ( Figure 1 112) and channel layer ( Figure 1 Between 108). When measured by secondary ion mass spectroscopy (SIMS), the relative intensities of lines 506, 508, 510, and 512 are proportional to the spectral intensities of multiple elements at various depths in the device.
[0074] In the passivation layer (see...) Figure 1 (112) and the channel layer (see 112) Figure 1 There is no intercalation layer between 108 (see 108) (see 108) Figure 1 In some embodiments of (110), the first portion 502 corresponds to the passivation layer ( Figure 1 (112). Furthermore, the spectral intensity corresponding to the aluminum extending into the second portion in the embodiment without the insert layer (shown by line 506) is significantly greater than the spectral intensity corresponding to the aluminum extending into the second portion in the embodiment with the insert layer (shown by line 510).
[0075] In the absence of an insert layer ( Figure 1 The embodiment of 110) and in the presence of an insert layer ( Figure 1 The aluminum atom concentration in the 110) example is Figure 5 The multiple depths are proportional to the spectral intensity corresponding to aluminum. That is, in the absence of an insert layer ( Figure 1 In the embodiment of (110), the aluminum atom concentration extending to the second portion 504 is significantly greater than that in the case of the intercalation layer ( Figure 1The aluminum atom concentration in the second part 504 is extended to the embodiment of 110).
[0076] Furthermore, extending from the second portion 504 to the first portion 502, the spectral intensity of gallium in the embodiment without the intercalation layer (shown by line 508) is greater than the spectral intensity of gallium in the embodiment with the intercalation layer (shown by line 512) at a distance from the channel layer ( Figure 1 The greater the distance to the 108) surface, the larger the difference becomes. That is, when the adjacent layer is a passivation layer (e.g., metal oxide) rather than an insertion layer (e.g., silicon dioxide), the difference from the channel layer ( Figure 1 The gallium (108) extends further into the adjacent layer. Therefore, the insertion layer ( Figure 1 The addition of 110 reduces both the mixing of metal from the passivation layer to the channel layer and the mixing of gallium to adjacent layers, resulting in a more pronounced difference between the channel layer and adjacent layers. Greater contrast between multiple layers preserves the channel layer ( Figure 1 The expected channel properties of 108) and resulting in improved device performance.
[0077] In the absence of an insert layer ( Figure 1 The embodiment of 110) and in the presence of an insert layer ( Figure 1 In the embodiment of 110), the gallium atom concentration is at Figure 5 The depths are proportional to the corresponding spectral intensity of gallium. That is, in the absence of an intercalation layer ( Figure 1 In embodiment 110), the gallium atomic concentration extending to the first portion 502 is significantly greater at a greater distance from the second portion 504 than in the portion with the intercalation layer. Figure 1 In the embodiment of 110), the gallium atomic concentration is extended to the first part 502.
[0078] Figure 6 The graph 600 illustrates the normalized absolute intensity of the spectra for various elements in the substrate, dielectric, channel layer, insertion layer, and passivation layer in some embodiments.
[0079] As shown in the figure, the normalized absolute spectral intensity chart 600 is divided into four parts corresponding to different layers of the device. The first part 602 corresponds to the substrate ( Figure 1 Part 102). Part 604 corresponds to the dielectric ( Figure 1 Part 606 corresponds to the channel layer (106). Figure 1 Part 108). The fourth part 608 corresponds to the insertion layer ( Figure 1 110). Line 610 corresponds to transistor ( Figure 1Line 612 corresponds to the spectral intensity of silicon in the multilayer (118). Line 614 corresponds to the spectral intensity of oxygen. Line 616 corresponds to the spectral intensity of gallium. Line 618 corresponds to the spectral intensity of zinc. Line 618 corresponds to the spectral intensity of indium. Line 620 corresponds to the spectral intensity of aluminum. As shown in the figure, in some embodiments, when reading from the third portion 606 to the fourth portion 608, the spectral intensity corresponding to gallium is close to zero. Furthermore, when reading from the end of the fourth portion 608 back to the third portion 606, the spectral intensity corresponding to aluminum is also close to zero.
[0080] When measured using energy-dispersive X-ray spectroscopy, the spectral intensities of the multiple lines 610, 612, 614, 616, 618, and 620 are proportional to the normalized absolute intensity of the emission spectra associated with the multiple elements corresponding to the multiple lines 610, 612, 614, 616, 618, and 620. Furthermore, the atomic concentrations of the multiple elements corresponding to the multiple lines 610, 612, 614, 616, 618, and 620 are also proportional to... Figure 6 The described spectral intensities are proportional. That is, in the first portion 602, the atomic concentration of silicon is greater than the atomic concentration of oxygen. Furthermore, the atomic concentration of oxygen increases in the second portion 604 and is significantly greater than the atomic concentration of silicon in the third portion. Therefore, in some embodiments, when reading from the third portion 606 to the fourth portion 608 (corresponding to...) of the figure... Figure 1 When inserting layer 110, the atomic concentration of gallium is close to zero. Furthermore, when reading from the end of the fourth portion 608 towards the third portion 606, the atomic concentration of aluminum is also close to zero.
[0081] Figures 7 to 14 The diagram shows cross-sectional views of some method embodiments of a transistor having an insertion layer formed between a channel and a passivation layer. Although Figures 7 to 14 This describes the relevant methods, but it should be understood that... Figures 7 to 14 The structures revealed in the paper are not limited to this method, but can exist independently of this method.
[0082] like Figure 7As shown in cross-sectional view 700, a bottom layer 702 is provided. The bottom layer 702 may be a substrate 102 or one of a plurality of interlayer dielectrics 202. A gate 104 is formed on the bottom layer 702. In some embodiments, the gate is or includes a conductive material such as copper, titanium, titanium nitride, doped polysilicon, etc. In some embodiments, the gate 104 is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition process combined with etching, damascene process, or a combination thereof.
[0083] like Figure 8 As shown in cross-sectional view 800, a dielectric 106 and a conformal channel layer 802 are formed above the gate 104. The dielectric 106 is formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other suitable deposition process, or a combination thereof. The conformal channel layer 802 is formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other suitable deposition process, or a combination thereof. In some embodiments, the dielectric 106 is or includes silicon dioxide, a high dielectric, etc. In some embodiments, the channel layer includes indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), gallium oxide (Ga2O3), indium oxide (In2O3), zinc oxide (ZnO), indium gallium oxide (InGaO), gallium zinc oxide (GaZnO), copper oxide (Cu2O), tin dioxide (SnO2), any combination thereof, etc.
[0084] like Figure 9 As shown in cross-sectional view 900, a conformal insertion layer 902 is formed above the conformal channel layer 804. In some embodiments, the conformal insertion layer 902 may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other suitable deposition process, or a combination thereof. In some embodiments, the conformal insertion layer 902 is or includes silicon dioxide, etc.
[0085] like Figure 10 As shown in the cross-sectional view 1000, a conformal insertion layer (see [reference]) is inserted in the region corresponding to the channel layer 108 to be formed subsequently. Figure 9 A first mask layer 1004 is formed above the 902 portion. In some embodiments, the first mask layer 1004 is a photoresist and is patterned using photolithography. After forming the first mask layer 1004, one or more etching processes 1002 are performed to remove the conformal intercalation layer (see [reference]). Figure 9902) and conformal channel layer (see 902) and conformal channel layer (see 902) Figure 9 The 804) consists of multiple parts, which correspond to multiple regions left by the exposure of the first mask layer 1004.
[0086] like Figure 11 As shown in the cross-sectional view 1100, the first mask layer was then removed (see...). Figure 10 (1004). One of the following processes, such as stripping or ashing, can be used to remove the first mask layer (see [reference]). Figure 10 (1004).
[0087] like Figure 12 As shown in cross-sectional view 1200, a passivation layer 112 is formed over the insertion layer 110, the channel layer 108, and the dielectric 106. In some embodiments, the passivation layer 112 is or includes a metal oxide (e.g., aluminum oxide, hafnium oxide), etc. In some embodiments, the passivation layer 112 can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other suitable deposition process, or a combination thereof. In another embodiment, when the passivation layer 112 is formed using a physical vapor deposition process, the ion bombardment from the physical vapor deposition process causes the passivation layer 112 material to diffuse into the insertion layer 110. The thickness of the insertion layer 110 slows down the diffusion of the passivation layer 112 material, resulting in fewer impurities in the channel layer 108 compared to embodiments without the insertion layer 110.
[0088] like Figure 13 As shown in cross-sectional view 1300, a second mask layer 1304 is formed and patterned over a passivation layer 112. In some embodiments, the second mask layer 1304 is or includes photoresist and is patterned using photolithography. After forming the second mask layer 1304, a second etching process 1302 is performed to remove portions of the passivation layer and the insertion layer corresponding to a plurality of openings in the second mask layer 1304. The second etching process 1302 forms a plurality of openings 1306. In some embodiments, the second etching process is an isotropic dry etching process. The second etching process stops at a channel layer 108, which serves as an etching stop layer.
[0089] like Figure 14As shown in cross-sectional view 1400, a plurality of source / drain contact windows 114 are formed in a plurality of openings (shown in dashed lines). In some embodiments, the plurality of source / drain contact windows 114 are or include copper (Cu), titanium (Ti), titanium nitride (TiN), etc. The plurality of source / drain contact windows 114 are formed by depositing a conformal metal layer over a passivation layer 112 and subsequently performing a planarization process (e.g., chemical mechanical planarization, CMP) to remove multiple portions of the conformal metal layer covering the passivation layer 112.
[0090] Figures 15-16 The diagram illustrates cross-sectional views of some alternative method embodiments for forming a channel layer and an insertion layer above the gate. (Compared to...) Figures 9 to 10 The steps described can be made by the following and Figures 15-16 The steps described above are replaced to form with Figure 3 The described embodiments. Although Figures 15-16 The methods described are related, but it should be understood that... Figures 15-16 The multiple structures revealed are not limited to this method, but can exist independently of this method.
[0091] like Figure 15 As shown in the cross-sectional view 1500, a third mask layer 1504 is formed above the conformal channel layer (see...). Figure 8 (802). In some embodiments, the third mask layer 1504 is or includes photoresist and is patterned using photolithography. After the formation of the third mask layer 1504, a third etching process 1502 is performed. The third etching process 1502 results in multiple portions of a conformal channel layer corresponding to multiple openings in the third mask layer 1504 (see 802). Figure 8 The 802 layer was removed. After the third etching process 1502, the channel layer 108 remained below the third mask layer 1504. The third mask layer 1504 was then removed.
[0092] like Figure 16 As shown in the cross-sectional view 1600, an insertion layer 110 is formed above the channel layer 108 and the dielectric 106. The insertion layer is conformal to multiple upper surfaces of the channel layer 108 and the dielectric 106, and covers multiple outermost walls 108s of the channel layer 108.
[0093] Figure 17 Flowchart 1700 illustrates some method embodiments of a transistor having an insertion layer between a channel and a passivation layer.
[0094] Although method 1700 is illustrated below as a series of actions or events, it should be understood that the schematic order of these actions or events should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown are required to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or phases.
[0095] At 1702, a gate is formed above the bottom layer. Figure 7 The diagram is a cross-sectional view 700 corresponding to some embodiments of action 1702.
[0096] At 1704, a dielectric is formed over the multiple sidewalls of the gate and the upper surface and across the bottom layer. Figure 8 The diagram is a cross-sectional view 800 corresponding to some embodiments of action 1704.
[0097] In 1706, a channel layer is formed over a plurality of upper surfaces and a plurality of sidewalls of the dielectric. Figure 8 The diagram is a cross-sectional view 800 corresponding to some embodiments of action 1706.
[0098] At 1708, an insertion layer is formed above multiple upper surfaces and multiple sidewalls of the channel layer. Figures 9 to 10 The figures are illustrated as cross-sectional views 900 to 1000 corresponding to some embodiments of action 1708.
[0099] At 1710, a passivation layer is formed covering the insertion layer, the channel layer, the gate, and the dielectric. Figure 12 The diagram is a cross-sectional view 1200 corresponding to some embodiments of action 1710.
[0100] At 1712, a plurality of contact window openings are etched through the passivation layer and the insertion layer, the plurality of contact window openings extending to the channel layer. Figure 13 The diagram is a cross-sectional view 1300 corresponding to some embodiments of action 1712.
[0101] At 1714, a plurality of source / drain contact windows are formed in the plurality of contact window openings on a plurality of opposite sides of the gate. Figure 14 The diagram is a cross-sectional view 1400 corresponding to some embodiments of action 1714.
[0102] Therefore, this invention relates to a new method for forming an integrated device having an insert layer that separates a plurality of upper surfaces of a channel layer from a passivation layer.
[0103] Accordingly, in some embodiments, the present invention relates to an integrated device including a substrate; a gate covering the substrate; a channel layer spaced apart by a dielectric and covering the gate; a plurality of source / drain regions located on the channel layer, the gate extending between the plurality of source / drain regions; an insertion layer conformally to the upper surface of the channel layer and comprising a first material; and a passivation layer conformally to the upper surface of the insertion layer and comprising a second material different from the first material; wherein the passivation layer has a greater density than the insertion layer, such that the passivation layer slows the diffusion of a plurality of ambient materials into the channel layer, and wherein the insertion layer slows the diffusion of the second material from the passivation layer into the channel layer.
[0104] In other embodiments, the present invention relates to an integrated device including a gate over a substrate; a dielectric surrounding an upper surface and a plurality of outer sidewalls of the gate; a channel layer surrounding a plurality of upper surfaces and a plurality of outer sidewalls of the dielectric; an insertion layer surrounding a plurality of upper surfaces and a plurality of outer sidewalls of the channel layer; and a passivation layer surrounding a plurality of upper surfaces and a plurality of outer sidewalls of the insertion layer, wherein the passivation layer and the dielectric extend through a plurality of outermost outer sidewalls of the insertion layer, and wherein the insertion layer spacees the outermost surface of the channel layer from the passivation layer.
[0105] In other embodiments, the present invention relates to a method of forming an integrated device, comprising forming a gate over a bottom layer; forming a dielectric over a plurality of sidewalls and a top surface of the gate and spanning the bottom layer; forming a channel layer over a plurality of top surfaces and sidewalls of the dielectric; forming an insertion layer over a plurality of top surfaces and sidewalls of the channel layer; forming a passivation layer covering the insertion layer, the channel layer, the gate, and the dielectric; etching a plurality of contact window openings through the passivation layer and the insertion layer, the plurality of contact window openings extending to the channel layer; and forming a plurality of source / drain contact windows in the plurality of contact window openings on a plurality of opposite sides of the gate.
[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.
Claims
1. An integrated device, characterized in that, include: Substrate; The gate is covered on the substrate; A channel layer, which separates the gates via a dielectric and covers the gates; Multiple source / drain regions are located on the channel layer, and the gate extends between the multiple source / drain regions; An insertion layer conformally to the upper surface of the channel layer and comprises a first material; as well as A passivation layer covers the upper surface of the insertion layer and comprises a second material different from the first material; The passivation layer has a higher density than the insertion layer, thus the passivation layer slows the diffusion of multiple environmental materials into the channel layer, and the insertion layer slows the diffusion of the second material from the passivation layer into the channel layer.
2. The integrated device of claim 1, wherein the channel layer conforms to a plurality of outer sidewalls of the gate, and the insertion layer conforms to a plurality of outer sidewalls of the channel layer.
3. The integrated device of claim 1, wherein the plurality of outer sidewalls of the insertion layer are aligned with the plurality of outer sidewalls of the channel layer.
4. The integrated device of claim 1, wherein the insertion layer extends through a plurality of outer sidewalls of the channel layer and spacees the plurality of outer sidewalls of the channel layer from the passivation layer.
5. The integrated device of claim 1, further comprising a plurality of contact windows extending to the plurality of source / drain regions of the channel layer, the plurality of contact windows extending through the insertion layer and the passivation layer to the upper surface of the channel layer.
6. The integrated device of claim 1, wherein the channel layer has a first thickness and the insertion layer has a second thickness greater than the first thickness.
7. An integrated device, comprising: The gate is covered on the substrate; A dielectric material surrounding the upper surface of the gate and multiple outer sidewalls; Channel layer, surrounding multiple upper surfaces and multiple outer walls of the dielectric; An insertion layer surrounds multiple upper surfaces and multiple outer walls of the channel layer; as well as A passivation layer surrounds a plurality of upper surfaces and a plurality of outer sidewalls of the insertion layer, wherein the passivation layer and the dielectric extend through a plurality of outermost sidewalls of the insertion layer, and wherein the insertion layer spacees the outermost surface of the channel layer from the passivation layer.
8. The integrated device of claim 7, wherein the insertion layer comprises a first material having a first density and the passivation layer comprises a second material having a second density, wherein the first density is less than the second density.
9. The integrated device of claim 7, wherein the channel layer includes an active region extending between a plurality of source / drain contact windows, wherein the active region has a first concentration of material from the passivation layer, and wherein the outer regions of the channel layer on a plurality of outermost walls of the channel layer have a second concentration of the material from the passivation layer, wherein the second concentration is greater than the first concentration.