Time delay circuit and rectification circuit and rectification chip thereof
By designing the first and second delay units in the delay circuit and using the same or complementary electrical parameters, the problem of inconsistent turn-on speeds between the power transistor and the rectifier transistor in the rectifier circuit was solved, thus achieving accuracy in dead time control and stability in delay duration.
Patent Information
- Application Number
- CN202422787369.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-05
- Filing Date
- 2024-11-15
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-11-15
AI Technical Summary
In synchronous rectification DC-DC chips, the switching speeds of the power transistor and the rectifier transistor are inconsistent, resulting in inaccurate dead time control of the rectifier circuit, and the delay time of the delay control circuit will change with temperature.
Design a time delay circuit, including a first time delay unit and a second time delay unit. By using a fixed value, the sum of the time it takes for the voltage of the first time delay unit after discharge to reach the first threshold voltage of the first inverting module and the time it takes for the voltage of the second time delay unit after charging to reach the second threshold voltage of the second inverting module is used. By using the same or mutually compensating electrical parameters of the inverting modules, the time delay is ensured to be unaffected by temperature.
This improves the accuracy and controllability of dead time control in the rectifier circuit, ensuring that the total delay of the delay circuit is unaffected by temperature changes.
Smart Images
Figure CN223553308U_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims priority to Chinese Patent Application No. 202410245322.6, filed on March 5, 2024, entitled “A Delay Circuit and Rectifier Circuit and Rectifier Chip Thereof”, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This application relates to the field of circuit design technology, and more specifically, to a time delay circuit, its rectifier circuit, and a rectifier chip. Background Technology
[0004] In synchronous rectification DC-DC chips, the power transistor and the rectifier transistor are turned on or off alternately. There is a problem that the on and off speeds of the two are inconsistent, which can lead to the power transistor and the rectifier transistor being turned on at the same time, resulting in the chip burning out.
[0005] To address these issues, a dead-time control needs to be introduced into the rectifier circuit design to prevent the power transistor and rectifier transistor from turning on simultaneously. Currently, dead-time control typically employs a time-delay control circuit. However, the delay time of currently designed time-delay control circuits varies with temperature, leading to inaccurate dead-time control in the rectifier circuit. Utility Model Content
[0006] The purpose of this application is to provide a delay circuit, its rectifier circuit, and a rectifier chip to solve the problem that the delay time of the current dead-time control circuit changes with temperature, resulting in inaccurate dead-time control of the rectifier circuit.
[0007] In a first aspect, this utility model provides a time delay circuit, comprising: a first time delay unit and a second time delay unit; the first time delay unit includes a first control module, a first charging / discharging module, a first inverting module, and a third inverting module; the second time delay unit includes a second control module, a second charging / discharging module, a second inverting module, and a third inverter; the output terminal of the first control module is electrically connected to the input terminal of the first inverting module and the first charging / discharging module, respectively; the input terminal of the first inverting module is also electrically connected to the first charging / discharging module; the output terminal of the first inverting module is electrically connected to the input terminal of the second control module through the third inverting module; the output terminal of the second control module is electrically connected to the second charging / discharging module and the second inverting module, respectively; and the output terminal of the second inverting module is electrically connected to the third inverter; the first control module is used to control the first charging / discharging module to discharge according to a target control signal; the first inverting module is used to... After the voltage of the first charging / discharging module reaches a first threshold voltage after discharging, it outputs an inverted signal of the target control signal to the third inverting module. The third inverting module outputs a first control signal to the second control module based on the inverted signal of the target control signal. The second control module controls the second charging / discharging module to charge based on the first control signal. After the voltage of the second charging / discharging module reaches a second threshold voltage after charging, the second inverting module outputs an inverted signal of the first control signal to the third inverter. The third inverter outputs a second control signal based on the inverted signal of the first control signal. The sum of the first time when the voltage of the first time delay unit reaches the first threshold voltage of the first inverting module after discharging and the second time when the voltage of the second time delay unit reaches the second threshold voltage of the second inverting module after charging is a target fixed value, which is determined based on the device electrical parameters of the first and second time delay units.
[0008] The aforementioned time delay circuit includes a first time delay unit and a second time delay unit. The first time delay unit includes a first inverting module, and the second time delay unit includes a second inverting module. The first time delay unit discharges according to the target control signal, and the second time delay unit charges. The sum of the first time when the voltage of the first time delay unit after discharge reaches the first threshold voltage of the first inverting module and the second time when the voltage of the second time delay unit after charging reaches the second threshold voltage of the second inverting module is a target fixed value (for example, if the first threshold voltage of the first inverting module increases with temperature, causing the first time for discharge to reach the first threshold voltage to shorten, in this case, the second threshold voltage of the second inverting module also increases with temperature, causing the second time for charging to reach the second threshold voltage to lengthen, but the sum of the two remains unchanged and is the target fixed value). By complementing the changes in the first time (discharge) and the second time (charging) due to temperature, the time delay of the time delay circuit is not affected by temperature, thereby improving the accuracy of dead time control.
[0009] In an optional embodiment of the first aspect, the first control module includes a first PMOS transistor and a first NMOS transistor; the first charge / discharge module includes a first constant current power supply and a first capacitor; and the first inverting module includes a second PMOS transistor, a second NMOS transistor, and a first resistor. The gates of the first NMOS transistor and the first PMOS transistor are used to receive a target control signal; the source of the first PMOS transistor is used to receive a power supply voltage; the drain of the first PMOS transistor is electrically connected to the first terminal of the first capacitor and the drain of the first NMOS transistor, respectively; the source of the first NMOS transistor is grounded through the first constant current power supply; and the second terminal of the first capacitor is grounded. The first terminal of the first capacitor is also electrically connected to the gate of the second PMOS transistor and the gate of the second NMOS transistor; the source of the second PMOS transistor is used to receive the power supply voltage; the source of the second NMOS transistor is grounded; the drain of the second PMOS transistor is connected to the first terminal of the first resistor; and the second terminal of the first resistor is electrically connected to the drain of the second NMOS transistor and the third inverting module, respectively.
[0010] In the above implementation method, this solution uses simple field-effect transistors, capacitors and constant current power supplies to design the first time delay unit, thereby saving costs and simplifying the circuit structure.
[0011] In an optional embodiment of the first aspect, the third inverter module includes a first inverter and a second inverter; the input terminals of both the first inverter and the second inverter are electrically connected to the second terminal of the first resistor, and the output terminals of both the first inverter and the second inverter are electrically connected to the second delay unit.
[0012] In an alternative embodiment of the first aspect, the first delay unit further includes a buffer stage; the buffer stage is disposed between the first resistor and the third inverting module.
[0013] In the above implementation, this solution amplifies the first control signal output by the first delay unit by designing an amplifier between the first resistor and the third inverting module, thereby avoiding interference caused by the small signal.
[0014] In an optional embodiment of the first aspect, the second control module includes a third NMOS transistor and a third PMOS transistor; the second charge / discharge module includes a second constant current power supply and a second capacitor; and the second inverting module includes a fourth NMOS transistor, a fourth PMOS transistor, and a second resistor. The gates of the third NMOS transistor and the third PMOS transistor are electrically connected to the third inverting module. The source of the third PMOS transistor is electrically connected to the power supply voltage through the second constant current power supply. The drain of the third PMOS transistor is electrically connected to the drain of the third NMOS transistor and the first terminal of the second capacitor. The second terminal of the second capacitor is grounded, and the source of the third NMOS transistor is grounded. The first terminal of the second capacitor is also electrically connected to the gate of the fourth NMOS transistor and the gate of the fourth PMOS transistor. The source of the fourth PMOS transistor is electrically connected to the power supply voltage and grounded. The drain of the fourth PMOS transistor is electrically connected to the drain of the fourth NMOS transistor and the input terminal of the third inverter through the second resistor.
[0015] In the above implementation method, this solution uses simple field-effect transistors, capacitors, and constant current power supplies to design the second delay unit, thereby saving costs and simplifying the circuit structure.
[0016] In an optional embodiment of the first aspect, the second PMOS transistor and the fourth PMOS transistor have the same electrical parameters, the second NMOS transistor and the fourth NMOS transistor have the same electrical parameters, the first resistor and the second resistor have the same electrical parameters, the first capacitor and the second capacitor have the same electrical parameters, and the first constant current power supply and the second constant current power supply have the same electrical parameters.
[0017] In the above implementation, this solution designs the second PMOS transistor and the fourth PMOS transistor to have the same electrical parameters, the second NMOS transistor and the fourth NMOS transistor to have the same electrical parameters, and the first resistor and the second resistor to have the same electrical parameters. This makes the first inverting module and the second inverting module identical, thereby making the first threshold voltage and the second threshold voltage identical, and the changes in the threshold voltages of the first inverting module and the second inverting module with temperature variations also identical. Simultaneously, the first resistor and the second resistor, the first capacitor and the second capacitor, and the first constant current power supply and the second constant current power supply have the same electrical parameters. This allows the change in the charging time of the second delay unit under temperature influence to complement the change in the discharging time of the first delay unit, thus keeping the total delay of the delay circuit constant, i.e., the total delay threshold voltage of the delay circuit is independent, improving the accuracy and controllability of the dead time.
[0018] Secondly, this utility model provides a rectifier circuit, which includes a power transistor, a rectifier transistor, an inductor, a fourth inverter, a first delay circuit, and a second delay circuit; wherein the first delay circuit and the second delay circuit both include delay circuits of any optional embodiment in the first aspect; the gate of the power transistor is electrically connected to the output terminal of the first delay circuit, and the input terminal of the first delay circuit is used to receive a PWM signal; the gate of the rectifier transistor is electrically connected to the output terminal of the second delay circuit, and the input terminal of the second delay circuit is electrically connected to the output terminal of the fourth inverter, and the input terminal of the fourth inverter is used to receive a PWM signal; the drain of the power transistor is used to receive a target voltage, the source of the power transistor is electrically connected to the drain of the rectifier transistor and the inductor respectively, and the source of the rectifier transistor is grounded.
[0019] The rectifier circuit designed above includes the time delay circuit described above. Therefore, the dead time of the designed rectifier circuit is not affected by temperature, thereby improving the accuracy of dead time control.
[0020] Thirdly, this utility model provides a rectifier chip, which includes a delay circuit of any optional embodiment of the first aspect.
[0021] The rectifier chip designed above contains the delay circuit described above. Therefore, the dead time of the designed rectifier circuit is not affected by temperature, thereby improving the accuracy of dead time control. Attached Figure Description
[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a first structural schematic diagram of the delay circuit provided in an embodiment of this application;
[0024] Figure 2 This is a schematic diagram of the second structure of the delay circuit provided in an embodiment of this application;
[0025] Figure 3 A third structural schematic diagram of the delay circuit provided in an embodiment of this application;
[0026] Figure 4 A fourth structural schematic diagram of the delay circuit provided in an embodiment of this application;
[0027] Figure 5 A fifth structural schematic diagram of the delay circuit provided in an embodiment of this application;
[0028] Figure 6 A sixth structural schematic diagram of the delay circuit provided in an embodiment of this application;
[0029] Figure 7 This is a schematic diagram of the rectifier circuit provided in an embodiment of this application;
[0030] Figure 8 This is a schematic diagram of the structure of the rectifier chip provided in an embodiment of this application.
[0031] Icons: 1-Rectifier chip; 10-First delay unit; 110-First inverter module; 120-First control module; 130-First charge / discharge module; 140-Third inverter module; 1410-First inverter; 1420-Second inverter; 150-Buffer stage; 20-Second delay unit; 210-Second inverter module; 220-Second control module; 230-Second charge / discharge module; 240-Third inverter; M1-First PMOS transistor; M2-First NMOS transistor Transistors; M3 - Second PMOS transistor; M4 - Second NMOS transistor; M5 - Third PMOS transistor; M6 - Third NMOS transistor; M7 - Fourth PMOS transistor; M8 - Fourth NMOS transistor; I1 - First constant current power supply; I2 - Second constant current power supply; R1 - First resistor; R2 - Second resistor; C1 - First capacitor; C2 - Second capacitor; Q1 - Power transistor; Q2 - Rectifier transistor; L1 - Inductor; F1 - Fourth inverter; A1 - First delay circuit; A2 - Second delay circuit. Detailed Implementation
[0032] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.
[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.
[0034] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.
[0035] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0036] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0037] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).
[0038] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.
[0039] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.
[0040] In synchronous rectification DC-DC chips, the power transistor and the rectifier transistor are turned on or off alternately. There is a problem that the on and off speeds of the two are inconsistent, which can lead to the power transistor and the rectifier transistor being turned on at the same time, resulting in the chip burning out.
[0041] To address these issues, a dead-time control needs to be introduced into the rectifier circuit design to prevent the power transistor and rectifier transistor from turning on simultaneously. Currently, dead-time control typically employs a time-delay control circuit. However, the delay time of currently designed time-delay control circuits varies with temperature, leading to inaccurate dead-time control in the rectifier circuit.
[0042] The applicant discovered that current time delay control circuits generally have an inverter structure composed of field-effect transistors. The reverse voltage threshold of the inverter structure composed of field-effect transistors changes with temperature. This causes the time delay of the designed time delay control circuit to change with temperature, resulting in inaccurate dead time control of the rectifier circuit.
[0043] Based on the above findings, this application designs a time delay circuit, which includes a first time delay unit and a second time delay unit. The first time delay unit includes a first inverting module, and the second time delay unit includes a second inverting module. The first time delay unit discharges according to the target control signal, and the second time delay unit charges. The sum of the first time when the voltage of the first time delay unit after discharge reaches the first threshold voltage of the first inverting module and the second time when the voltage of the second time delay unit after charging reaches the second threshold voltage of the second inverting module is a target fixed value (for example, if the first threshold voltage of the first inverting module increases with temperature, the first time for discharge to reach the first threshold voltage becomes shorter. In this case, the second threshold voltage of the second inverting module also increases with temperature, which in turn makes the second time for charging to reach the second threshold voltage longer, but the sum of the two remains unchanged and is the target fixed value). By complementing the changes in the first time (discharge) and the second time (charging) due to temperature, the time delay of the time delay circuit is not affected by temperature, thereby improving the accuracy of dead time control.
[0044] Based on the above ideas, this application first provides a time delay circuit, such as... Figure 1 As shown, the delay circuit includes a first delay unit 10 and a second delay unit 20. The first delay unit 10 includes a first inverting module 110, and the second delay unit 20 includes a second inverting module 210.
[0045] In the time delay circuit designed above, the first time delay unit 10 can receive the target control signal IN transmitted from the outside. The first time delay unit 10 discharges according to the target control signal IN. After the voltage after discharge reaches the first threshold voltage of the first inverting module 110, it outputs the first control signal to the second time delay unit 20.
[0046] The second delay unit 20 charges according to the first control signal, and outputs the second control signal OUT after the voltage after charging reaches the second threshold voltage of the second inverting module 210. In the delay circuit designed in this scheme, the sum of the first time when the voltage after the first delay unit 10 discharges reaches the first threshold voltage of the first inverting module 110 and the second time when the voltage after the second delay unit 20 is charged reaches the second threshold voltage of the second inverting module 210 is a target fixed value.
[0047] The first threshold voltage mentioned above represents the voltage threshold required for the first inverting module 110 to invert the signal, and the second threshold voltage represents the voltage threshold required for the second inverting module 210 to invert the signal.
[0048] The target fixed value means that the sum of the first time and the second time remains constant. For example, if the first threshold voltage of the first inverting module 110 increases with temperature, causing the first time for discharge to reach the first threshold voltage to shorten, the second threshold voltage of the second inverting module 210 also increases with temperature, but the second time for the second delay unit 20 to reach the second threshold voltage through charging becomes correspondingly longer, thus keeping the sum of the two constant at the target fixed value. As another example, if the first threshold voltage of the first inverting module 110 decreases with temperature, causing the first time for discharge to reach the first threshold voltage to lengthen, the second threshold voltage of the second inverting module 210 also decreases with temperature, thus shortening the second time for the second delay unit 20 to reach the second threshold voltage through charging, keeping the sum of the two constant at the target fixed value. This ensures that the delay circuit's duration is not affected by temperature, thereby improving the accuracy of dead-time control.
[0049] As one possible implementation, this solution can design the first inverting module 110, the second inverting module 210, and the charging and discharging related circuits to be circuit structures with identical circuit structures and device electrical parameters. This makes the first threshold voltage equal to the second threshold voltage. Furthermore, since the electrical parameters are the same, the changes in the threshold voltages of the first inverting module 110 and the second inverting module 210 due to temperature are also the same. This makes the changes in the discharge time of the first delay unit 10 and the changes in the charging time of the second delay unit complementary, so that the sum of the two remains unchanged and is always the target fixed value. As another possible implementation, this solution can also design the first inverting module 110 and the second inverting module 210, as well as the charging and discharging related circuits, to have different circuit structures and device electrical parameters. In this way, other means can be used to ensure that the change in the discharge time of the first delay unit 10 is complementary to the change in the charging time of the second delay unit, so that the sum of the two remains unchanged and is in the form of a target fixed value. For example, other forms of circuits can be added to adjust the charging time of the second delay unit, thereby ensuring that the change in the charging time of the second delay unit due to temperature is complementary to the change in the discharge time of the first delay unit 10 due to temperature.
[0050] As one possible implementation, the first delay unit 10 described above can receive a voltage power supply, the initial voltage of which is the power supply voltage, that is, discharge begins from the power supply voltage; the initial voltage of the second delay unit 20 can be 0V, that is, charging begins from 0V.
[0051] The target fixed value of the above design can be determined based on the device electrical parameters of the first delay unit 10 and the second delay unit 20. That is, the user can adjust the target fixed value by selecting the device electrical parameters of the first delay unit 10 and the second delay unit 20.
[0052] The aforementioned time delay circuit includes a first time delay unit and a second time delay unit. The first time delay unit includes a first inverting module, and the second time delay unit includes a second inverting module. The first time delay unit discharges according to the target control signal, and the second time delay unit charges. The sum of the first time when the voltage of the first time delay unit after discharge reaches the first threshold voltage of the first inverting module and the second time when the voltage of the second time delay unit after charging reaches the second threshold voltage of the second inverting module is a target fixed value (for example, if the first threshold voltage of the first inverting module increases with temperature, causing the first time for discharge to reach the first threshold voltage to shorten, in this case, the second threshold voltage of the second inverting module also increases with temperature, causing the second time for charging to reach the second threshold voltage to lengthen, but the sum of the two remains unchanged and is the target fixed value). By complementing the changes in the first time (discharge) and the second time (charging) due to temperature, the time delay of the time delay circuit is not affected by temperature, thereby improving the accuracy of dead time control.
[0053] In an optional implementation of this embodiment, such as Figure 2 As shown, the first delay unit 10 may further include a first control module 120, a first charging and discharging module 130, and a third inverting module 140. The output terminal of the first control module 120 is electrically connected to the input terminal of the first inverting module 110 and the first charging and discharging module 130, respectively. The input terminal of the first inverting module 110 is also electrically connected to the first charging and discharging module 130. The output terminal of the first inverting module 110 is electrically connected to the second delay unit 20 through the third inverting module 140.
[0054] The first delay unit 10 of the above design includes a first control module 120 for controlling the first charge-discharge module 130 to discharge according to the target control signal; a first inverting module 110 for outputting an inverted signal of the target control signal to a third inverting module 140 after the voltage of the first charge-discharge module 130 after discharge reaches a first threshold voltage; and a third inverting module 140 for outputting a first control signal to the second delay unit 20 according to the inverted signal of the target control signal.
[0055] As a specific implementation method, such as Figure 3 As shown, the first control module 120 of this design may specifically include a first PMOS transistor M1 and a first NMOS transistor M2, the first charge and discharge module 130 includes a first constant current power supply I1 and a first capacitor C1, and the first inverting module 110 includes a second PMOS transistor M3, a second NMOS transistor M4 and a first resistor R1.
[0056] In this configuration, the gate of the first NMOS transistor M2 and the gate of the first PMOS transistor M1 are used to receive the target control signal IN. The source of the first PMOS transistor M1 is used to receive a power supply voltage VDD. The drain of the first PMOS transistor M1 is electrically connected to the first terminal of the first capacitor C1 and the drain of the first NMOS transistor M2, respectively. The source of the first NMOS transistor M2 is grounded through the first constant current power supply I1, and the second terminal of the first capacitor C1 is grounded. The first terminal of the first capacitor C1 is also electrically connected to the gate of the second PMOS transistor M3 and the gate of the second NMOS transistor M4. The source of the second PMOS transistor M3 is used to receive the power supply voltage VDD, and the source of the second NMOS transistor M4 is grounded. The drain of the second PMOS transistor M3 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is electrically connected to the drain of the second NMOS transistor M4 and the third inverting module 140, respectively.
[0057] Based on the first delay unit 10 of the above design, as follows Figure 4 As shown, the second delay unit 20 designed in this scheme may include a second control module 220, a second charge / discharge module 230, and a third inverter 240; the input terminal of the second control module 220 is electrically connected to the third inverter module 140, the output terminal of the second control module 220 is electrically connected to the second charge / discharge module 230 and the second inverter module 210 respectively, and the output terminal of the second inverter module 210 is electrically connected to the third inverter 240.
[0058] The second control module 220 is used to control the second charge-discharge module 230 to charge according to the first control signal sent by the first delay unit 10; the second inverter module 210 is used to output the inverted signal of the first control signal to the third inverter 240 after the voltage of the second charge-discharge module 230 after charging reaches the second threshold voltage; the third inverter 240 is used to output the second control signal OUT according to the inverted signal of the first control signal.
[0059] Specifically, such as Figure 5 As shown, the second control module 220 includes a third PMOS transistor M5 and a third NMOS transistor M6, the second charge / discharge module 230 includes a second constant current power supply I2 and a second capacitor C2, and the second inverting module 210 includes a fourth PMOS transistor M7, a fourth NMOS transistor M8, and a second resistor R2.
[0060] The gates of the third PMOS transistor M5 and the third NMOS transistor M6 are electrically connected to the third inverter module 140. The source of the third PMOS transistor M5 is electrically connected to the power supply voltage VDD through the second constant current power supply I2. The drain of the third PMOS transistor M5 is electrically connected to the drain of the third NMOS transistor M6 and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is grounded, and the source of the third NMOS transistor M6 is grounded. The first terminal of the second capacitor C2 is also electrically connected to the gates of the fourth PMOS transistor M7 and the fourth NMOS transistor M8. The source of the fourth PMOS transistor M7 is electrically connected to the power supply voltage VDD, and the source of the fourth NMOS transistor M8 is grounded. The drain of the fourth PMOS transistor M7 is electrically connected to the drain of the fourth NMOS transistor M8 and the input terminal of the third inverter 240 through the second resistor R2.
[0061] In the above-described design, the first delay unit 10 and the second delay unit 20, when in operation, receive the target control signal IN (assuming it is a high-level signal) from the first PMOS transistor M1 and the first NMOS transistor M2. The first PMOS transistor M1 is turned off, and the first NMOS transistor M2 is turned on, causing the first terminal of capacitor C1 to discharge to ground through the first NMOS transistor M2 and the first constant current power supply I1. The voltage at the first terminal of C1 starts discharging from the power supply voltage VDD. When the voltage at the first terminal of C1 drops to the first threshold voltage of the first inverting module 110, the second terminal of the first resistor R1 outputs the inverted signal of the target control signal. This inverted signal of the target control signal is transmitted... The signal is supplied to the third inverter module 140, which in turn transmits the first control signal (which has the same level as the target control signal) to the third PMOS transistor M5 and the third NMOS transistor M6. This causes the third PMOS transistor M5 to be turned off and the third NMOS transistor M6 to be turned on, thereby causing the second constant current power supply I2 to charge the second capacitor C2 from 0V. When the voltage at the first terminal of the second capacitor C2 reaches the second threshold voltage, the second inverter module 210 outputs the inverted signal of the first control signal to the third inverter 240, which in turn outputs the second control signal OUT (which has the same level as the target control signal).
[0062] From the above principles and circuit structure, assuming the power supply voltage is VDD, the first threshold voltage is V1, and the second threshold voltage is V2, the first time t1 required for the first time delay unit 10 to discharge from voltage VDD to reach the first threshold voltage of the first inverting module 110 can be calculated as follows:
[0063] t1 = C1*(VDD-V1) / I1;
[0064] The second time t2 required for the second delay unit 20 to charge from voltage 0 to the second threshold voltage V2 of the second inverting module 210 can be calculated as follows: t2=C2*V2 / I2;
[0065] Based on the above, the total delay t of the delay circuit is: t = t1 + t2;
[0066] Based on the above, this scheme designs the second PMOS transistor M3 and the fourth PMOS transistor M7 to have the same electrical parameters, the second NMOS transistor M4 and the fourth NMOS transistor M8 to have the same electrical parameters, and the first resistor R1 and the second resistor R2 to have the same electrical parameters. That is, the first inverter module 110 and the second inverter module 210 are completely identical, i.e., V1 = V2; the first capacitor C1 and the second capacitor C2 have the same electrical parameters, i.e., C1 = C2; the first constant current power supply I1 and the second constant current power supply I2 have the same electrical parameters, i.e., I1 = I2.
[0067] Therefore, the above formula t2 can be equivalent to: t2=C1*V1 / I1;
[0068] Correspondingly, the total delay t is: t = t1 + t2 = C1 * VDD / I1;
[0069] Based on the above analysis, it can be seen that the total delay t of the delay circuit designed in this scheme is independent of the threshold voltages of the first inverting module 110 and the second inverting module 210. Therefore, the total delay of the delay circuit designed in this scheme will not be affected by temperature changes, improving the accuracy and controllability of the dead time. Furthermore, the total delay of the delay circuit designed in this scheme is a target fixed value. The magnitude of the target fixed value is determined based on the capacitor, power supply voltage, and constant current power supply current in the circuit. Specifically, the magnitude of the capacitor, power supply voltage, and constant current power supply current can be adaptively adjusted according to the actual application scenario, thereby adjusting the delay circuit to have a suitable dead time.
[0070] It should be noted that the charging and discharging module designed in this scheme can be in the form of a constant current power supply and other rechargeable devices, which are not limited to capacitors; the control module of this scheme can also be in the form of other control switches, not limited to field-effect transistors, such as thyristors, etc.; the inverting module can also be a module with inverting function in other circuit structures composed of field-effect transistors. This scheme does not limit these aspects.
[0071] In an optional implementation of this embodiment, such as Figure 6As shown, based on the second delay unit 20 designed above, the third inverter module 140 of the first delay unit 10 designed in this scheme may include a first inverter 1410 and a second inverter 1420. The input terminals of the first inverter 1410 and the second inverter 1420 are both connected to the output terminal of the first inverter module 110. The output terminal of the first inverter 1410 is connected to the gate of the third NMOS transistor M6, and the output terminal of the second inverter 1420 is connected to the gate of the third PMOS transistor M5.
[0072] In an optional implementation of this embodiment, such as Figure 6 As shown, the first delay unit 10 designed in this scheme may also include a buffer stage 150, which may be set between the third inverting module 140 and the first inverting module 110.
[0073] This application also provides a rectifier circuit, such as Figure 7 As shown, the rectifier circuit includes a power transistor Q1, a rectifier transistor Q2, an inductor L1, a fourth inverter F1, a first delay circuit A1, and a second delay circuit A2; wherein the first delay circuit A1 and the second delay circuit A2 include the delay circuits described in any of the optional embodiments above.
[0074] In this circuit, the gate of power transistor Q1 is electrically connected to the output of the first delay circuit A1, and the input of the first delay circuit A1 is used to receive the PWM signal; the gate of rectifier transistor Q2 is electrically connected to the output of the second delay circuit A2, and the input of the second delay circuit A2 is electrically connected to the output of the fourth inverter F1, and the input of the fourth inverter F1 is used to receive the PWM signal; the drain of power transistor Q1 is used to receive a target voltage VIN, the source of power transistor Q1 is electrically connected to the drain of rectifier transistor Q2 and inductor L1 respectively, the source of rectifier transistor Q2 is grounded, and inductor L1 outputs a delayed control signal VOUT.
[0075] In the rectifier circuit designed above, when the PWM signal is low, power transistor Q1 is cut off and rectifier transistor Q2 is turned on. At this time, inductor L1 is directly grounded after passing through rectifier transistor Q2. When the PWM signal changes from low to high, it passes through the fourth inverter F1 and the second delay circuit A2, controlling rectifier transistor Q2 to turn off. Since the second delay circuit A2 generates a delay when it is high, the total delay of this path is only the transmission delay of the logic gate. Therefore, rectifier transistor Q2 quickly turns off. However, when the PWM signal passes through the first delay circuit A1, since the PWM signal is high, the first delay circuit A1 generates a total delay t1, causing power transistor Q1 to turn on after a delay of t1. This results in power transistor Q1 turning on lagging behind rectifier transistor Q2 turning off, thus creating a dead time. Similarly, when the PWM signal changes from high to low, the opposite is true, and will not be elaborated here.
[0076] The rectifier circuit designed above includes the time delay circuit described above. Therefore, the dead time of the designed rectifier circuit is not affected by temperature, thereby improving the accuracy of dead time control.
[0077] This application also provides a rectifier chip, such as Figure 8 As shown, the rectifier chip 1 includes the delay circuit described in any of the optional embodiments above.
[0078] The rectifier chip designed above contains the delay circuit described above. Therefore, the dead time of the designed rectifier circuit is not affected by temperature, thereby improving the accuracy of dead time control.
[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
Claims
1. A time delay circuit, characterized in that, The delay circuit includes: a first delay unit and a second delay unit; the first delay unit includes a first control module, a first charging and discharging module, a first inverting module and a third inverting module, and the second delay unit includes a second control module, a second charging and discharging module, a second inverting module and a third inverter; The output terminal of the first control module is electrically connected to the input terminal of the first inverting module and the first charging and discharging module, respectively. The input terminal of the first inverting module is also electrically connected to the first charging and discharging module. The output terminal of the first inverting module is electrically connected to the input terminal of the second control module through the third inverting module. The output terminal of the second control module is electrically connected to the second charging and discharging module and the second inverting module, respectively. The output terminal of the second inverting module is electrically connected to the third inverter. The first control module is used to control the first charging and discharging module to discharge according to the target control signal; The first inverting module is used to output the inverted signal of the target control signal to the third inverting module after the voltage of the first charging and discharging module after discharge reaches the first threshold voltage; The third inverting module is used to output a first control signal to the second control module according to the inverted signal of the target control signal; The second control module is used to control the second charging and discharging module to charge according to the first control signal; The second inverter module is used to output the inverted signal of the first control signal to the third inverter after the voltage of the second charge-discharge module reaches the second threshold voltage; The third inverter is used to output a second control signal based on the inverted signal of the first control signal; The target fixed value is the sum of the first time when the voltage of the first delay unit after discharge reaches the first threshold voltage of the first inverting module and the second time when the voltage of the second delay unit after charging reaches the second threshold voltage of the second inverting module. The target fixed value is determined based on the device electrical parameters of the first delay unit and the second delay unit.
2. The time delay circuit according to claim 1, characterized in that, The first control module includes a first NMOS transistor and a first PMOS transistor; the first charge / discharge module includes a first constant current power supply and a first capacitor; and the first inverting module includes a second NMOS transistor, a second PMOS transistor, and a first resistor. The base of the first NMOS transistor and the gate of the first PMOS transistor are used to receive the target control signal. The source of the first PMOS transistor is used to receive a power supply voltage. The drain of the first PMOS transistor is electrically connected to the first terminal of the first capacitor and the drain of the first NMOS transistor, respectively. The source of the first NMOS transistor is grounded through the first constant current power supply, and the second terminal of the first capacitor is grounded. The first terminal of the first capacitor is also electrically connected to the gate of the second NMOS transistor and the gate of the second PMOS transistor. The source of the second PMOS transistor is used to receive the power supply voltage. The source of the second NMOS transistor is grounded. The drain of the second PMOS transistor is connected to the first terminal of the first resistor. The second terminal of the first resistor is electrically connected to the drain of the second NMOS transistor and the third inverting module, respectively.
3. The time delay circuit according to claim 2, characterized in that, The third inverter module includes a first inverter and a second inverter; The input terminals of the first inverter and the second inverter are both electrically connected to the second terminal of the first resistor, and the output terminals of the first inverter and the second inverter are both electrically connected to the second delay unit.
4. The time delay circuit according to claim 2, characterized in that, The first delay unit further includes a buffer stage; The buffer stage is positioned between the first resistor and the third inverting module.
5. The time delay circuit according to claim 2, characterized in that, The second control module includes a third NMOS transistor and a third PMOS transistor; the second charge / discharge module includes a second constant current power supply and a second capacitor; and the second inverting module includes a fourth NMOS transistor, a fourth PMOS transistor, and a second resistor. The gates of the third NMOS transistor and the third PMOS transistor are electrically connected to the third inverting module, respectively. The source of the third PMOS transistor is electrically connected to the power supply voltage through the second constant current power supply. The drain of the third PMOS transistor is electrically connected to the drain of the third NMOS transistor and the first terminal of the second capacitor. The second terminal of the second capacitor is grounded, and the source of the third NMOS transistor is grounded. The first terminal of the second capacitor is also electrically connected to the gate of the fourth NMOS transistor and the gate of the fourth PMOS transistor, respectively. The source of the fourth PMOS transistor is electrically connected to the power supply voltage. The source of the fourth NMOS transistor is grounded. The drain of the fourth PMOS transistor is electrically connected to the source of the fourth NMOS transistor and the input terminal of the third inverter through the second resistor, respectively.
6. The time delay circuit according to claim 5, characterized in that, The second PMOS transistor has the same electrical parameters as the fourth PMOS transistor, the second NMOS transistor has the same electrical parameters as the fourth NMOS transistor, the first resistor has the same electrical parameters as the second resistor, the first capacitor has the same electrical parameters as the second capacitor, and the first constant current power supply has the same electrical parameters as the second constant current power supply.
7. A rectifier circuit, characterized in that, The rectifier circuit includes a power transistor, a rectifier transistor, an inductor, a fourth inverter, a first delay circuit, and a second delay circuit; wherein the first delay circuit and the second delay circuit both include the delay circuit according to any one of claims 1-6. The base of the power transistor is electrically connected to the output terminal of the first delay circuit, and the input terminal of the first delay circuit is used to receive PWM signals. The gate of the rectifier is electrically connected to the output terminal of the second delay circuit, the input terminal of the second delay circuit is electrically connected to the output terminal of the fourth inverter, and the input terminal of the fourth inverter is used to receive the PWM signal. The drain of the power transistor is used to receive a target voltage, the source of the power transistor is electrically connected to the drain of the rectifier and the inductor respectively, and the source of the rectifier is grounded.
8. A rectifier chip, characterized in that, The rectifier chip includes the delay circuit according to any one of claims 1-6.