Chip testing device and testing system
By designing a chip testing device that matches the target server's printed circuit board, the time and manpower costs of power chip verification testing were solved, resulting in more efficient and fair test results. This device is applicable to step-down power chips from different suppliers.
Patent Information
- Application Number
- CN202520242539.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2035-02-17
AI Technical Summary
In the existing technology, the verification and testing circuits for power chips are provided by the supplier, which requires the purchaser to set up multiple testing environments, increasing time and manpower costs, and making it difficult to ensure the fairness of the verification results.
A chip testing device is provided, including a printed circuit board (PCB) with the same physical parameters as the PCB used to connect the step-down power supply chip in the target server. This device supports chip testing from different suppliers, reduces the need for testers to adjust the circuit, and enables testing that simulates a real application environment through multiple connection points and test points.
It reduces testing time and manpower costs, improves the validity and authenticity of test results, supports chip testing from different suppliers, and enhances testing fairness and efficiency.
Smart Images
Figure CN223597830U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of electronics, and in particular to a chip testing device and a testing system. BACKGROUND
[0002] With the increasing of power chip suppliers, the power chip products are also increasing. At present, servers have high requirements for stable and efficient power supply during operation. It is critical to select a power chip that can better meet the operation requirements of the server mainboard in various complex environments.
[0003] Most power chips are Pin to Pin (P2P) series chips with the same pin positions and definitions of two integrated circuit (IC) chips. The verification test circuit of each power chip is usually provided by the supplier. The purchaser needs to build a test environment according to the verification test circuit provided by the supplier, and then perform performance testing, stability testing, compatibility testing and other aspects, aiming to comprehensively evaluate the performance of the chip in various actual operation scenarios.
[0004] It can be seen that the purchaser needs to build a test environment for each power chip provided by the manufacturer, which requires a large amount of time and labor costs. Moreover, the verification test circuit of the power chip is provided by the supplier, which is difficult to guarantee the fairness of the verification results. CONTENT OF THE INVENTION
[0005] The present application provides a chip testing device and a testing system, which can reduce the time and labor costs of the tester for testing the step-down power chip, and the scheme can improve the effectiveness and authenticity of the test results.
[0006] In a first aspect, an embodiment of the present application provides a chip testing device applied to testing a step-down power chip, wherein the step-down power chip is used to provide services for a target server.
[0007] The device comprises a printed circuit board (PCB), wherein the PCB comprises a first area and a second area.
[0008] A plurality of connection points are arranged in the first area, and the plurality of connection points correspond one-to-one to a plurality of to-be-tested pins of the step-down power chip. Each connection point is used to connect to a corresponding to-be-tested pin. The second area comprises at least one input point and a plurality of test points. The input point is used to receive an input signal, and at least one test point in the plurality of test points is used to output a test signal.
[0009] The physical parameters of the PCB are the same as the physical parameters of a printed circuit board in the target server used to connect the step-down power chip.
[0010] The chip testing device provided by the embodiments of the present application can support the testing of the buck power supply chips provided by different suppliers. The tester can change the buck power supply chip to be tested by adjusting the buck power supply chip connected to the multiple connection points in the first area, without the need to design or change the circuit connected to the buck power supply chip, thereby reducing the time cost and labor cost of the tester. The PCB in the chip testing device has the same physical parameters as the printed circuit board in the target server for connecting the buck power supply chip. Such a design can make the chip testing device simulate the printed circuit board in the target server for connecting the buck power supply chip, so that the buck power supply chip to be tested can be tested in a close-to-real application environment, thereby improving the effectiveness and authenticity of the testing and facilitating the selection of a buck power supply chip suitable for the target server.
[0011] In a possible implementation, the chip testing device provided by the embodiments of the present application includes a target package type chip, and the target package type is TQFN-25 package.
[0012] The embodiments of the present application provide a chip testing device for a buck power supply chip in TQFN-25 package, and solve the problem that there is no testing device for the buck power supply chip in TQFN-25 package in the industry. The tester does not need to design an additional testing device for the buck power supply chips provided by different suppliers.
[0013] In a possible implementation, the chip testing device provided by the embodiments of the present application includes the following one or more of the physical parameters of the PCB:
[0014] Material and thickness.
[0015] In the embodiments of the present application, the physical parameters of the PCB in the chip testing device are the same as the physical parameters of the printed circuit board in the target server for connecting the buck power supply chip, which can include the same material and the same thickness. Optionally, the PCB in the chip testing device can also include some peripheral circuits that are the same as or close to the peripheral circuits on the printed circuit board in the target server for connecting the buck power supply chip.
[0016] In a possible implementation, the chip testing device provided by the embodiments of the present application includes at least one first test point and at least one second test point, wherein the first test point is connected to any connection point through at least one functional module or component, and the second test point is connected to any connection point.
[0017] In a possible implementation, the chip testing device provided by the embodiment of the present application comprises a third test point in the at least one first test point, and the third test point is connected to any connection point through a functional module.
[0018] The functional module is any one of the following functional modules:
[0019] a boot module and an enabling module.
[0020] In a possible implementation, the chip testing device provided by the embodiment of the present application comprises a fourth test point in the at least one first test point, and the fourth test point is connected to any connection point through a plurality of functional modules.
[0021] The plurality of functional modules comprise a boot module and an absorbing module; or the plurality of functional modules comprise a feedback module and an output module.
[0022] In a possible implementation, the chip testing device provided by the embodiment of the present application comprises a feedback module, and an equivalent resistance of the feedback module is adjustable.
[0023] In a possible implementation, the chip testing device provided by the embodiment of the present application comprises a feedback module, and the feedback module comprises a plurality of resistance branches and a switch circuit, and the switch circuit is used to connect one resistance branch to an output end of the feedback module.
[0024] In a second aspect, the embodiment of the present application further provides a testing system, which can comprise the chip testing device provided by the first aspect and any possible implementation thereof.
[0025] In a possible implementation, the testing system provided by the embodiment of the present application can further comprise a to-be-tested step-down power supply chip. BRIEF DESCRIPTION OF DRAWINGS
[0026] Figure 1 A structural schematic diagram of a chip testing device provided by the embodiment of the present application;
[0027] Figure 2 A circuit structural schematic diagram of a chip testing device provided by the embodiment of the present application;
[0028] Figure 3 A circuit structural schematic diagram of a feedback module provided by the embodiment of the present application;
[0029] Figure 4 A layout diagram of the circuit structure shown; Figure 2
[0030] Figure 5 A structural schematic diagram of a testing system provided by the embodiment of the present application. DETAILED DESCRIPTION
[0031] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application. The embodiments in the present application and the features in the embodiments can be combined with each other in a non-conflicting manner. Moreover, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described can be performed in an order different from the order shown.
[0032] The terms "first" and "second" in the specification and claims of the present application and the above-described drawings are used to distinguish different objects, rather than to describe a specific sequence. In addition, the term "comprising" and any variations thereof are intended to cover the non-exclusive protection. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed or can optionally include other steps or units inherent to the process, method, product or device. "Multiple" in the present application can mean at least two, for example, can be two, three or more, and the embodiments of the present application are not limited. "A and / or B" in the present application can mean A, B, A and B.
[0033] Figure 1 An exemplary structure schematic diagram of a chip testing device is shown. The chip testing device can be used to test different suppliers' power supply chips respectively, or to perform verification testing. The chip testing device can reduce the time cost and labor cost of the testing personnel of the purchaser. The chip testing device can help to improve the fairness of each power supply chip testing, and is conducive to selecting a power supply chip suitable for the target server.
[0034] The chip testing device provided by the embodiments of the present application can be applied to testing a step-down power supply chip. The step-down power supply chip is used to provide services for a target server. Please refer to Figure 1The device comprises a printed circuit board (PCB). The PCB comprises a first region and a second region. The first region is provided with a plurality of connection points, which correspond one-to-one to a plurality of to-be-tested pins of the voltage reduction power supply chip. Each connection point is used to connect to a corresponding to-be-tested pin. The second region comprises at least one input point and a plurality of test points. The input point is used to receive an input signal. At least one test point of the plurality of test points is used to output a test signal. The physical parameters of the PCB are the same as the physical parameters of a printed circuit board in the target server used to connect the voltage reduction power supply chip.
[0035] In some application scenarios, the chip testing device can also be used as an Evaluation Module (EVM) board. The EVM board generally refers to a hardware platform provided by a chip manufacturer to facilitate developers to quickly test the performance of a new chip and verify the functions. The chip to be evaluated and necessary peripheral circuits can be integrated on such a board. Developers can directly test various functions and characteristics of the chip through the EVM board.
[0036] The connection points provided in the first region of the PCB can be used to connect the voltage reduction power supply chip. The to-be-tested pins of the voltage reduction power supply chip can be welded on the connection points in the first region by the tester. The number of connection points provided in the first region can be the same as the number of to-be-tested pins of the voltage reduction power supply chip. The plurality of connection points in the first region correspond one-to-one to the plurality of to-be-tested pins of the voltage reduction power supply chip. One connection point is used to connect only to the to-be-tested pin corresponding to the connection point.
[0037] The second region of the PCB can be provided with at least one input point and a plurality of test points. The input point can be used to receive an input voltage or an input current, etc. The tester can adjust the input voltage or the input current provided to the input point to adjust the test environment of the chip testing device.
[0038] The plurality of test points in the second region can satisfy a plurality of test contents. For one test content, one or more test points corresponding to the test content can be used to output a test signal. The tester can output a test signal through one or more test points corresponding to a test content to evaluate the voltage reduction power supply chip.
[0039] The chip testing device provided by the application can be used to test or verify test the buck power supply chips provided by different suppliers. Such design improves the testing efficiency, reduces the time cost, does not need to adjust the testing circuit, and improves the testing fairness. In addition, the physical parameters of the PCB in the chip testing device are the same as the physical parameters of the printed circuit board in the target server for connecting the buck power supply chip, so that the chip testing device can simulate the printed circuit board in the target server, and can provide the to-be-tested buck power supply chip with the working environment in the target server. Such design is beneficial to the testing personnel to select the buck power supply chip more suitable for the target server.
[0040] In a possible implementation, the physical parameters of the PCB in the chip testing device include one or more of the following: material, thickness. The material of the PCB in the chip testing device can be the same as the material of the printed circuit board in the target server for connecting the buck power supply chip, and / or the thickness (i.e., layer thickness parameter) of the PCB in the chip testing device can be the same as the thickness of the printed circuit board in the target server for connecting the buck power supply chip. In some examples, the components used in the PCB in the chip testing device can be selected according to the component selection standard of the printed circuit board in the target server for connecting the buck power supply chip. Such design makes the testing environment of the chip testing device simulate the real running state of the buck power supply chip in the target server to the greatest extent, and is beneficial to selecting the buck power supply chip more suitable for the target server.
[0041] In a possible implementation, the buck power supply chip is a chip of a target packaging type, and the target packaging type is TQFN-25 packaging. The buck power supply chip in TQFN-25 packaging can include a PASS pin, a VIN pin, a VCC pin, a VDRV pin, a PG pin, an EN pin, an IIC pin, a BST pin, a SW pin, an FB pin, a PS# pin, an ISUM pin, an IREF pin, an ADDR pin, a TAKE pin, a GND pin, and a SET pin.
[0042] The to-be-tested pins of the buck power supply chip include a PASS pin, a VIN pin, a VCC pin, a VDRV pin, a PG pin, an EN pin, an IIC pin, a BST pin, a SW pin, an FB pin, a PS# pin, an ISUM pin, an IREF pin, an ADDR pin, a TAKE pin, and a GND pin. For convenience of distinction, they are respectively referred to as a PASS to-be-tested pin, a VIN to-be-tested pin, a VCC to-be-tested pin, a VDRV to-be-tested pin, a PG to-be-tested pin, an EN to-be-tested pin, an IIC to-be-tested pin, a BST to-be-tested pin, a SW to-be-tested pin, an FB to-be-tested pin, a PS# to-be-tested pin, an ISUM to-be-tested pin, an IREF to-be-tested pin, an ADDR to-be-tested pin, a TAKE to-be-tested pin, and a GND to-be-tested pin.
[0043] Please refer to Figure 2 The plurality of connection points of the chip testing device can include a PASS connection point, a VIN connection point, a VCC connection point, a VDRV connection point, a PG connection point, an EN connection point, an IIC connection point, a BST connection point, a SW connection point, an FB connection point, a PS# connection point, an ISUM connection point, an IREF connection point, an ADDR connection point, a TAKE connection point, and a GND connection point.
[0044] In the chip testing device, an input point S1 can be connected to the VIN connection point through an input module. The input point S1 is configured to receive an input signal, such as an input voltage or an input current, and the input module can provide the input signal to the VIN to-be-tested pin through the VIN connection point.
[0045] In a possible implementation, in the first region, the plurality of test points include at least one first test point and at least one second test point, wherein the first test point is connected to the connection point through at least one functional module or component, and the second test point is connected to the connection point.
[0046] In the embodiments of the present application, the test points are configured to output test signals, which can include but are not limited to test voltages, test currents, test loads, and the like. A tester can use a test device to connect the test points and collect or obtain the test signals.
[0047] The second test point can refer to a test point directly connected to the to-be-tested pin of the buck power supply chip. The first test point can refer to a test point indirectly connected to the connection point. The first test point can be connected to any connection point through at least one functional module. When each connection point is respectively connected to a corresponding to-be-tested pin of the chip, the first test point is connected to the to-be-tested pin of the chip through at least one functional module. Alternatively, the first test point can be connected to any connection point through a component. When each connection point is respectively connected to a corresponding to-be-tested pin of the chip, the first test point is connected to the to-be-tested pin of the chip through the component.
[0048] Please combine Figure 2 , the second test point can be implemented as test point T1, which is connected with the VCC connection point. Alternatively, the second test point can be implemented as test point T2, which is connected with the PG connection point.
[0049] In a possible design, the at least one first test point can include a third test point. The third test point is connected with any connection point through one functional module. The third test point can represent the first test point connected with the connection point through one functional module.
[0050] The one functional module is any one of the following functional modules:
[0051] boot module, enable module.
[0052] The boot module can be used to control the chip initialization process. Various enable modes can be configured in the enable module, which are driven by resistance voltage division, or driven by external high level.
[0053] Please combine Figure 2 , the third test point can be implemented as test point P1, which is connected with the BST connection point through the boot module. Alternatively, the third test point can be implemented as test point P2, which is connected with the EN connection point through the enable module.
[0054] In a possible design, the at least one first test point can include the fourth test point connected with any connection point through multiple functional modules. The fourth test point can represent the first test point connected with the connection point through multiple functional modules.
[0055] The multiple functional modules include boot module and snubber absorption module; or the multiple functional modules include feedback module and output module.
[0056] The snubber absorption module can also be generally referred to as snubber absorption module, which can be matched with different parameters of resistance and capacitance, and can always absorb voltage spikes, overshoot and high-frequency ringing in switching power supply.
[0057] Please combine Figure 2 , the fourth test point can be implemented as test point M1, which is connected with the BST connection point through the snubber absorption module and the boot module. Alternatively, the fourth test point can be implemented as test point M2, which is connected with the FB connection point through the feedback module and the output module.
[0058] The PCB of the chip testing device can include components directly connected to the connection points. For example, the PCB can include resistors R1, R2, R3, R4, R5, R6, R7, R8, and R9. The PCB can include capacitors C1, C2, and C3.
[0059] The first pole of the capacitor C1 is connected to the VCC connection point and the test point T1, the first end of the resistor R1, the first end of the resistor R4, the first end of the resistor R3, and the second pole of the capacitor C1 is connected to the AGND end. The second end of the resistor R1 is connected to the first end of the resistor R2, and the first end of the resistor R6 is connected to the TAKE connection point. The second end of the resistor R4 is connected to the VDEV connection point and the first pole of the capacitor C3. The second pole of the capacitor C3 is connected to the GND end. The second end of the resistor R2 is connected to the GND end. The second end of the resistor R6 is connected to the PASS connection point. The second end of the resistor R3 is connected to the first end of the resistor R5, and the second end of the resistor R5 is connected to the GND end.
[0060] The first pole of the capacitor C2 is connected to the ISUM connection point, and the second pole is connected to the AGND end. The first end of the resistor R9 is connected to the IREF connection point, and the second end is connected to the AGND end. The first end of the resistor R7 is connected to the ADDR connection point, and the second end is connected to the AGND end. The PS connection point is usually connected to the AGND end. The GND connection point is connected to the GND end.
[0061] The components on the PCB of the chip testing device connected to the connection points can simulate the layout of the printed circuit board in the target server for connecting the voltage reduction power supply chip, making the chip testing device more similar to the printed circuit board in the target server for connecting the voltage reduction power supply chip, and providing a close-to-real test environment.
[0062] Optionally, the PCB of the chip testing device can also include an IIC communication module. The IIC communication module is used to connect the IIC connection end, and the IIC communication module can be used to configure and monitor the chip. The IIC communication module has an IIC circuit interface, and the tester can connect the test equipment to the IIC circuit interface to test the communication function of the voltage reduction power supply chip.
[0063] The input module can include an input inductor LIN and an input capacitor CIN. The first end of the input inductor LIN is connected to the input point PIN, and the second end is connected to the first pole of the input capacitor CIN and the VIN connection point. The second pole of the input capacitor CIN is connected to the GND.
[0064] The output module can include an output inductor LOUT and an output capacitor COUT. A first end of the output inductor LOUT is connected to the SW connection point, a second end is connected to a test point M2, a first pole of the output capacitor COUT, and an output end of the feedback module. A second pole of the output capacitor COUT is connected to the GND end.
[0065] In a possible implementation, the equivalent resistance of the feedback module is not adjustable. In order to change the test content or the test environment, the tester also needs to replace the feedback module with another feedback module with a different equivalent resistance. When the tester is soldering a new feedback module, parasitic parameters and abnormal risks may be introduced.
[0066] In another possible implementation, the equivalent resistance of the feedback module is adjustable. By adjusting the equivalent resistance of the feedback module, different test conditions can be provided.
[0067] In a possible design, the feedback module includes a plurality of resistance branches and a switch circuit, and the switch circuit is used to connect one resistance branch to the output end of the feedback module. Such a design facilitates the tester to quickly adjust the equivalent resistance of the feedback module, so as to adjust the test content or the test environment.
[0068] Figure 3 An exemplary structure diagram of a feedback module is shown, in which the FB+ end of the feedback module is connected to the first end of a first resistor RF1, the second end of the first resistor RF1 is connected to the first pole of a capacitor CF, and the second pole of the capacitor CF is connected to the output end VOUT of the feedback module. The FB- end of the feedback module is connected to the first end of each resistance branch. The switch circuit includes a plurality of selection ends and an output end. The plurality of selection ends are one-to-one corresponding to the plurality of resistance branches, and each selection end is connected to the second end of the corresponding resistance branch. The output end of the switch circuit is connected to the first end of a second resistor RF2, and the second end of the second resistor RF2 is connected to the output end VOUT of the feedback module.
[0069] The equivalent resistances of the resistance branches are different. The switch branch is used to connect one resistance branch in the plurality of resistance branches to the output end VOUT of the feedback module. The structure of the switch circuit is not limited in the embodiments of the present application. It should be noted that the circuit structure capable of realizing the functions of the switch circuit is acceptable. In some examples, the switch circuit can include a single-pole multi-throw switch. The movable end of the single-pole multi-throw switch can be implemented as the output end of the switch circuit. The fixed end of the single-pole multi-throw switch can be implemented as the selection end of the switch circuit.
[0070] As Figure 2 A circuit schematic diagram of a chip test device is shown. The plurality of test points of the chip test device can support, but are not limited to, the following test contents:
[0071] Static ripple and noise testing, transient response testing, startup and reset testing, overshoot and undershoot testing, switching frequency testing, jitter testing, Bode plot testing, efficiency testing, overcurrent and short circuit protection testing, thermal design testing, etc.
[0072] In addition, the chip testing unit can also support thermal verification testing and signal integrity verification testing of buck power supply chips. Due to its high integration, the chip testing unit offers high portability. It can be placed in the thermal environment required for testing the target server. For example, it can be set up in a temperature chamber to verify and test the buck power supply chip at ambient temperatures of 0°C or 55°C.
[0073] For signal integrity testing, the PCB of a chip test device includes multiple connection points, multiple test points, and at least one input point. The PCB of the chip test device can also include peripheral circuits, including functional modules and components. In this design, the chip test device can simulate the PCB of a target server used to connect a step-down power supply chip. Using such a chip test device allows for more convenient testing of the actual signal state, eliminating redundant interference under full-board conditions.
[0074] Figure 4 for Figure 2 An exemplary layout diagram of the provided chip testing apparatus. Figure 4 This diagram illustrates the first area of the PCB, the input points, the test points, and the relative positions of the components on the PCB. During the PCB design of the chip testing device, power devices are arranged as compactly as possible, distributed around the first area. Input capacitors in the input module can be placed close to the buck power supply chip. Signal ground (e.g.) Figure 2 (as shown in the diagram) and power ground (e.g.) Figure 2 The GND terminal shown is a single-point connection. In the chip testing setup, the trace connecting to the SW pin of the buck power supply chip can be short and thick, without vias, to avoid interference with other signals. Additionally, using the largest possible ground plane reduces noise and facilitates heat dissipation for the buck power supply chip.
[0075] On the other hand, this application also provides a testing system, which may include any of the chip testing devices provided in this application. Optionally, such as Figure 5 As shown, the test system may also include the step-down power supply chip under test. Optionally, the test system may also include a test signal acquisition device. Testers can connect the test signal acquisition device to the test point to acquire the test signals output from the test point.
[0076] Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.
Claims
1. A chip testing apparatus characterized by comprising: The application is applied to test a step-down power supply chip used for providing service for a target server. The device comprises a printed circuit board (PCB), wherein the PCB comprises a first area and a second area; The first area is provided with a plurality of connection points corresponding to a plurality of to-be-tested pins of the step-down power supply chip, each connection point being used for connecting with a corresponding to-be-tested pin; the second area comprises at least one input point and a plurality of test points, the input point being used for receiving an input signal, and at least one test point of the plurality of test points being used for outputting a test signal. The physical parameters of the PCB are the same as the physical parameters of a printed circuit board in the target server used for connecting the step-down power supply chip.
2. The apparatus of claim 1, wherein, The step-down power supply chip is a chip of a target packaging type, and the target packaging type is TQFN-25 packaging.
3. The apparatus of claim 1, wherein, The physical parameters of the PCB comprise one or more of the following: Material and thickness.
4. The apparatus of claim 1, wherein, The plurality of test points comprise at least one first test point and at least one second test point, wherein the first test point is connected with any connection point through at least one functional module or component, and the second test point is connected with any connection point.
5. The apparatus of claim 4, wherein, The at least one first test point comprises a third test point, and the third test point is connected with any connection point through one functional module. The one functional module is any one of the following functional modules: A boot module and an enable module.
6. The apparatus of claim 4, wherein, The at least one first test point comprises a fourth test point, and the fourth test point is connected with any connection point through a plurality of functional modules. The plurality of functional modules comprise a boot module and an absorption module; or the plurality of functional modules comprise a feedback module and an output module.
7. The apparatus of claim 6, wherein, The equivalent resistance of the feedback module is adjustable.
8. The apparatus of claim 7, wherein, The feedback module comprises a plurality of resistance branches and a switch circuit, and the switch circuit is used for connecting one resistance branch with an output end of the feedback module.
9. A test system, characterized by The system further comprises a to-be-tested step-down power supply chip.
10. The system of claim 9, wherein, The system further comprises a to-be-tested step-down power supply chip.