Photonic interconnection wafer and electronic / photonic package

Abstract

The utility model relates to a photon interconnection wafer and an electronic / photon package. A photonic interconnect wafer may include a substrate, a dielectric waveguide including a core portion and a cladding portion and formed over the substrate, a first photonic coupler formed at a first end of the dielectric waveguide, and a second photonic coupler formed at a second end of the dielectric waveguide. The dielectric waveguide may include a planar geometry within the cladding portion such that a surface of the dielectric waveguide is parallel to the first surface of the photonic interconnect wafer. The first photonic coupler and the second photonic coupler may each be configured to couple a photonic signal into and out of the photonic interconnect wafer such that a photonic signal channel connects the first photonic coupler, the dielectric waveguide, and the second photonic coupler. The photonic interconnect wafer may further couple photonic signals into and out of the first dielectric window and the second dielectric window.

Description

Technical Field

[0001] This utility model relates to a photonic interconnect chip, and more particularly to a photonic interconnect chip including a photonic coupler and an electronic / photonic package including the photonic interconnect chip. Background Technology

[0002] Many computing applications use optical (i.e., photonic) signals to provide secure, high-speed data transmission. Various emerging technologies are also under development that offer the ability to perform computational operations directly on optical / photonic signals. Silicon photonics is a promising technological field that uses semiconductor device fabrication techniques to provide systems that incorporate integrated electronic and photonic components. These components can be used to generate, route, modulate, process, and detect light. Together, these functions form a photonic analog electronic integrated circuit (EIC), and thus a photonic integrated circuit (PIC). Utility Model Content

[0003] According to an embodiment of the present invention, a photonic interconnect chip is provided. The photonic interconnect chip includes a substrate, a dielectric waveguide, a first photonic coupler, and a second photonic coupler. The dielectric waveguide includes a core portion and a cladding portion and is formed on the substrate. The first photonic coupler is formed at a first end of the dielectric waveguide, and the second photonic coupler is formed at a second end of the dielectric waveguide. The dielectric waveguide may contain a planar geometry within the cladding portion, such that the surface of the dielectric waveguide is parallel to the first surface of the photonic interconnect chip. The first photonic coupler and the second photonic coupler may each be configured to couple photonic signals into and out of the photonic interconnect chip, such that a photonic signal channel connects the first photonic coupler, the dielectric waveguide, and the second photonic coupler.

[0004] In one embodiment, the photonic interconnect chip further includes: a first dielectric window located at a first position on a first surface of the photonic interconnect chip; and a second dielectric window located at a second position on the first surface of the photonic interconnect chip, wherein the first photonic coupler and the second photonic coupler each couple multiple photonic signals into and out of the photonic interconnect chip through the first dielectric window and the second dielectric window, respectively.

[0005] In one embodiment, the first photonic coupler includes a first grating coupler that couples a plurality of first input photonic signals received from a first dielectric window into a dielectric waveguide and transmits a plurality of first output photonic signals received from the dielectric waveguide through the first dielectric window; and the second photonic coupler includes a second grating coupler that couples a plurality of second input photonic signals received from a second dielectric window into the dielectric waveguide and transmits a plurality of second output photonic signals received from the dielectric waveguide through the second dielectric window.

[0006] In one embodiment, the first photonic coupler includes a first angled reflector that couples a plurality of first input photonic signals received from a first dielectric window into a dielectric waveguide and transmits a plurality of first output photonic signals received from the dielectric waveguide through the first dielectric window; and the second photonic coupler includes a second angled reflector that couples a plurality of second input photonic signals received from a second dielectric window into a dielectric waveguide and transmits a plurality of second output photonic signals received from the dielectric waveguide through the second dielectric window.

[0007] In one embodiment, the photonic interconnect chip further includes: a first dielectric window located on a second surface of the photonic interconnect chip, the second surface being perpendicular to the first surface of the photonic interconnect chip; and a second dielectric window located on a third surface of the photonic interconnect chip, the third surface being perpendicular to the first surface of the photonic interconnect chip and parallel and opposite to the second surface, wherein the first photonic coupler and the second photonic coupler each couple multiple photonic signals into and out of the photonic interconnect chip through the first dielectric window and the second dielectric window, respectively.

[0008] In one embodiment, the first photonic coupler includes a first edge coupler that couples a plurality of first input photonic signals received from a first dielectric window into a dielectric waveguide and transmits a plurality of first output photonic signals received from the dielectric waveguide through the first dielectric window; and the second photonic coupler includes a second edge coupler that couples a plurality of second input photonic signals received from a second dielectric window into the dielectric waveguide and transmits a plurality of second output photonic signals received from the dielectric waveguide through the second dielectric window.

[0009] According to a further embodiment, an electronic / photonic package is provided. The electronic / photonic package includes a first photonic component, a second photonic component, and a photonic interconnect chip. The first photonic component includes a plurality of first photonic signal channels, the second photonic component includes a plurality of second photonic signal channels, and the photonic interconnect chip includes a plurality of dielectric waveguides. The photonic interconnect chip is coupled to the first and second photonic components, such that the first photonic signal channels are optically coupled to the second photonic signal channels through the plurality of dielectric waveguides.

[0010] In one embodiment, the electronic / photonic package further includes: an interconnect, wherein the first photonic component and the second photonic component are formed as separate wafers and are attached to and electrically coupled to the interconnect, and wherein a first portion of the photonic interconnect wafer is mechanically and optically coupled to the first photonic component, and a second portion of the photonic interconnect wafer is mechanically and optically coupled to the second photonic component, such that the photonic interconnect wafer is configured as an in-package photonic coupler.

[0011] In one embodiment, the photonic interconnect chip in the electronic / photonic package further includes: a substrate; an cladding portion formed on the substrate; a plurality of dielectric waveguide core portions formed within the cladding portion; a plurality of first photonic couplers; and a plurality of second photonic couplers, wherein each of the plurality of first photonic couplers and the plurality of second photonic couplers is coupled to a first end and a second end of a plurality of dielectric waveguide core portions, and wherein the plurality of first photonic couplers and the plurality of second photonic couplers guide a plurality of photonic signals into and out of the photonic interconnect chip, such that a corresponding photonic signal channel connects each dielectric waveguide to a corresponding one of the plurality of first photonic couplers and the plurality of second photonic couplers.

[0012] In one embodiment, a plurality of dielectric waveguides are formed on a coplanar substrate and include a fan-out configuration, or a plurality of dielectric waveguides are arranged in a three-dimensional configuration within an encapsulated portion. Attached Figure Description

[0013] The complete disclosure is based on the following detailed description and accompanying drawings. It should be noted that, in accordance with industry practice, the illustrations are not necessarily drawn to scale. In fact, the dimensions of components may be arbitrarily enlarged or reduced for clarity.

[0014] Figure 1 This is a schematic diagram of various components that can be used in a photonic computing system.

[0015] Figure 2 This is a top view schematic diagram illustrating a photonic integrated circuit according to various embodiments.

[0016] Figure 3A This is a vertical cross-sectional view of a photonic integrated circuit formed on a silicon-on-insulator substrate according to various embodiments.

[0017] Figure 3B It is shown according to various embodiments Figure 3A A vertical cross-sectional view of a portion of a photonic integrated circuit, showing the photonic components.

[0018] Figure 3C It is shown according to various embodiments Figure 3A A vertical cross-sectional view of a further portion of the photonic integrated circuit, showing the photonic coupler.

[0019] Figure 3D It is shown according to various embodiments Figure 3A A vertical cross-sectional view of a further portion of the photonic integrated circuit, showing a further photonic coupler.

[0020] Figure 4 This is a vertical cross-sectional view illustrating an electronic / photonic package including an optical engine and electronic components, according to various embodiments.

[0021] Figure 5A This is a top view illustrating a further electronic / photonic package including a photonic interconnect chip according to various embodiments.

[0022] Figure 5B It is shown according to various embodiments Figure 5A Vertical cross-sectional view of the electronic / photonic package.

[0023] Figure 6A This is a top view of a photonic interconnect wafer that optically connects a first photonic component to a second photonic component, according to various embodiments.

[0024] Figure 6B This is a top view of a photonic interconnect chip that shows optical connections between a first photonic component, a second photonic component, a third photonic component, and a fourth photonic component, according to various embodiments.

[0025] Figure 7 This is a vertical cross-sectional view illustrating a further electronic / photonic package containing a photonic interconnect chip according to various embodiments.

[0026] Figure 8A This is a top view illustrating a further electronic / photonic package 800 including a first photonic interconnect chip, a second photonic interconnect chip, and a third photonic interconnect chip, according to various embodiments.

[0027] Figure 8B It is shown according to various embodiments Figure 8A A vertical cross-sectional view of the electronic / photonic package.

[0028] Figure 8C It is shown according to various embodiments Figure 8B A detailed three-dimensional perspective view of the fiber optic array unit.

[0029] Figure 9A This is a top view illustrating a further electronic / photonic package comprising multiple photonic interconnect chips according to various embodiments.

[0030] Figure 9B It is shown according to various embodiments Figure 9A A cross-sectional view of a portion of an electronic / photonic package.

[0031] Figure 10A This is a top view illustrating a further electronic / photonic package comprising multiple photonic interconnect chips according to various embodiments.

[0032] Figure 10B It is shown according to various embodiments Figure 10A A cross-sectional view of a portion of an electronic / photonic package.

[0033] Figure 11This is a top view illustrating a further electronic / photonic package including a first component package and a second component package according to various embodiments.

[0034] Figure 12 This is a cross-sectional view illustrating a further electronic / photonic package including a photonic interconnect wafer with edge couplers, according to various embodiments.

[0035] Figure 13 This is a cross-sectional view illustrating, according to various embodiments, a further electronic / photonic package comprising a photonic interconnect wafer that couples photonic signals between two hybrid interconnects.

[0036] Figure 14A This is a cross-sectional view illustrating an intermediate structure that can be used to form a photonic interconnect wafer, according to various embodiments.

[0037] Figure 14B This is a cross-sectional view illustrating a further intermediate structure that can be used to form a photonic interconnect wafer, according to various embodiments.

[0038] Figure 14C This is a cross-sectional view illustrating a further intermediate structure that can be used to form a photonic interconnect wafer, according to various embodiments.

[0039] Figure 14D This is a cross-sectional view illustrating a further intermediate structure that can be used to form a photonic interconnect wafer, according to various embodiments.

[0040] Figure 14E This is a top view illustrating, according to various embodiments, a further intermediate structure that can be used to form a photonic interconnect wafer.

[0041] Figure 15A This is a cross-sectional view illustrating a further intermediate structure that can be used to form a photonic interconnect wafer, according to various embodiments.

[0042] Figure 15B This is a cross-sectional view illustrating a further intermediate structure that can be used to form a photonic interconnect wafer, according to various embodiments.

[0043] Figure 15C This is a cross-sectional view illustrating a further intermediate structure that can be used to form a photonic interconnect wafer, according to various embodiments.

[0044] Figure 16A This is a vertical cross-sectional view illustrating, according to various embodiments, a further intermediate structure that can be used to form a photonic interconnect wafer.

[0045] Figure 16B This is a vertical cross-sectional view illustrating, according to various embodiments, a further intermediate structure that can be used to form a photonic interconnect wafer.

[0046] Figure 16CThis is a vertical cross-sectional view illustrating, according to various embodiments, a further intermediate structure that can be used to form a photonic interconnect wafer.

[0047] Figure 16D This is a vertical cross-sectional view of a photonic interconnect wafer according to various embodiments.

[0048] Figure 16E This is a vertical cross-sectional view of a further photonic interconnect wafer according to various embodiments.

[0049] Figure 16F This is a vertical cross-sectional view of a further photonic interconnect wafer according to various embodiments.

[0050] Figure 16G This is a vertical cross-sectional view of a further photonic interconnect wafer according to various embodiments.

[0051] Figure 16H This is a vertical cross-sectional view of a further photonic interconnect wafer according to various embodiments.

[0052] Figure 17A This is a top view of a photonic interconnect wafer including edge couplers, according to various embodiments.

[0053] Figure 17B It is shown according to various embodiments Figure 17A A vertical cross-sectional view of a photonic interconnect chip.

[0054] Figure 18A This is a top view illustrating, according to various embodiments, an intermediate structure that can be used to form a photonic interconnect wafer containing a grating coupler.

[0055] Figure 18B It is shown according to various embodiments Figure 18A A cross-sectional view of the intermediate structure.

[0056] Figure 18C This is a cross-sectional view of a photonic interconnect wafer including a grating coupler, according to various embodiments.

[0057] Figure 19A This is a vertical cross-sectional view illustrating an intermediate structure for forming a photonic interconnect wafer, according to various embodiments.

[0058] Figure 19B This is a vertical cross-sectional view illustrating a further intermediate structure for forming a photonic interconnect wafer, according to various embodiments.

[0059] Figure 19C This is a vertical cross-sectional view illustrating a further intermediate structure for forming a photonic interconnect wafer, according to various embodiments.

[0060] Figure 19DThis is a top view illustrating further intermediate structures for forming a photonic interconnect wafer, according to various embodiments.

[0061] Figure 20 This is a flowchart illustrating a method for forming a photonic interconnect wafer according to various embodiments.

[0062] The reference numerals in the attached figures are explained as follows:

[0063] 102: Photon Source

[0064] 104: Dielectric waveguide

[0065] 104a: First group of dielectric waveguides

[0066] 104b: Second group of dielectric waveguides

[0067] 104c: Group 3 dielectric waveguide

[0068] 104d: Group 4 dielectric waveguide

[0069] 104e: Group 5 Dielectric Waveguide

[0070] 106: Photon Detector

[0071] 108: Photon Modulator

[0072] 110: Photon Processing Component

[0073] 112a: First photonic coupler

[0074] 112b: Second photonic coupler

[0075] 114: Beam Splitter

[0076] 116: Multiplexer

[0077] 118: Circuit Pad

[0078] 200, 200d, 200e, 200f, 200g: Photonic integrated circuits

[0079] 200a: First Photonic Integrated Circuit

[0080] 200b, 200d: Second photonic integrated circuit

[0081] 200c: Third Photonic Integrated Circuit

[0082] 202a: Launch Path

[0083] 202b: Receive Path

[0084] 204: Fiber Optic

[0085] 204a: Output optical fiber

[0086] 204b: Input fiber

[0087] 204h: Horizontally oriented optical fiber

[0088] 204V: Vertically oriented optical fiber

[0089] 300b, 300d: Partial

[0090] 302: Substrate

[0091] 302a: Silicon substrate layer

[0092] 302b: Silicon layer

[0093] 304: Oxide layer

[0094] 306a: Grating Coupler

[0095] 306b: Edge Coupler

[0096] 306c: Angled reflector

[0097] 308: Trench Array

[0098] 310, 310c: Photon signals

[0099] 310a: First photon signal

[0100] 310b: Second vertically propagating photon signal

[0101] 312: Undercut Structure

[0102] 313b: Internal surface

[0103] 400, 500, 700, 800, 900, 1000, 1100, 1200, 1300: Electronic / Photonic Packaging

[0104] 402: Optical Engine

[0105] 402a: First Optical Engine

[0106] 402b: Second Optical Engine

[0107] 402c: Third Optical Engine

[0108] 402d: Fourth Optical Engine

[0109] 404: Electronic Integrated Circuits

[0110] 404a: First Electronics Integrated Circuit

[0111] 404b: Second Electronic Integrated Circuit

[0112] 405: Mixed bond structure

[0113] 406: Electronic Components

[0114] 407a: First Solder Section

[0115] 407b: Second Solder Section

[0116] 408: Electronic interconnects

[0117] 408a: First Electronic Interconnector

[0118] 408b: Second Electronic Interconnector

[0119] 410: Packaging substrate

[0120] 410a: First packaging substrate

[0121] 410b: Second packaging substrate

[0122] 412: Integrated Optical Components

[0123] 414: Lens

[0124] 416a: First electrical interconnection structure

[0125] 416b: Second Electrical Interconnection Structure

[0126] 418a: First dielectric layer

[0127] 418b: Second dielectric layer

[0128] 502: Photonic interconnect chip

[0129] 502a: First Photonic Interconnect Chip

[0130] 502b: Second Photonic Interconnect Chip

[0131] 502c: Third Photonic Interconnect Chip

[0132] 502d, 502e, 502f, 502g, 502h: Photonic interconnect chips

[0133] 514a: First photon signal channel

[0134] 514b: Second photon signal channel

[0135] 520: Substrate

[0136] 522: Covered portion

[0137] 522L: Coating material layer

[0138] 524: Core Part

[0139] 524L: Core material layer

[0140] 526a: Part 1

[0141] 526b: Part Two

[0142] 702: Optical adhesive

[0143] 702a: First optical adhesive layer

[0144] 702b: Second optical adhesive layer

[0145] 802: Fiber optic array unit

[0146] 804: Outer casing

[0147] 806: Curved reflector surface

[0148] 808: Fiber Coupling Section

[0149] 810: Fiber optic cable

[0150] 812: Trench

[0151] 813a: Internal surface

[0152] 815: Plane

[0153] 817: Surface

[0154] 819: Fixed diameter

[0155] 821a: Incident photon signal

[0156] 821b: Reflected photon signal

[0157] 823: Angle

[0158] 902: Active Interconnector

[0159] 904: Stacked Structure

[0160] 1102a: First component package

[0161] 1102b: Second component package

[0162] 1104: Omitted

[0163] 1400a, 1400b, 1400c, 1400d, 1400e, 1500a, 1500b, 1500c, 1600a, 1600b, 1600c, 1800, 1900a, 1900b, 1900c: Intermediate structure

[0164] 1402: Patterned photoresist layer

[0165] 1602a: First inclined groove

[0166] 1602b: Second inclined groove

[0167] 1604a: First dielectric window

[0168] 1604b: Second dielectric window

[0169] 1604L: Dielectric material layer

[0170] 1606: Surface

[0171] 1608a: First surface

[0172] 1608b: Second surface

[0173] 1608c: Third Surface

[0174] 1610: Reflective coating

[0175] 1612: Dielectric Stack

[0176] 1616: Transition Edge Coupler

[0177] 1702: Conical end

[0178] 1704: Enclosed Dielectric Material

[0179] 1904: Laser Radiation

[0180] 1906: Specific Depth

[0181] 1908: Beam width

[0182] 2000: Method

[0183] 2002, 2004, 2006, 2008: Operations

[0184] B-B': Section

[0185] H1, H2: Depth

[0186] θ1: First angle

[0187] θ2: Second angle Detailed Implementation

[0188] The following disclosure provides many different embodiments or examples to implement different features of this invention. The following disclosure describes specific examples of the various components and their arrangements for simplification. Of course, these specific examples are not intended to be limiting. For example, if the present invention describes a first feature formed on or above a second feature, it indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the same reference numerals and / or designations may be repeated in the different examples disclosed below. These repetitions are for simplification and clarity and are not intended to limit any specific relationship between the different embodiments and / or structures discussed.

[0189] Furthermore, spatially related terms, such as "below," "below," "lower," "above," "higher," and similar terms, are used to facilitate the description of the relationship between one element or feature and another(s) in the illustration. In addition to the orientations shown in the figures, these spatially related terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same way. Unless otherwise expressly stated, each element with the same element symbol is assumed to have the same material composition and thickness within the same range.

[0190] Various embodiments of this invention provide photonic interconnect chips that allow photonic signals to propagate between a first photonic component and a second photonic component within an electronic / photonic package. Integrating optical / photonic signal functionality into an electronic / photonic package can provide reduced signal delay and ohmic loss. In this regard, in certain embodiments, it may be advantageous to transmit signals as photonic signals along a portion of a signal channel to avoid long electrical signal paths and their associated delays and ohmic losses. This can be achieved by converting an electrical signal to a photonic signal at a first point along the signal channel, propagating the photonic signal a certain distance, and then converting the photonic signal back to an electrical signal at a second point along the signal channel. In further embodiments, the functionality of converting electrical signals to photonic signals and vice versa may be advantageous in photonic (quantum or classical) computing operations. Using photonic interconnect chips allows various electronic and photonic components to be fabricated as separate chips. These chips can then be assembled into an electronic / photonic package, and photonic components can be coupled through the photonic interconnect chip.

[0191] One embodiment of a photonic interconnect chip may include a substrate, a dielectric waveguide, a first photonic coupler, and a second photonic coupler. The dielectric waveguide includes a core portion and a cladding portion and is formed on the substrate. The first photonic coupler is formed at a first end of the dielectric waveguide, and the second photonic coupler is formed at a second end of the dielectric waveguide. The dielectric waveguide may include a planar geometry within the cladding portion, such that the surface of the dielectric waveguide is parallel to the first surface of the photonic interconnect chip. The first and second photonic couplers may each be configured to couple photonic signals into and out of the photonic interconnect chip, such that a photonic signal channel connects the first photonic coupler, the dielectric waveguide, and the second photonic coupler. The photonic interconnect chip may further couple photonic signals into and out of a first dielectric window and a second dielectric window.

[0192] According to a further embodiment, an electronic / photonic package is provided. The electronic / photonic package may include a first photonic component, a second photonic component, and a photonic interconnect chip. The first photonic component includes a first photonic signal channel, the second photonic component includes a second photonic signal channel, and the photonic interconnect chip includes a plurality of dielectric waveguides. The photonic interconnect chip is coupled to the first and second photonic components, such that the first photonic signal channel is optically coupled to the second photonic signal channel through the plurality of dielectric waveguides.

[0193] An embodiment of forming a photonic interconnect chip may include forming a waveguide cladding portion on a substrate; forming a waveguide core portion within the waveguide cladding portion; forming a first photonic coupler at a first end of the waveguide core portion; and forming a second photonic coupler at a second end of the waveguide core portion.

[0194] Figure 1 This is a schematic diagram of various components that can be used in a photonic computing system. System components may include a generating device, a routing device, and a detector. The generating device, also known as a photon source 102, may be a laser or a light-emitting diode (LED). The routing device may include multiple dielectric waveguides 104 configured to route photon signals. The detector includes one or more photon detectors 106 configured to detect photon signals and convert the received photon signals into output electrical signals. Additional components may include a modulation device, which includes one or more photon modulators 108 and a photon processing unit 110.

[0195] One or more photonic modulators 108 can receive input electrical signals and modulate input photonic signals to apply amplitude and / or phase modulation to the input photonic signals as a response to the input electrical signals. Thus, one or more photonic modulators 108 can be used to convert data provided in the form of electrical signals into data encoded in photonic signals. Similarly, one or more photonic detectors 106 can convert the processed photonic signals back into output electrical signals. A photonic processing unit 110 can be configured to perform (classical or quantum) logic operations on the modulated photonic signals. Various photonic components (102 to 110) can be integrated into a single chip to form a photonic integrated circuit (PIC), as described below. Figures 2 to 3D As described in detail.

[0196] Figure 2 This is a top view schematic diagram of the PIC 200 according to various embodiments. The PIC 200 may include a photon source 102, a first photonic coupler 112a, a dielectric waveguide 104, a beam splitter 114, a photonic modulator 108, a photonic multiplexer 116, a second photonic coupler 112b, and one or more photonic detectors 106. Other components (not shown) may include active or passive photonic amplifiers, photonic switches, (quantum or classical) logic gates, etc. Figure 2 The PIC 200 can be configured as a photonic transceiver that can generate multiple photonic signals along transmit path 202a and receive photonic signals along receive path 202b. In other embodiments (not shown), the PIC can be configured as a transmitter (i.e., receiver path 202b omitted) or a receiver (i.e., transmit path 202a omitted). Various other PIC devices (not shown) can provide various other types of functionality, such as allowing direct logical operations on photonic signals.

[0197] exist Figure 2 In the exemplary embodiment of PIC 200, transmit path 202a can be configured to receive input electrical signals from various input electrical connections (e.g., specific numbers of a plurality of circuit pads 118) and can generate output photonic signals that can be provided to one or more output channels, such as output fiber 204a. receive path 202b can receive various input photonic signals from one or more input channels (e.g., input fiber 204b) and can convert the received input photonic signals into corresponding output electrical signals that can be provided to various output electrical connections (e.g., specific numbers of a plurality of circuit pads 118).

[0198] According to various embodiments, the transmission path 202a can be configured as follows. Each photon source 102 may include a laser or LED that generates an unmodulated signal, such as a continuous wave (CW) light / radiation beam. The unmodulated signal generated by each photon source 102 can then be provided to its respective first photonic coupler 112a, which can provide the unmodulated signal to the dielectric waveguide 104 and the photonic modulator 108. As shown, a beam splitter 114 can also be used to increase the number of signals provided to the photonic modulator 108. Each photonic modulator 108 can then generate a modulated signal (from its respective received unmodulated signal) in response to a time-dependent (e.g., received from some circuit pads 118) input electrical signal. The modulated signal can then be fed into a multiplexer 116 via an additional dielectric waveguide 104. The multiplexer 116 can then generate a multiplexed output signal, which can be sent to its respective output channel, such as an output fiber 204a.

[0199] Various photon sources 102 can generate multiple unmodulated signals corresponding to multiple individual wavelengths. Multiplexer 116 can then combine the various modulated signals with different wavelengths into a smaller number of output photon channels that can carry the multiplexed signals. Other photonic system components (e.g., photonic processing component 110) can then receive the multiplexed photon signals and can use a demultiplexer (not shown) to separate (i.e., demultiplex) the various photon signals for further processing operations.

[0200] like Figure 2 As shown, the receiving path 202b may include one or more photon detectors 106. For simplicity, only a single photon detector 106 is shown. However, according to various embodiments, the PIC 200 may include multiple input optical fibers 204b that can receive multiple corresponding input photon signals. In some embodiments, the input optical signals may contain multiplexed data, which includes photon signals with multiple wavelengths. A demultiplexer (not shown) can then separate the various signals with their respective wavelengths. Each separated signal can then be provided to its respective photon detector 106, which can convert the received photon signal into a corresponding output electrical signal. The resulting output electrical signal can then be provided as an output to other circuit pads 118.

[0201] Some components of the PIC 200 may be passive components (e.g., beam splitter 114, dielectric waveguide 104, multiplexer 116, etc.) that do not generate or receive electrical signals. Other components of the PIC 200 may be active components (e.g., photon source 102, photon detector 106, photon modulator 108, etc.) that can receive or generate electrical signals. Therefore, the PIC 200 may include both electrical and optical circuitry. As described above, the PIC 200 may include multiple circuit pads 118 that can be electrically connected to various active components of the PIC 200. Thus, some circuit pads 118 may be configured to receive input electrical signals, while others may be configured to provide output electrical signals. Still other circuit pads 118 may be configured to receive power, which can be supplied to active components that require power (e.g., photon source 102).

[0202] According to various embodiments, the electronic and photonic circuitry of the PIC 200 can be formed using semiconductor fabrication techniques in both front-end-of-line (FEOL) and back-end-of-line (BEOL) operations. Therefore, the PIC 200 can be manufactured as a standalone photonic chip, which can be integrated into a photonic package structure, as will be described in more detail below. In this regard, various electro-optical circuitry components (e.g., photon source 102 and photon detector 106) can include semiconductor device components, which can be fabricated on a semiconductor substrate layer in the FEOL process and on various interconnect layers in the BEOL process. For example, in some embodiments, specific active components can include control circuitry comprising transistor structures (e.g., CMOS circuitry) formed in the FEOL process.

[0203] Various electrical interconnect structures and other transistor structures can be formed in the BEOL process. Active and passive components can be formed within or on top of various interconnect layers in the BEOL process. For example, electro-optic components (e.g., photon source 102, photon modulator 108, photon detector 106, etc.) can be formed in the BEOL process and may include, for example, thin-film transistors, which may contain, for example, oxide semiconductor materials. Passive components (such as dielectric waveguide 104) can be formed by depositing and patterning various dielectric structures. For example, dielectric waveguide 104 can be formed to include a core material having a higher refractive index than the surrounding cladding material, as will be described in more detail below.

[0204] Figure 3AThis is a vertical cross-sectional view of a PIC 200 formed on a silicon-on-insulator (SOI) substrate 302 according to various embodiments. The SOI substrate 302 may include a silicon substrate layer 302a, an oxide layer 304 formed above the silicon substrate layer 302a, and a silicon layer 302b formed above the oxide layer 304. As described above, semiconductor device manufacturing techniques (e.g., photolithography patterning and etching) can be performed on the silicon layer 302b to form photonic components (104, 106, 108) and photonic couplers (112a, 112b).

[0205] like Figure 3A As shown, the vertically oriented fiber 204V can be coupled to the PIC 200 in a nominally vertical direction, as described below. Figure 3C This will be described in more detail. Alternatively, the horizontally oriented fiber 204h can be coupled to the PIC 200, as described below. Figure 3D This will be described in more detail. The PIC 200 may also include various electrical circuit components (not shown), which can be formed together with photonic components (104, 106, 108) and photonic couplers (112a, 112b) using semiconductor device manufacturing techniques. (Refer to the above...) Figure 2 The electrical circuit components can provide power to the active photonic components and allow input electrical signals to be provided to the PIC 200, and enable output electrical signals from the PIC 200 to be received by other components.

[0206] Figure 3B It is shown according to various embodiments Figure 3A A vertical cross-sectional view of a portion 300b of the PIC 200, showing the photonic components (104, 106, 108). Figure 3C It is shown according to various embodiments Figure 3A A vertical cross-sectional view of a further portion 300c of the PIC 200, showing the first photonic coupler 112a, while Figure 3D It is shown according to various embodiments Figure 3A A further section 300d of the photonic integrated circuit is shown in a vertical cross-sectional view, revealing the second photonic coupler 112b. (See diagram below.) Figure 3B As shown, the photonic components (104, 106, 108) may include a dielectric waveguide 104, a photonic detector 106, a photonic modulator 108, etc. Other photonic components (not shown) may include a photonic source 102, a splitter 114, a multiplexer 116, etc.

[0207] Photonic signals can be coupled into and out of the PIC 200 through various photonic couplers (112a, 112b). For example... Figure 3CAs shown, the first photonic coupler 112a can be a grating coupler 306a, which allows coupling between the PIC 200 and the vertically oriented optical fiber 204v. Furthermore, as... Figure 3D As shown, the second photonic coupler 112b can be configured as an edge coupler 306b, which allows coupling between the PIC 200 and the horizontally oriented optical fiber 204h. The first photonic coupler 112a can be formed by etching a periodic array of shallow trenches 308 in the dielectric waveguide 104. Each shallow trench in the periodic array can act as a scatterer of electromagnetic radiation (i.e., light / photons). Therefore, the first photonic coupler 112a can be configured as a diffraction grating. Such a diffraction grating can be configured to constructively interfere the scattering contributions from the various trenches in a predetermined direction (e.g., 8–10 degrees upward relative to the top surface of the PIC 200). In this way, the photonic signal 310 (i.e., electromagnetic wave) can be... Figure 3C As shown, a photonic signal (not shown) is coupled from the first photonic coupler 112a to the vertically oriented fiber 204v. Similarly, a photonic signal can also be coupled into the PIC 200 from the vertically oriented fiber 204v via the first photonic coupler 112a.

[0208] like Figure 3D As shown, the second photonic coupler 112b can be configured as an edge coupler 306b. In this respect, the photonic signal 310 (i.e., light / photon) can be coupled out of the surface of the dielectric waveguide 104 (also referred to as "butt-coupling") and into the horizontally oriented optical fiber 204h. However, according to various embodiments, a disparity in optical mode size may exist between the dielectric waveguide 104 and the horizontally oriented optical fiber 204h. In this respect, the optical mode size refers to the spatial extent of the electromagnetic field in a direction perpendicular to the longitudinal axis (e.g., along the x-axis) of the dielectric waveguide 104 (e.g., along the z-axis). For example, the optical mode size of the silicon dielectric waveguide 104 may be between 3 and 4 micrometers, while the mode size of the optical fiber may be between 8 and 10 micrometers.

[0209] To accommodate the mode size difference between the dielectric waveguide 104 and the horizontally oriented optical fiber 204h, the second photonic coupler 112b may include a spot-size converter (SSC). The SSC (not shown) may have a shape along the propagation direction (e.g., along...). Figure 3DThe lateral profile (x-axis) gradually changes size. By slowly changing (e.g., increasing) the lateral dimensions of the SSC, light propagating within the SSC can be confined to a basic optical mode, where the spot size gradually increases to match the size of the core (not shown) of the horizontally oriented fiber 204h. To reduce optical insertion loss, an undercut structure 312 can be provided to prevent extended optical modes propagating within the SSC from overlapping with the silicon substrate layer 302a beneath the SSC.

[0210] like Figure 3D As shown, the undercut structure 312 can be a silicon-free region located beneath the second photonic coupler 112b and can be formed by performing a two-step etching process. In the first operation, an opening (not shown) can be etched into the SOI substrate 302. The opening can then provide a channel for etchant chemicals in a wet etching process to reach the silicon surface at the interface between the silicon substrate layer 302a and the oxide layer 304 in the second etching process. In this respect, the silicon can be isotropically etched through the opening. A dielectric material can then be formed in the undercut structure 312 to provide structural stability. The refractive index of the selected dielectric material can be sufficiently different from that of silicon so that light modes do not propagate within the undercut region 312.

[0211] Figure 4 This is a vertical cross-sectional view illustrating an electronic / photonic package 400 including an optical engine 402 and electronic components 406, according to various embodiments. The optical engine 402 can be configured to convert electrical signals into photonic signals 310 and vice versa. The electronic component 406 can be an active EIC, such as a CPU chip, GPU chip, application-specific integrated circuit (ASIC), memory chip, etc. Alternatively, the electronic component 406 can be a passive component, such as a capacitor, inductor, resistor, diode, transformer, integrated passive chip, etc.

[0212] Optical engine 402 and electronic component 406 can each be attached to and electrically coupled to electronic interconnect 408. Optical engine 402 and electronic component 406 can further receive and transmit electrical signals to electronic interconnect 408. In this respect, optical engine 402 and electronic component 406 can communicate with each other via the electrical connection provided by electronic interconnect 408. Optical engine 402 and electronic component 406 can be attached to electronic interconnect 408 via a plurality of first solder portions 407a. Conversely, electronic interconnect 408 can be attached to and electrically coupled to package substrate 410 via a plurality of second solder portions 407b. Package substrate 410 allows electronic / photonic package 400 to be connected to other system components (such as printed circuit boards (PCBs)) (not shown).

[0213] Optical engine 402 can be used to reduce signal delay and ohmic loss by providing optical / photonic signal functionality. Therefore, in certain embodiments, it may be advantageous to transmit the signal as a photonic signal along a portion of the signal channel to avoid long electrical signal paths and their associated delays and ohmic losses. This can be achieved by converting the electrical signal into a photonic signal at a first point along the signal channel, propagating the photonic signal a specific distance, and then converting the photonic signal back into an electrical signal at a second point along the signal channel. In further embodiments, the functionality of converting electrical signals to photonic signals and vice versa may be advantageous in photonic (quantum or classical) computing operations, as described below. Figure 9A and Figure 9B A more detailed description will follow.

[0214] The optical engine 402 can be configured as a co-packaged electronic / photonic chip. In this regard, the electronic integrated circuit (EIC) 404 can be bonded to the PIC 200 via a hybrid bonding structure 405. (See above for reference.) Figures 2 to 3D The PIC 200 may include electrical and optical / photonic circuitry that can generate a photonic signal 310 based on a received electrical signal. The optical engine 402 may also receive and process the photonic signal 310 to generate an electrical signal, which may be provided as an output to the electronic interconnect 408.

[0215] EIC 404 can be configured to provide control signals to PIC 200. For example, EIC 404 can provide modulated electrical signals that can encode digital information. PIC 200 can then use various electro-optical components to generate a photonic signal 310 based on the modulated electrical signals received from EIC 404. For example, PIC 200 may include one or more photonic modulators 108 and one or more dielectric waveguides 104. PIC 200 may also include one or more photonic couplers 112 that can transmit the photonic signal 310 between PIC 200 and the integrated optical portion 412 of optical engine 402. The integrated optical portion 412 may include various optical components, such as lenses 414, reflectors (not shown), diffraction gratings (also not shown), etc. The integrated optical portion 412 may also include various coupling structures (e.g., fiber array units (not shown)) that can couple the integrated optical portion 412 to one or more fiber optics. For example, such as Figure 4 As shown, the integrated optical component 412 can be mechanically and optically coupled to a nominally vertically oriented optical fiber 204v.

[0216] like Figure 4As shown, the electronic interconnect 408 may include multiple electrical interconnect structures (416a, 416b) formed within one or more dielectric layers (418a, 418b). In various embodiments, the electronic interconnect 408 may be a semiconductor interconnect, a glass interconnect, or an organic interconnect. In this regard, the first dielectric layer 418a may be a glass layer, a semiconductor layer (e.g., a silicon layer), or a polymer material layer, while the second dielectric layer 418b may be another polymer material. For example, the first dielectric layer 418a may be a silicon substrate, while the second dielectric layer may be a polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzo-bisoxazole (PBO). In such an embodiment, the first electrical interconnect structure 416a may be formed within the first dielectric layer 418a by performing semiconductor device fabrication processes. For example, the process operation may include patterning and etching the first dielectric layer 418a, followed by depositing a conductive material (e.g., aluminum (Al), copper (Cu), etc.) to form the first electrical interconnect structure 416a.

[0217] According to some embodiments, a second electrical interconnect structure 416b may be formed within a second dielectric layer 418b as a redistributed interconnect structure. In this regard, the second dielectric layer 418b may be formed as layers of sequentially deposited polymer materials such as PI, BCB, and PBO. Each of these sequentially deposited layers may then be patterned, and conductive materials (e.g., titanium (Ti), copper (Cu), nickel (Ni), and aluminum (Al)) may be sequentially deposited (e.g., by electroplating) to form the second electrical interconnect structure 416b within the second dielectric layer 418b. In some embodiments, the second electrical interconnect structure 416b may have a fan-out configuration (not shown).

[0218] Figure 5A This is a top view illustrating a further electronic / photonic package 500 including a photonic interconnect chip 502, according to various embodiments. Figure 5B Various embodiments are shown Figure 5A A vertical cross-sectional view of the 500-electron / photonic package. Definition Figure 5B The vertical plane of the cross-sectional view is composed of Figure 5AThe cross-section B-B' in the diagram indicates this. The electronic / photonic package 500 may include a plurality of first EICs 404a and a plurality of second EICs 404b. Each of the plurality of first EICs 404a provides a first function, while each of the plurality of second EICs 404b provides a second function. For example, the plurality of first EICs 404a may be a CPU chip, a GPU chip, an application-specific integrated circuit (ASIC), etc., which provides the function of performing computational logic operations. In various embodiments, the plurality of second EICs 404b may be memory (e.g., high-bandwidth memory (HBM)) chips, which provide data storage functionality.

[0219] Each of the plurality of first EICs 404a and the plurality of second EICs 404b may be attached to and electrically coupled to the electronic interconnect 408. Conversely, the electronic interconnect 408 may be attached to and electrically coupled to the package substrate 410. The electronic interconnect 408 may provide electrical connections between the plurality of first EICs 404a and the plurality of second EICs 404b. Thus, the electronic interconnect 408 may provide power to various components of the electronic / photonic package 500 and further provide electrical signal paths between the components of the electronic / photonic package 500. The package substrate 410 may allow the electronic / photonic package 500 to be connected to other system components, such as printed circuit boards (PCBs) (not shown).

[0220] To reduce signal delay and ohmic loss, the electronic / photonic package 500 may further include photonic components that can provide optical / photonic signal functionality. For example, the electronic / photonic package 500 may include a first optical engine 402a and a second optical engine 402b. Each of the first optical engine 402a and the second optical engine 402b can be configured to convert an electrical signal into a photonic signal and vice versa, as described above. Figure 4 More detailed description.

[0221] like Figure 5B As shown, in addition to multiple first EICs 404a and multiple second EICs 404b, first optical engines 402a and second optical engines 402b can also be attached to and electrically coupled to electronic interconnects 408. In this respect, each of the first optical engines 402a and second optical engines 402b can be attached to the electronic interconnect 408 via multiple first solder portions 407a. Conversely, the electronic interconnect 408 can be attached to and electrically coupled to the package substrate 410 via multiple second solder portions 407b. Therefore, each of the first optical engines 402a and second optical engines 402b can receive power from the electrical connection provided by the electronic interconnect 408.

[0222] Each of the first optical engine 402a and the second optical engine 402b can further receive electrical signals from and transmit electrical signals to the electronic interconnect 408. In this respect, the first optical engine 402a and the second optical engine 402b can communicate with each other and with other components of the electronic / photonic package 500 via electrical connections provided by the electronic interconnect 408. For example, one or more of the plurality of first EICs 404a can provide electrical control signals to the first optical engine 402a and the second optical engine 402b.

[0223] The specific electrical signal received by the first optical engine 402a can be converted into a first photonic signal 310a, which can be provided to the first photonic signal channel 514a within the first optical engine 402a. The first photonic signal 310a can propagate within the first photonic signal channel 514a and can be coupled into the second photonic signal channel 514b within the second optical engine 402b through the photonic interconnect chip 502.

[0224] In this regard, the photonic interconnect chip 502 may include a dielectric waveguide 104, which can be optically coupled to a first photonic coupler 112a formed at a first end of the dielectric waveguide 104 and a second photonic coupler 112b formed at a second end of the dielectric waveguide 104. Each of the first photonic coupler 112a and the second photonic coupler 112b can couple photonic signals in and out of the photonic interconnect chip 502, such that a photonic signal channel connects the first photonic coupler 112a, the dielectric waveguide 104, and the second photonic coupler 112b. Figure 5B As shown, the photonic interconnect chip 502 may include a substrate 520 and a covering portion 522 formed on the substrate 520. The dielectric waveguide 104 may further include a core portion 524 formed within the covering portion 522.

[0225] Each of the cladding portion 522 and the core portion 524 may be made of a dielectric material such that a first refractive index of the core portion 524 is greater than a second refractive index of the cladding portion 522. For example, in some embodiments, the substrate 520 may be a semiconductor (e.g., silicon), the cladding portion 522 may be silicon dioxide, and the core portion may be made of silicon. Such a structure can be formed by patterning a silicon-on-insulator structure, as referenced above. Figures 3A to 3D As described above. In other embodiments, both the covering portion 522 and the core portion 524 may be made of polymer materials, as referred to below. Figures 14A to 15C This will be described in more detail. In another example, the core portion 524 can be formed by laser-writing an operation on a photosensitive polymer material, as described below. Figures 19A to 19DThis will be described in more detail. In this respect, the microstructure of the polymer material can be locally altered during the absorption of laser radiation (e.g., the refractive index can be increased). The irradiated local region can then serve as the core portion 524, while the surrounding unirradiated portion can serve as the covering portion 522.

[0226] like Figure 5B As shown, each of the first photonic coupler 112a and the second photonic coupler 112b can be configured as an angled reflector 306c, which converts a vertically propagating photonic signal into a horizontally propagating signal, and vice versa. Therefore, a first photonic signal 310a propagating vertically along the first photonic signal channel 514a can enter the photonic interconnect chip 502 from the first optical engine 402a. Once received from the first optical engine 402a via the photonic interconnect chip 502, the first photonic signal 310a can be converted by the first photonic coupler 112a into a photonic signal 310c propagating horizontally within the core portion 524 of the dielectric waveguide 104. Conversely, the horizontally propagating photonic signal 310c can be received from the dielectric waveguide 104 and converted by the second photonic coupler 112b into a second vertically propagating photonic signal 310b that can be provided to the second optical engine 402b. The received second vertically propagating photonic signal 310b can then propagate vertically along the second photonic signal channel 514b within the second optical engine 402b. Various other types of photonic couplers may be provided in other embodiments. For example, grating coupler 306a (see, for example, see...) Figure 3C and Figure 18C ) and edge coupler 306b (e.g., see Figure 3D and Figure 12 This may be provided in other embodiments, as will be described in more detail below.

[0227] like Figure 5B As further shown, each of the first optical engine 402a and the second optical engine 402b can be formed as a separate chip and can be attached to and electrically coupled to the electronic interconnect 408. The photonic interconnect chip 502 can also be formed as a separate chip, for example, and can be attached to the first optical engine 402a and the second optical engine 402b, such as... Figure 5B As shown. In this respect, the first portion 526a of the photonic interconnect chip 502 may be mechanically and optically coupled to the first optical engine 402a, while the second portion 526b of the photonic interconnect chip 502 may be mechanically and optically coupled to the second optical engine 402b. See below for reference. Figure 7 In more detail, the photonic interconnect chip 502 can be coupled to the first optical engine 402a and the second optical engine 402b using optical adhesives (702a, 702b), and the optical adhesives can be transparent to photonic signals.

[0228] like Figure 5A and Figure 5B As shown, the photonic interconnect chip 502 can be configured as an intra-package photonic coupler. In this respect, the photonic interconnect chip 502 can couple photonic components (402a, 402b) formed on a single electronic interconnect 408 within the package 500. In other embodiments, the photonic interconnect chip 502 can couple components formed on two or more different interconnects, as described below. Figure 8A and Figure 8B More detailed description. Therefore, in a further embodiment, the photonic interconnect chip 502 may be configured as an inter-package photonic coupler.

[0229] Figure 6A This is a top view of a photonic interconnect chip 502 illustrating optically connecting a first photonic component (200a, 402a) and a second photonic component (200b, 402b) according to various embodiments. In this respect, the first photonic component may be one of a first photonic integrated circuit (PIC) 200a or a first optical engine 402a, while the second photonic component may be one of a second PIC 200b or a second optical engine 402b. An exemplary embodiment of the photonic interconnect chip 502 coupling the first optical engine 402a and the second optical engine 402b is, for example, as described above. Figure 5A and Figure 5B More detailed description. In a further embodiment, the first optical engine 402a may be coupled to the PIC 200, as described below. Figure 9A , Figure 9B See Figure 10 for a more detailed description.

[0230] like Figure 6A As shown, the photonic interconnect chip 502 may include a plurality of dielectric waveguides 104. Each dielectric waveguide may include a core portion 524 formed within a surrounding cladding portion 522. Each dielectric waveguide 104 may be optically coupled to a first photonic coupler 112a and a second photonic coupler 112b. In this exemplary embodiment, each dielectric waveguide 104 may share a common first photonic coupler 112a and a common second photonic coupler 112b. Each of the common first photonic coupler 112a and the common second photonic coupler 112b may be formed as a beveled reflector 306c (e.g., see...). Figure 5B Other embodiments may include other types of photonic couplers (306a, 306b), which will be described in more detail below.

[0231] In contrast to the common first photonic coupler 112a and common second photonic coupler 112b, in other embodiments, each core portion 524 may be coupled to a respective independent first photonic coupler 112a (not shown) and a respective independent second photonic coupler 112b (not shown). For example, each core portion 524 may be coupled to a respective angled reflector 306c, which may be spatially separated from each other. Alternatively, each core portion 524 may be coupled to a respective grating coupler 306a. The formation of the angled reflector 306c will be referred to below. Figures 16A to 16H A more detailed description is provided below, and the formation of the grating coupler 306a will be referred to in the following text. Figures 18A to 18C More detailed description. See above for reference. Figure 5B It is mentioned that the photonic interconnect chip 502 may include a substrate 520 (for illustration purposes). Figure 6A (in the middle), the covering portion 522 can be formed thereon, as shown below. Figures 14A to 15C More detailed description. Although Figure 6A The photonic interconnect chip 502 can couple two photonic components, and other embodiments can couple three, four, or more photonic components, as described below. Figure 6B More detailed description.

[0232] Figure 6B This is a top view of a photonic interconnect chip 502 illustrating optical connections between first photonic components (200a, 402a), second photonic components (200b, 402b), third photonic components (200c, 402b), and fourth photonic components (200d, 402d) according to various embodiments. In this regard, various combinations of PICs (200a, 200b, 200c, 200d) and optical engines (402a, 402b, 402c, 402d) can be optically coupled. As shown, the photonic interconnect chip 502 may include a first set of dielectric waveguides 104a, a second set of dielectric waveguides 104b, a third set of dielectric waveguides 104c, a fourth set of dielectric waveguides 104d, and a fifth set of dielectric waveguides 104e.

[0233] exist Figure 6BIn an exemplary embodiment, the first set of dielectric waveguides 104a can optically couple the first photonic component (200a, 402a) to the second photonic component (200b, 402b); the second set of dielectric waveguides 104b can optically couple the third photonic component (200c, 402c) to the fourth photonic component (200d, 402d); the third set of dielectric waveguides 104c can optically couple the first photonic component (200a, 402a) to the third photonic component (200c, 402c); the fourth set of dielectric waveguides 104d can optically couple the second photonic component (200b, 402b) to the fourth photonic component (200d, 402d); and the fifth set of dielectric waveguides 104e can optically couple the first photonic component (200a, 402a) to the fourth photonic component (200d, 402d).

[0234] Each set of dielectric waveguides (104a, 104b, 104c, 104d, 104e) may include multiple core portions 524 formed within a surrounding cladding portion 522. Each set of dielectric waveguides (104a, 104b, 104c, 104d, 104e) may also be optically coupled to respective first photonic couplers 112a and second photonic couplers 112b. The photonic couplers (112a, 112b) may, in different embodiments, include a grating coupler 306a, an edge coupler 306b, and an angled reflector 306c (see, for example, see...). Figure 3C , Figure 3D and Figure 5B ).like Figure 6B As shown, multiple sets of dielectric waveguides (104a, 104b, 104c, 104d, 104e) can be configured in various ways, including straight dielectric waveguides (104a, 104b, 104c, 104d) and curved dielectric waveguide 104e. Although Figure 6B The photonic interconnect chip 502 can couple four photonic components, and in other embodiments, it can couple three, five, six, or more photonic components.

[0235] Figure 7This is a vertical cross-sectional view illustrating a further electronic / photonic package 700 including a photonic interconnect chip 502 according to various embodiments. As shown, the electronic / photonic package 700 may include a first optical component (e.g., a first optical engine 402a) and a second optical component (e.g., a second optical engine 402b). As shown, a first portion 526a of the photonic interconnect chip 502 may be mechanically and optically coupled to the first optical engine 402a, while a second portion 526b of the photonic interconnect chip 502 may be mechanically and optically coupled to the second optical engine 402b. In this regard, a first optical adhesive layer 702a may connect the first portion 526a of the photonic interconnect chip 502 to a first integrated optical portion 412a of the first optical engine 402a, while a second optical adhesive layer 702b may connect the second portion 526b of the photonic interconnect chip 502 to a second integrated optical portion 412b of the second optical engine 402b.

[0236] As shown in the figure, the first optical adhesive layer 702a and the second optical adhesive layer 702b may have different thicknesses to accommodate different sizes and placement / alignment errors of the optical components (402a, 402b), which will be connected by the photonic interconnect chip 502. In this respect, the first optical adhesive layer 702a may be thicker than the second optical adhesive layer 702b. For example, the first optical engine 402a may have a smaller thickness than the second optical engine 402b. Alternatively, the first optical engine 402a and the second optical engine 402b may have a common thickness, but may have a positioning tolerance that allows for a specific height difference due to variations in the thickness of the first solder portion 407a, which is used to bond the optical components (402a, 402b) to the electronic interconnect 408.

[0237] The optical adhesive layers (702a, 702b) may be transparent and provide a strong mechanical connection between the photonic interconnect chip 502 and the optical components (402a, 402b). According to one embodiment, the optical adhesive layers (702a, 702b) may comprise an adhesive similar to materials used to secure optical fibers in connectors, splices, and other components in an optical fiber system. Therefore, the optical adhesive layers (702a, 702b) may comprise materials with optical clarity, low shrinkage, and good adhesion properties to ensure effective light transmission between the photonic interconnect chip 502 and the optical components (402a, 402b).

[0238] In some embodiments, the optical adhesive layers (702a, 702b) may comprise an optical epoxy resin, which may be a two-component adhesive comprising a resin and a hardener. When mixed in the correct proportions and applied between the optical components (402a, 402b) and the photonic interconnect chip 502, the optical adhesive layers (702a, 702b) undergo a chemical reaction to cure and form a solid, transparent bond. The cured optical adhesive layers (702a, 702b) thus form a mechanical connection that maintains the alignment and stability of the optical components (402a, 402b) and the photonic interconnect chip 502, minimizes signal loss, and ensures reliable data transmission between the photonic interconnect chip 502 and the optical components (402a, 402b).

[0239] The chemical composition of optical adhesives or optical epoxy resins can vary based on the specific needs and desired properties of different applications. According to specific embodiments, optical epoxy resins may comprise epoxy resin, curing agents or hardeners, fillers, plasticizers, adhesion promoters, UV stabilizers, and optically clearing agents. Epoxy resins provide the primary structure and adhesive properties. These resins can be polymeric materials formed by the reaction of epoxy resin with curing agents or hardeners. Examples of epoxy resins include bisphenol A (DGEBA) and bisphenol F. The curing agent or hardener component initiates the polymerization reaction with the epoxy resin, resulting in the curing or hardening of the adhesive. Amines can be used as curing agents in optical epoxy resins.

[0240] Fillers may be added to improve the mechanical and thermal properties of the optical adhesive layers (702a, 702b). In some embodiments, fillers may also enhance the optical properties of the optical adhesive layers (702a, 702b). Examples of fillers may include silica or other fine particles, such as carbon / graphite particles. Plasticizers may be added to improve elasticity and reduce brittleness in the cured adhesive layers (702a, 702b). Adhesion promoters may contain compounds added to enhance bonding performance with specific materials, such as glass or metal surfaces. According to some embodiments, optical epoxy resins used in applications exposed to UV light may contain UV stabilizers to prevent degradation of the optical adhesive layers (702a, 702b) due to UV radiation. According to some embodiments, the optical adhesive layers (702a, 702b) may contain optically clearing agents to maintain or enhance optical clarity. These agents may be used to ensure that the cured optical adhesive layers (702a, 702b) have low optical absorption, thereby not introducing loss of transmitted photon signals.

[0241] Figure 8A This is a top view illustrating a further electronic / photonic package 800 including a first photonic interconnect chip 502a, a second photonic interconnect chip 502b, and a third photonic interconnect chip 502c, according to various embodiments. Figure 8B It is shown according to various embodiments Figure 8AA vertical cross-sectional view of an electronic / photonic package. Definition Figure 8B The vertical plane of the cross-sectional view is composed of Figure 8A The section B-B' is indicated in the text. For example... Figure 8A As shown, the electronic / photonic package 800 may include a plurality of first EICs 404a and a plurality of second EICs 404b. Each first EIC 404a provides a first function, while each second EIC 404b provides a second function. For example, the plurality of first EICs 404a may be CPU chips, GPU chips, application-specific integrated circuits (ASICs), etc., which provide functions for performing computational logic operations. In various embodiments, the plurality of second EICs 404b may be memory (e.g., high-bandwidth memory (HBM)) chips, which provide data storage functions.

[0242] The electronic / photonic package 800 may further include a first electronic interconnect 408a and a second electronic interconnect 408b. Some of the plurality of first EICs 404a and the plurality of second EICs 404b may be attached to and electrically coupled to the first electronic interconnect 408a, while others of the plurality of first EICs 404a and the plurality of second EICs 404b may be attached to and electrically coupled to the second electronic interconnect 408b. Conversely, each of the first electronic interconnect 408a and the second electronic interconnect 408b may be attached to and electrically coupled to a package substrate 410. The package substrate 410 allows the electronic / photonic package 800 to be connected to other system components, such as a printed circuit board (PCB) (not shown). The first electronic interconnects 408a and the second electronic interconnects 408b provide electrical connections for various components in the plurality of first EICs 404a and the plurality of second EICs 404b.

[0243] As described in the other embodiments above, the electronic / photonic package 800 may further include photonic components that can provide optical / photonic signal functionality. For example, the electronic / photonic package 800 may include a first optical engine 402a, a second optical engine 402b, a third optical engine 402c, and a fourth optical engine 402d. Each of the first optical engine 402a, the second optical engine 402b, the third optical engine 402c, and the fourth optical engine 402d may be configured to convert electrical signals into photonic signals and vice versa, as referred to above. Figure 4 , Figure 5A and Figure 5BMore detailed description. The first optical engine 402a and the second optical engine 402b may be attached to and electrically coupled to the first electronic interconnect 408a. Similarly, the third optical engine 402c and the fourth optical engine 402d may be attached to and electrically coupled to the second electronic interconnect 408b.

[0244] Each of the first optical engine 402a and the second optical engine 402b can receive and transmit electrical signals to the first electronic interconnect 408a, while each of the third optical engine 402c and the fourth optical engine 402d can receive and transmit electrical signals to the second electronic interconnect 408b. The first photonic interconnect chip 502a can optically couple the first optical engine 402a and the second optical engine 402b, and therefore can be configured as a photonic coupler within a package. Similarly, the third photonic interconnect chip 502c can also be configured as a photonic coupler within a package, optically coupling the third optical engine 402c and the fourth optical engine 402d. Conversely, the second photonic interconnect chip 502a, which can optically couple the second optical engine 402b and the third optical engine 402c, is configured as a photonic coupler between packages. In this respect, signals can be efficiently routed between the device attached to the first electronic interconnect 408a and the device attached to the second electronic interconnect 408b.

[0245] like Figure 8A and Figure 8B As shown, the electronic / photonic package 800 may further include a fiber array unit (FAU) 802. The FAU 802 can couple photonic signals into and out of the fourth optical engine 402b. Figure 8B As shown, FAU 802 may include a housing 804 having a curved reflector surface 806 and a fiber coupling portion 808. Fiber optic cable 810 may be mechanically and optically coupled to the fiber coupling portion 808. Therefore, the optical fiber 204 within the fiber optic cable 810 may be optically coupled to the housing 804, such that a photon signal 310 propagating perpendicularly within the fourth optical engine 402d may be reflected by the curved reflector surface 806 into the fiber coupling portion 808. The photon signal 310 received from the fourth optical engine 402d may then be transmitted into one or more optical fibers 204 within the fiber optic cable 810. Similarly, the photon signal 310 received from the fiber optic cable 810 may be reflected by the curved reflector surface 806 into the fourth optical engine 402d.

[0246] Figure 8C It is shown according to various embodiments Figure 8BA detailed three-dimensional perspective view of the FAU 802. As shown, the housing 804 may include a curved reflector surface 806. An optical fiber 204 may be placed in a fiber coupling portion 808 formed in individual trenches 812 within the housing 804. Optical adhesive 702 may be formed between the end of the optical fiber 204 and the coupling surface 814 of the housing 804. The housing 804 may be formed of a polymer material, which may be patterned and etched using semiconductor manufacturing techniques. For example, the curved reflector surface 806 may be formed, according to various embodiments, by patterning and etching the polymer material of the housing 804 using a multi-tone mask and a low-contrast photoresist.

[0247] The dashed area of ​​the fiber coupling portion 808 can also be formed by removing a portion of the polymer material forming the housing 804 using patterning and etching techniques. Similarly, the trench 812 for fixing the optical fiber can be created by performing an etching process. Figure 8B As shown, optical fiber 204 can be provided in optical fiber cable 810 (in Figure 8C (omitted for clarity). Once the fiber 204 is secured within the groove of the housing 804, additional polymer material (not shown) can be formed over the fiber 204 within the volume indicated by the dashed area of ​​the fiber coupling portion 808. Using a single angled reflector surface 806 for multiple fibers 204 allows multiple fibers 204 to be closely spaced without requiring strict alignment tolerances, which would otherwise require strict alignment tolerances if each fiber 204 were to be aligned with its own individual reflector criterion.

[0248] like Figure 8CAs further shown, the trench 812 can be formed to have internal surfaces (813a, 313b) that can form an angle with respect to a plane 815 parallel to the surface 817 of the housing 804. In this respect, the first surface 813a can form a first angle θ1 with respect to the plane 815. The second surface 813b can have a similar angle (not shown) with respect to the plane 815. An optical fiber 204 of fixed diameter 819 can be disposed in the trench 812 with respect to the surface 817 of the housing 804 to a depth H1, such that the depth H1 is a geometric function of the first angle θ1. Alternatively, in another embodiment, the trench can be wider and thus can be characterized by a second angle θ2 (where θ2 > θ1) measured with respect to the plane 815. In this example, the wider trench can accommodate the optical fiber 204 of fixed diameter 819 to a depth H2, which is greater than the depth H1 of the first trench. The depth H2 is given by the same geometric function of the second angle θ2, just as the first depth H1 is determined as a function of the first angle θ1. The first depth H1 and the second depth H2 measure the vertical position of the optical fiber 812 relative to the surface 817. Therefore, by forming the groove 812 with inner surfaces (813a, 813b) that are at predetermined angles relative to the horizontal plane 815, the vertical position of the optical fiber 204 can be designed to have a predetermined depth.

[0249] Similarly, such as Figure 8C As further shown, the curvature of the curved reflector surface 806 can be selected to provide a predetermined reflectivity for the photon signal provided by the optical fiber 204. In this respect, the incident photon signal 821a can strike the curved reflector 806 and be reflected, thereby generating a reflected photon signal 821b. As shown, the reflected photon signal 821b can propagate away from the curved reflector surface 806 relative to the incident photon signal 821a at an angle 823. The reflection angle 823 can depend on the angle of incidence (not explicitly shown) between the incident photon signal 821a and the curved reflector surface 806. The reflection angle 823 can further depend on the curvature (i.e., radius of curvature) of the curved reflector surface 806. Therefore, by selecting a specific predetermined value for the curvature of the curved reflector surface 806 (i.e., local radius of curvature), predetermined reflection characteristics (e.g., reflection angle 823) can be determined. Therefore, the coupling between optical fiber 204 and FAU 802 can be determined by the curvature of the curved reflector surface 806 and by adjusting the vertical position of optical fiber 204 as described above.

[0250] In some embodiments, the curved reflector surface 806 may have a single curvature (e.g., denoted as "curvature 1") or may have a variable curvature. A single curvature refers to a single value characterizing the radius of curvature across the entire surface. In other embodiments, the surface may have a curvature (i.e., a radius of curvature) that varies along the surface. In one example, the surface may, according to a further embodiment, have a first portion and a second portion, the first portion having a first radius of curvature (e.g., denoted as "curvature 1") and the second portion having a second radius of curvature (e.g., denoted as "curvature 2"). In a further embodiment, the curved reflector surface 806 may have a continuously varying radius of curvature (not shown) as a function of position on the curved reflector surface 806. In other embodiments, the radius of curvature may be a piecewise-smooth function (not shown) of position on the curved reflector surface 806 (i.e., may contain N segments, each corresponding to N different corresponding curvatures, where N is an integer).

[0251] Figure 9A This is a top view illustrating a further electronic / photonic package 900 comprising a plurality of photonic interconnect chips (502a, 502b, 502c, 502d, 502e, 502f, 502g, 502h) according to various embodiments. The electronic / photonic package 900 may include a plurality of first EICs 404a and a plurality of second EICs 404b. Each first EIC 404a provides a first function (e.g., logic operation), while each second EIC 404b provides a second function (e.g., data storage operation).

[0252] Each of the plurality of first EICs 404a and the plurality of second EICs 404b may be attached to and electrically coupled to the electronic interconnect 408. Conversely, the electronic interconnect 408 may be attached to and electrically coupled to the package substrate 410. The electronic interconnect 408 may provide electrical connections between the plurality of first EICs 404a and the plurality of second EICs 404b. Thus, the electronic interconnect 408 may provide power to various components of the electronic / photonic package 900 and further provide electrical signal paths between the components of the electronic / photonic package 900. The package substrate 410 may allow the electronic / photonic package 900 to be connected to other system components, such as printed circuit boards (PCBs) (not shown).

[0253] like Figure 9AAs shown, some first EICs 404a may be attached to and electrically coupled to the active interconnect 902. The active interconnect may provide electrical connections between adjacent first EICs 404a and may further include active circuitry. For example, the active interconnect 902 may include transistors that provide additional logic processing operations and / or data storage functionality. Some second EICs 404b may be co-packaged with one or more first EICs 404a to form a stacked structure 904. In this respect, the stacked structure 904 may include second EICs 404b stacked on top of the first EICs 404a. For example, the second EICs 404b may be bonded to the first EICs 404a in the stacked structure 904 using a hybrid bonding structure (not shown). In this respect, the first EICs 404a may provide control circuitry to the second EICs 404b, which may provide data storage functionality.

[0254] To reduce signal delay and ohmic loss, the electronic / photonic package 900 may further include photonic components that can provide optical / photonic signal functionality. For example, the electronic / photonic package 900 may include multiple PICs (200a, 200b, 200c, 200d, 200e, 200f, 200g). Therefore, the signal channels within the electronic / photonic package 900 may include electronic signal channels (e.g., see solid arrows) and photonic signal channels (e.g., see dashed arrows). Figure 9A As shown, electronic signal channels can exist between adjacent first EICs 404a, between first EICs 404a and second EICs 404b, between first EICs 404a and one or more PICs (200a, 200b, 200c, 200d, 200e, 200f, 200g), and between second EICs 404b and one or more PICs (200a, 200b, 200c, 200d, 200e, 200f, 200g).

[0255] In addition to reducing ohmic losses by providing a photonic signal path, one or more PICs (200a, 200b, 200c, 200d, 200e, 200f, 200g) can provide the ability to perform (classical or quantum) logic operations directly on the photonic signal. Therefore, various components (200a, 200b, 200c, 200d, 200e, 200f, 200g) within multiple PICs can provide their own functions and have their own structural configurations. For example, some PICs (200d, 200e, 200f, 200g) may be smaller than others (200a, 200b, 200c) and may have more limited functionality than others. For example, smaller PICs (200d, 200e, 200f, 200g) can be configured as photonic transceivers, as described above. Figure 2 As stated above.

[0256] Alternatively, larger PICs (200a, 200b, 200c) can be configured as monolithic electronic / photonic devices capable of performing various functions, including photonic signal generation and photonic signal processing. For example, monolithic PICs (200a, 200b, 200c) can receive electrical signals from adjacent EICs (404a, 404b) and photonic signals from adjacent PICs (200d, 200e, 200f, 200g), and can perform various processing operations on the received signals. The electronic / photonic package 900 may further include a FAU 802, which can be configured to transmit and receive photonic signals. As shown, the FAU 802 provides a photonic interface between a PIC (e.g., PIC 200b) and external photonic circuitry (not shown). The FAU 802 is consistent with the above references. Figure 8B and Figure 8C The FAU 802 is similar and can provide similar photonic signaling capabilities.

[0257] Figure 9B It is shown according to various embodiments Figure 9A A cross-sectional view of a portion of the electronic / photonic package 900. Definition Figure 9B The vertical plane of the cross-sectional view is composed of Figure 9A The section B-B' is indicated in the figure. Figure 9AA portion of the illustrated electronic / photonic package 900 includes a first photonic interconnect chip 502a and a second photonic interconnect chip 502b. The first photonic interconnect chip 502a optically connects a first PIC 200a to a second PIC 200d. Similarly, the second photonic interconnect chip 502b optically connects a second PIC 200d to a third PIC 200c. As described above, the various PICs (200a, 200c, 200d) can have their own configurations and provide their own functions. For example, the second PIC 200c can have relatively limited functions, such as being configured as a photonic transceiver, as referenced above. Figure 2 The first PIC 200a and the third PIC 200c can be formed as a single-unit structure, which can provide more complex functions, such as computation and logic operations on photonic data.

[0258] Figure 10A This is a top view illustrating a further electronic / photonic package 1000 comprising multiple photonic interconnect chips (502a, 502b, 502c, 502d, 502e, 502f, 502g, 502h) according to various embodiments. Figure 10B It is shown according to various embodiments Figure 10A A cross-sectional view of a portion of the electronic / photonic package 1000. Definition Figure 10B The vertical plane of the cross-sectional view is composed of Figure 10A The cross-section B-B' is indicated in the diagram. The electronic / photonic package 1000 is compatible with... Figure 9A and Figure 9B The electronic / photonic package 900 is similar. In this respect, the electronic / photonic package 1000 may include a plurality of first EICs 404a and a plurality of second EICs 404b. Each first EIC 404a provides a first function (e.g., logic operation), and each second EIC 404b provides a second function (e.g., data storage operation).

[0259] Each of a plurality of first EICs 404a and a plurality of second EICs 404b may be attached to and electrically coupled to electronic interconnect 408. Conversely, electronic interconnect 408 may be attached to and electrically coupled to package substrate 410. Electronic interconnect 408 may provide electrical connections between the plurality of first EICs 404a and the plurality of second EICs 404b. Thus, electronic interconnect 408 may provide power to the various components of electronic / photonic package 1000 and may further provide electrical signal paths between the components of electronic / photonic package 1000. Package substrate 410 may allow electronic / photonic package 1000 to be connected to other system components, such as printed circuit boards (PCBs) (not shown).

[0260] and Figure 9A and Figure 9B Compared to the illustrated electronic / photonic package 900, the electronic / photonic package 1000 omits the active interconnect 902 and the stacking structure 904. Therefore, all the first EICs 404a and second EICs 404b can be directly attached to and electrically coupled to the electronic interconnect 408. Thus, the electronic / photonic package 1000 simplifies the electrical connections formed between the various EICs (404a, 404b) and the electronic interconnect 408. Figure 9A and Figure 9B The relative simplicity of the electronic / photonic package 900 can be advantageous for certain applications.

[0261] and Figure 9A and Figure 9B The electronic / photonic packaging is the same as the 900. Figure 10A and Figure 10B The electronic / photonic package 1000 may further include photonic components that can provide optical / photonic signal functionality. For example, the electronic / photonic package 1000 may include multiple PICs (200a, 200b, 200c, 200d) and optical engines (402a, 402b, 402c). Therefore, the signal channels within the electronic / photonic package 1000 may include electronic signal channels (e.g., see solid arrows) and photonic signal channels (e.g., see dashed arrows). Figure 10A As shown, electronic signal channels can exist between adjacent first EICs 404a, between first EICs 404a and second EICs 404b, between first EICs 404a and one or more optical engines (402a, 402b, 402c), and between second EICs 404b and one or more optical engines (402a, 402b, 402c).

[0262] and Figure 9A and Figure 9B Similar to the electronic / photonic package 900, besides reducing ohmic losses by providing a photonic signal path, one or more PICs (200a, 200b, 200c, 200d) can directly provide the functionality to perform (classical or quantum) logic operations on the photonic signal. Therefore, various PICs (200a, 200b, 200c, 200d) can provide their own functions and have their own structural configurations. For example, some PICs (200a, 200b, 200c, 200d) may have more limited functionality than others. For example, some PICs (200a, 200b, 200c, 200d) can be configured as photonic transceivers, as described above. Figure 2Alternatively, other PICs (200a, 200b, 200c, 200d) can be configured to perform a variety of functions including photon signal generation and photon signal processing.

[0263] Unlike the other embodiments described above (for example, see...), Figures 4 to 5B The optical engines (402a, 402b, 402c) can be larger and configured to provide more functionality than the other optical engines mentioned above. In this regard, Figure 10A and Figure 10B The optical engines (402a, 402b, 402c) can be larger, single-unit devices that provide enhanced functionality. In this regard, Figure 10A and Figure 10B The optical engines (402a, 402b, 402c) can be configured to be optically coupled to two or more PICs, and electrically connected to multiple first EICs 404a and second EICs 404b. For example, as Figure 10A As shown, the first single optical engine 402a can be electrically coupled to the second EICs 404b, which is attached to the electronic interconnect 408 adjacent to the first single optical engine 402a.

[0264] Furthermore, the first single-unit optical engine 402a can be optically coupled to the first PIC 200a and the second PIC 200b. Therefore, according to a specific embodiment, photonic logic operations can be performed by the first PIC 200a and the second PIC 200b, and the results of photonic computations can be provided to the first single-unit optical engine 402a via the first photonic interconnect chip 502a and the second photonic interconnect chip 502b, respectively. The photonic signals received by the first single-unit optical engine 402a can then be converted into corresponding electrical signals, which encode data representing the results of the logic operations performed by the first PIC 200a and the second PIC 200b. Conversely, the data can then be provided to one or more data storage devices provided by second EICs adjacent to the first single-unit optical engine 402a, which can store the corresponding data.

[0265] The electronic / photonic package 1000 may further include an FAU 802, which can be configured to transmit and receive photonic signals. As shown, the FAU 802 provides a photonic interface between the second single-unit optical engine 402b and external photonic circuitry (not shown). The FAU 802 can be configured similarly to the above reference. Figure 8B and Figure 8C The FAU 802 is described and can provide similar photon signaling capabilities.

[0266] Figure 10B It is shown according to various embodiments Figure 10AA cross-sectional view of a portion of the electronic / photonic package 1000. Definition Figure 10B The vertical plane of the cross-sectional view is composed of Figure 10A The section B-B' is indicated in the figure. Figure 10A A portion of the electronic / photonic package 1000 includes a first photonic interconnect chip 502a and a second photonic interconnect chip 502b. The first photonic interconnect chip 502a is optically connected to a first single-unit optical engine 402a and a first PIC 200a. Similarly, the second photonic interconnect chip 502b is optically connected to the first PIC 200a and the second single-unit optical engine 402b.

[0267] Figure 11 This is a top view illustrating a further electronic / photonic package 1100 including a first component package 1102a and a second component package 1102b according to various embodiments. The first component package 1102a may include a plurality of first EICs 404a attached to a first electronic interconnect 408a, while the second component package 1102b may include a plurality of second EICs 404b. As shown, the first electronic interconnect 408a may be attached to a first package substrate 410a, and the second electronic interconnect 408b may be attached to a second package substrate 410b. The first component package 1102a may be optimized to perform computational logic operations, while the second component package 1102b may be optimized to perform data storage and retrieval operations.

[0268] In this regard, the plurality of first EICs 404a in the first component package 1102a can be CPU chips, GPU chips, application-specific integrated circuits (ASICs), etc., while the plurality of second EICs 404b in the second component package 1102b can be memory (e.g., high bandwidth memory (HBM)) chips that provide data storage functionality. See reference... Figure 9A and Figure 9B In the stacked structure 904, one or more first EICs 404a of the first component package 1102a may be attached to the active interconnect 902, and one or more second EICs 404b of the second component package 1102b may be attached to the first EIC 404a. In another embodiment, the active interconnect 902 and the EIC 404a of the stacked structure 904 may be omitted.

[0269] Each of the first component package 1102a and the second component package 1102b may further include photonic components that can provide optical / photonic signal functionality. For example, each of the first component package 1102a and the second component package 1102b may include one or more PICs (200a, 200b, 200c, 200d) and one or more optical engines (402a, 402b). Therefore, each of the first component package 1102a and the second component package 1102b may include an electronic signal channel (e.g., see solid arrows) and a photonic signal channel (e.g., see dashed arrows).

[0270] As mentioned above, the various PICs (200a, 200b, 200c, 200d) can have different configurations and provide their own functions. For example, some PICs (200a, 200b) can be configured as standalone PICs, as shown in [reference]. Figure 9A and Figure 9B As described in more detail, other PICs (200c, 200d) may have simpler structures and perform their respective functions. Furthermore, see reference... Figure 10A and Figure 10B The first component package 1102a and the second component package 1102b may contain one or more individual optical engines (402a, 402b). As described above, the one or more individual optical engines (402a, 402b) may be configured to interact with a plurality of EICs (404a, 404b) and convert electronic signals into photonic signals, and vice versa.

[0271] like Figure 11 As further shown, the first component package 1102a and the second component package 1102b can be optically coupled to each other via an optical fiber cable 810. In this regard, the first component package 1102a may include a first FAU 802a coupled to a first end of the optical fiber cable 810, while the second component package 1102b may include a second FAU 802b coupled to a second end of the optical fiber cable 810. Data can be transmitted between the first component package 1102a and the second component package 1102b via the optical fiber cable 810. As shown, the first FAU 802a and the second FAU 802b can be optically coupled to their respective individual PIC 200b or optical engine 402b.

[0272] Data generated by the computational logic process executed by the first EICs 404a through the first component package 1102a can be transmitted to the second component package 1102b in the form of photonic signals. These photonic signals received by the second component package 1102b can then be converted into electrical signals and provided to the second EICs 404b for storage as digital data. Similarly, data stored in the second component package 1102b by the second EICs 404b can be retrieved as needed and sent back to the first component package 1102a for use in the continuous logic operations performed by the first EICs 404a of the first component package 1102a.

[0273] like Figure 11 As shown in the diagram (omitted 1104), the first component package 1102a and the second component package 1102b can represent a repeating unit in an electronic / photonic package 1100 comprising multiple component packages. Therefore, the multiple first component packages 1102a can form a computing resource pool that performs logical operations. Similarly, the multiple second component packages 1102b can provide a storage resource pool that performs data storage and retrieval operations.

[0274] Figure 12 This is a cross-sectional view illustrating a further electronic / photonic package 1200 including a photonic interconnect chip 502 with an edge coupler 306b, according to various embodiments. As shown, the electronic / photonic package 1200 may include a first optical engine 402a and a second optical engine 402b. The first optical engine 402a and the second optical engine 402b may be attached to and electrically coupled to an electronic interconnect 408. The electronic interconnect 408 may be further attached to and electrically coupled to a package substrate 410.

[0275] The photonic interconnect chip 502 may include a substrate 520 and a cladding layer 522 formed over the substrate 520. The photonic interconnect chip 502 may further include a core portion 524 formed within the cladding layer 522, such that the core portion 524 and the cladding layer 522 form a dielectric waveguide 104. As in other embodiments described above, the core portion 524 may be selected as a dielectric material having a higher refractive index than the cladding layer 522. Therefore, photonic signals may preferentially propagate within the core portion 524 of the dielectric waveguide.

[0276] However, unlike the embodiments described above (for example, see...), Figure 5B The photonic interconnect chip 502 can be configured to allow photonic signals to enter and exit the photonic interconnect chip 502 through the edge coupler 306b. (See above for reference.) Figure 3DThe edge coupler 306b may include a plane of waveguide 104, allowing photonic signals to be coupled into and out of the ends of the dielectric waveguide 104. In some embodiments, the edge coupler 306b may further include a spot size converter (e.g., see...). Figure 17A and Figure 17B This allows for an increase in the lateral size of the optical mode, enabling efficient coupling of photonic signals between the dielectric waveguide 104 and the optical fiber (also not shown).

[0277] like Figure 12 As shown, the photonic interconnect chip 502 can be formed such that the substrate 520 has a first width 1202a, which is larger than the second width 1202b of the dielectric waveguide 104. Therefore, the photonic interconnect chip 502 can be positioned such that the corresponding edges of the substrate 520 contact the top edges of the first optical engine 402a and the second optical engine 402b. In this respect, the photonic interconnect chip 502 can be mechanically supported by the top edges of the first optical engine 402a and the second optical engine 402b. As shown, the sides of the core portion 524 and the covering portion 522 can contact the corresponding sides of the first optical engine 402a and the second optical engine 402b. Therefore, photonic signals can be coupled from the optical engines (402a, 402b) to the photonic interconnect chip 502 using an edge coupling configuration (i.e., with an edge coupler 306b), and vice versa.

[0278] Figure 13 This is a cross-sectional view of a further electronic / photonic package 1300 comprising a photonic interconnect chip 502 coupling photonic signals between two hybrid interconnects (408a, 408b) according to various embodiments. As shown, the electronic / photonic package 1300 may include a first optical engine 402a and a second optical engine 402b. Each of the first optical engine 402a and the second optical engine 402b may be attached to and electrically coupled to its respective interconnect (408a, 408b). Each interconnect (408a, 408b) may further be attached to and electrically coupled to its respective package substrate (410a, 410b).

[0279] like Figure 13 As shown, each interconnect (408a, 408b) can be configured as a hybrid interconnect (408a, 408b) comprising both electronic signal channels and photonic signal channels. In this respect, each hybrid interconnect (408a, 408b) can be similar to the PIC200 (e.g., see...). Figure 2(and related descriptions) and may include passive components (such as dielectric waveguide 104) and active components (such as photon source 102, detector 106 and modulator 108 (e.g., see...) Figure 1 (and related descriptions). Therefore, the photonic interconnect chip 502 can be attached to the respective surfaces of the hybrid interconnects (408a, 408b). In this respect, photonic signals can be routed from the first hybrid interconnect 408a to the second hybrid interconnect 408b via the photonic interconnect chip 502, and vice versa.

[0280] Figures 14A to 14D The diagram shows cross-sectional views of various intermediate structures (1400a to 1400d) that can be used to form a photonic interconnect chip 502, according to various embodiments. Figure 14A The intermediate structure 1400a may include a substrate 520, a covering portion 522 formed over the substrate 520, and a core material layer 524L formed over the covering portion. According to various embodiments, both the covering portion 522 and the core material layer 524L may be dielectric materials, such that the refractive index of the core material layer 524L is greater than the refractive index of the covering portion 522. For example, the core material layer 524L may be a silicon layer, and the covering portion 522 may be silicon oxide. The substrate 520 may be any suitable substrate that provides mechanical support for the covering portion 522 and the core material layer 524L. In other embodiments, both the covering portion 522 and the core material layer 524L may be polymer materials, selectively such that the refractive index of the core material layer 524L is greater than the refractive index of the covering material layer 524L.

[0281] like Figure 14A and Figure 14B As shown, intermediate structures 1400a and 1400b may further include a patterned photoresist layer 1402 formed above the core material layer 524. The patterned photoresist layer 1402 can be formed by depositing a uniform photoresist layer (not shown) above the core material layer 524L. The uniform photoresist layer can then be patterned using photolithography to form the patterned photoresist layer 1402. The patterned photoresist layer 1402 can then serve as an etching mask in an etching process, which can be used to etch the core material layer 524L. Figure 14B As shown, this type of etching process can form multiple core sections 524. For example... Figure 14C As shown, the patterned photoresist layer 1402 can then be removed by ashing or solvent dissolution, leaving multiple core portions 524 formed on top of the covered portion 522.

[0282] like Figure 14DAs shown, additional cladding material can then be deposited over the multiple core portions 524 to extend the thickness of the cladding portions 522. In this respect, the deposited additional material can thus surround the core portions 524, such that the core portions 524 are formed within the cladding portions. Therefore, each core portion 524 can thus form the core portion of its respective dielectric waveguide 104.

[0283] Figure 14E This is a top view illustrating a further intermediate structure 1400e that can be used to form a photonic interconnect wafer 502, according to various embodiments. Figure 14E As shown, each core portion 524 may extend along a first direction (i.e., the x-direction). The core portions 524 may be separated from each other along a second direction (i.e., the y-direction), which is perpendicular to the first direction. Therefore, each core portion 524 together with the surrounding portion of the covering portion 522 can form a dielectric waveguide.

[0284] Figures 15A to 15C This is a cross-sectional view showing an intermediate structure (1500a to 1500c) that can be used to form a photonic interconnect wafer 502 according to various embodiments. Figure 15A The intermediate structure 1500a can be used in Figure 14D An additional core material layer 524L is deposited above the intermediate structure 1400d, and then a patterned photoresist 1402 is formed on top of the additional core material layer 524L. In this respect, the patterned photoresist 1402 can be formed by depositing a uniform photoresist layer (not shown) on the additional core material layer 524L. The uniform photoresist layer can then be patterned using photolithography to form the patterned photoresist layer 1402. The patterned photoresist layer 1402 can then be used as an etch mask in an etching process for etching the core material layer 514L. Figure 15B As shown, this type of etching process can form multiple additional core portions 524. The patterned photoresist layer 1402 can then be removed by ashing or solvent dissolution, leaving multiple core portions 524 formed on top of the covered portion 522.

[0285] like Figure 15C As shown, additional cladding material can then be deposited over the multiple core portions 524 to extend the thickness of the cladding portions 522. In this respect, the deposited additional material can then surround the additional core portions 524, such that the core portions 524 are formed within the cladding portions 522. Thus, each additional core portion 524 can thus form the core portion of its respective dielectric waveguide 104. Therefore, by repeating the above and... Figures 14A to 15C The related processes form multiple dielectric waveguides 104 in a three-dimensional configuration.

[0286] Figures 16A to 16CThe figures show vertical cross-sectional views of various intermediate structures (1600a to 1600c) that can be used to form a photonic interconnect wafer 502, according to various embodiments. Figure 16D Various embodiments are shown by reference. Figures 16A to 16C The described process forms a vertical cross-sectional view of the photonic interconnect wafer 502. The intermediate structure 1600a may include a core portion 524 formed within the covering portion 522. (Refer to the above text.) Figures 14A to 15C The core portion 524 can be one of multiple core portions 524. For example... Figure 16B As shown, the first beveled trench 1602a and the second beveled trench 1602b can be formed in the covering portion 522. The first beveled trench 1602a and the second beveled trench 1602b can be formed by etching the covering portion 522. In this regard, a multi-tone mask can be used to perform the etching process that creates the bevels.

[0287] Then, a dielectric material layer 1604L can be deposited on top of the intermediate structure 1600b to form... Figure 16C The intermediate structure 1600c. A planarization process (e.g., chemical mechanical planarization) can then be performed to remove excess portions of the dielectric material layer 1604L on the top surface of the covered portion 522, thereby forming... Figure 16D The photonic interconnect chip 502. For example... Figure 16D As shown, the remaining portion of the dielectric material layer 1604L can be filled with the beveled trenches (1602a, 1602b) to form the first dielectric window 1604a and the second dielectric window 1604b.

[0288] like Figure 16D As shown, the photonic interconnect chip 502 includes a substrate 520 and a dielectric waveguide 104 formed on the substrate 520. The dielectric waveguide 104 includes a core portion 524 and a cladding portion 522. The photonic interconnect chip 502 also includes a first photonic coupler 112a formed at a first end of the dielectric waveguide 104 and a second photonic coupler 112b formed at a second end of the dielectric waveguide 104. Figure 16D As shown, the dielectric waveguide 104 has a planar geometry within the cladding portion 522, such that the surface 1606 of the dielectric waveguide 104 (e.g., the surface 1606 of the core portion 524) is parallel to the first surface 1608a of the photonic interconnect wafer. Furthermore, as... Figure 16D As shown, the first photonic coupler 112a and the second photonic coupler 112b each couple the photonic signal 310 into and out of the photonic interconnect chip, so that the photonic signal channel (see dashed line) connects the first photonic coupler 112a, the dielectric waveguide 104 and the second photonic coupler 112b.

[0289] In addition, such as Figure 16DAs shown, the first dielectric window 1604a may be located at a first position (e.g., on the left side) on the first surface 1608a of the photonic interconnect wafer 502, while the second dielectric window 1604b may be located at a second position (e.g., on the right side) on the first surface 1608a of the photonic interconnect wafer 502. In this respect, the first photonic coupler 112a and the second photonic coupler 112b respectively couple the photonic signal 310 into and out of the photonic interconnect wafer 502 through the first dielectric window 1604a and the second dielectric window 1604b.

[0290] like Figure 16D As shown, the first photonic coupler 112a can be configured as a first angled reflector 306c (e.g., see...). Figure 5B The first photonic coupler 112a couples the photonic signal 310 received from the first dielectric window 1604a into the dielectric waveguide 104. The first photonic coupler 112a can further transmit the photonic signal received from the dielectric waveguide 104 through the first dielectric window 1604a. Similarly, the second photonic coupler 112b can be configured as a second angled reflector 306c (e.g., see...). Figure 5B It couples the photon signal 310 received from the second dielectric window 1604b into the dielectric waveguide 104, and transmits the photon signal received from the dielectric waveguide 104 through the second dielectric window 1604b.

[0291] Figures 16E to 16H This is a vertical cross-sectional view illustrating an additional photonic interconnect wafer 502 including an angled reflector, according to various embodiments. Figure 16E As shown, each angled reflector may further include a reflective coating 1610. The reflective coating may be a metallic material, which may be deposited prior to the deposition of the dielectric material layer 1604L. Figure 16B Above each beveled groove (1602a, 1602b) of the intermediate structure 1600b. Or, as Figure 16F As shown, the multilayer dielectric stack 1612 can be formed before the deposition of the dielectric material layer 1604L. Figure 16B Above each beveled groove (1602a, 1602b) of the intermediate structure 1600b.

[0292] The multilayer dielectric stack 1612 may comprise thin, alternating layers of dielectric material, such that the multilayer dielectric stack 1612 forms a reflector. In this respect, electromagnetic fields reflected multiple times from the layers of the multilayer dielectric stack 1612 can constructively interfere, enabling the multilayer dielectric stack 1612 to function as a reflector. In some embodiments, the multilayer dielectric stack 1612 can provide strongly reflected photonic signals without the ohmic losses that might occur with the use of a metallic reflector 1610.

[0293] like Figure 16G and Figure 16HAs shown, each photonic interconnect chip 502 may include a first photonic coupler 112a and a second photonic coupler 112b having a curved reflector 806. (Refer to the above...) Figure 8C The curved reflector 806 can be produced by an etching process using a multi-mask. Figure 16H As shown, the photonic interconnect chip may further include a transition edge coupler 1616 structure. As illustrated, the transition edge coupler 1616 may include additional core portions (524a, 524b) formed adjacent to the core portion 524. These additional core portions (524a, 524b) can be described using the methods referenced above. Figures 14A to 15C The described processing operations form the transition edge coupler 1616, which can be used to extend the lateral width of the electromagnetic field associated with the photon signal propagating within the core portion 524 of the dielectric waveguide 104. A similar edge coupler 306b (see...) Figure 3D (Refer to the following text) Figure 17A and Figure 17B As described in the text.

[0294] Figure 17A Various embodiments are shown including an edge coupler 306b (see [reference]). Figure 3D A top view of the photonic interconnect chip 502, and Figure 17B It is shown according to various embodiments Figure 17A A vertical cross-sectional view of the photonic interconnect chip 502. Definition Figure 17B The vertical plane of the cross-sectional view is composed of Figure 17A The cross-section B-B' is indicated in the figure. As shown, the photonic interconnect wafer 502 may include a plurality of dielectric waveguides 104, each including a core portion 524 surrounded by a covering portion 522. As shown, each core portion 524 may have a tapered end 1702. Each tapered end 1702 of the core portion 524 may be enclosed within a further region of the dielectric material 1704, thereby forming a spot size converter (SSC). As shown, the distribution of electromagnetic field lines 1706 may be extended by an edge coupler 306b. In this respect, the field within the core portion may have a smaller lateral distribution than the field lines that can be coupled into and out of the photonic interconnect wafer. Therefore, the photonic interconnect wafer 502 including the edge coupler 306b can effectively couple photonic signals from the dielectric waveguides 104 to an external optical fiber (not shown).

[0295] like Figure 17BAs shown, the first dielectric window 1604a and the second dielectric window 1604b can be formed on the corresponding surfaces (1608b, 1608c) of the first photonic coupler 112a and the second photonic coupler 112b, respectively. In this respect, the first dielectric window 1604a can be located on the second surface 1608b of the photonic interconnect wafer 502, perpendicular to the first surface 1608a of the photonic interconnect wafer 502. Similarly, the second dielectric window 1604b can be located on the third surface 1608c of the photonic interconnect wafer 502, also perpendicular to the first surface 1608a of the photonic interconnect wafer 502. In this exemplary embodiment, the third surface 1608c of the photonic interconnect wafer 502 is parallel to and opposite to the second surface 1608b. Therefore, each of the first photonic coupler 112a and the second photonic coupler 112b couples the photonic signal 310 into and out of the photonic interconnect chip 502 through the first dielectric window 1604a and the second dielectric window 1604b, respectively.

[0296] Figure 18A Various embodiments are shown that can be used to form a grating coupler 306a (see...). Figure 3C A top view of the intermediate structure of the photonic interconnect chip 502. Figure 18B It is shown according to various embodiments Figure 18A A cross-sectional view of the intermediate structure, and Figure 18C This is a cross-sectional view of a photonic interconnect wafer including a grating coupler, according to various embodiments. Definitions Figure 18B The vertical plane of the cross-sectional view is composed of Figure 18A The cross-section B-B' is indicated in the figure. As shown, each dielectric waveguide 104 may contain a corresponding core portion 524 surrounded by the covered portion. Figures 18A to 18C The dielectric waveguide in the above can be connected to the dielectric waveguide in the above-mentioned Figures 14A to 15C The processes described are similar to those used in manufacturing.

[0297] like Figure 18A As shown, each core portion 524 may include a grating coupler 306a formed at each end of the core portion 524. In this regard, each end of the core portion 524 may include an extension portion comprising a plurality of trenches 308. The trenches may be formed by etching the top surface of the core portion 524, such as... Figure 18B As shown. Figure 18C The photonic interconnect chip 502 in the middle can be made by Figure 18A and Figure 18B The intermediate structure 1800 is formed, and the covering portion 522 surrounds the core portion 524 by forming an additional covering material layer. For example... Figure 18C As shown, additional dielectric material 1604L can then be deposited on top of the intermediate structure 1800 (see...). Figure 16CDielectric windows (1604a, 1604b) are formed. Then, a planarization process can be performed to remove excess portions of the dielectric material layer 1604L, thereby creating the dielectric windows (1604a, 1604b), as shown above. Figure 16C and Figure 16D As stated above.

[0298] As shown in the figure, the photonic signal 310 can be coupled into and out of the photonic interconnect chip 502 through photonic couplers (112a, 112b). Therefore, as... Figures 16D to 16H In one embodiment, the first dielectric window 1604a may be located at a first position (e.g., the left side) of the first surface 1608a of the photonic interconnect wafer 502, while the second dielectric window 1604b may be located at a second position (e.g., the right side) of the first surface 1608a of the photonic interconnect wafer 502.

[0299] Figures 19A to 19D This is a vertical cross-sectional view illustrating intermediate structures (1900a to 1900d) for forming a photonic interconnect chip according to various embodiments. The intermediate structure 1900a can be formed by forming a cladding material layer 522L over a substrate (not shown). The cladding material layer 522L can be selected from a photosensitive polymer material. Laser writing operations can then be performed on the cladding material layer 522L to create a core portion 524. In this respect, as... Figure 19B As shown, laser 1902 can generate a laser radiation 1904, which is guided to a specific depth 1906 within the cladding material layer 522L. The laser radiation 1904 can be selected to have a specific beam width 1908.

[0300] In response to the absorption of laser radiation during laser writing operations, the interaction between laser radiation 1904 and the coating material layer 522L can be used to alter the microstructure of the polymer material of the coating material layer 522L in a localized region. The altered microstructure is characterized by an increase in refractive index relative to the coating material layer 522L. Therefore, as... Figure 19C As shown, the irradiated local area can then serve as the core portion 524, while the unirradiated portion surrounding the covering material layer 522L can serve as the covering portion 522. The use of laser writing allows for considerable flexibility in the spatial layout of the core portion 524. For example, as... Figure 19D As shown, multiple dielectric waveguides 104 with a non-uniform spatial distribution can be generated. For example, the multiple dielectric waveguides 104 may include a fan-out configuration, wherein the linear spacing of the core portions 524 may increase laterally (e.g., in the y-direction) as a function of the longitudinal direction (e.g., the x-direction).

[0301] Figure 20This is a flowchart illustrating a method 2000 for forming a photonic interconnect wafer 502 according to various embodiments. In operation 2002, method 2000 may include forming a waveguide cladding portion 522 on a substrate 520. In operation 2004, method 2000 may include forming a waveguide core portion 524 within the waveguide cladding portion 522. In operation 2006, method 2000 may include forming a first photonic coupler 112a at a first end of the waveguide core portion 524. In operation 2008, method 2000 may include forming a second photonic coupler 112b at a second end of the waveguide core portion 524.

[0302] In operation 2002, forming the cladding portions (522, 304), and in operation 2004, forming the waveguide core portions (524, 302b), method 2000 may further include forming a silicon-on-insulator substrate 302, which includes a silicon substrate 302a, a first silicon dioxide layer 304 formed above the silicon substrate 302a, and a silicon layer 302b formed above the first silicon dioxide layer 304. Method 2000 may further include patterning and etching the silicon layer 302b to form the silicon waveguide core portions (524, 302b). Method 2000 may further include forming a second silicon dioxide layer 304 above the waveguide core portions (522, 304), such that the waveguide core portions 524 are surrounded by silicon dioxide 304, thus the waveguide cladding portion 522 may include both the first silicon dioxide layer 304 and the second silicon dioxide layer 304.

[0303] In operation 2002 forming the cladding portion (522, 304) and in operation 2004 forming the waveguide core portion (524, 302b), method 2000 may further include forming a first layer of a first polymer material 522 over the substrate 520; forming a second layer of a second polymer material 524L over the substrate 520; patterning the second layer of the second polymer material 524L to form the waveguide core portion 524; and forming a third layer of the first polymer material 522 over the waveguide core portion 524, such that the first layer and the third layer of the first polymer material 522 form the waveguide cladding portion 522. In operation 2002 forming the covering portion (522, 304) and in operation 2004 forming the waveguide core portion (524, 302b), method 2000 may further include forming a radiation-curable polymer material 522L above the substrate 520; and using laser radiation 1904 to irradiate the area of ​​the radiation-curable polymer material 522L in the laser writing operation to form the waveguide core portion 524, such that the unirradiated portion of the radiation-curable polymer material 522L can serve as the waveguide covering portion 522.

[0304] Referring to all the accompanying drawings and various embodiments of the present invention, a photonic interconnect chip 502 is provided. The photonic interconnect chip 502 may include a substrate 520, a dielectric waveguide 104, a first photonic coupler 112a, and a second photonic coupler 112b. The dielectric waveguide 104 includes a core portion 524 and a covering portion 522 and is formed on the substrate 520. The first photonic coupler 112a is formed at a first end of the dielectric waveguide 104, and the second photonic coupler 112b is formed at a second end of the dielectric waveguide 104. The dielectric waveguide 104 may include a planar geometry located within the covering portion 522, such that the surface of the dielectric waveguide 104 is parallel to the first surface 1608a of the photonic interconnect chip 502.

[0305] Each of the first photonic coupler 112a and the second photonic coupler 112b can couple the photonic signal 310 into and out of the photonic interconnect chip 502, such that photonic signal channels (514a, 524, 514b) connect the first photonic coupler 112a, the dielectric waveguide 104, and the second photonic coupler 112b. The photonic interconnect chip 502 may also include a first dielectric window 1604a and a second dielectric window 1604b, wherein the first dielectric window 1604a is located at a first position on the first surface 1608a of the photonic interconnect chip 502, and the second dielectric window 1604b is located at a second position on the first surface 1608a of the photonic interconnect chip 502. The first photonic coupler 112a and the second photonic coupler 112b can couple the photonic signal 310 into and out of the photonic interconnect chip 502 through the first dielectric window 1604a and the second dielectric window 1604b, respectively.

[0306] In some embodiments, the first photonic coupler 112a may include a first grating coupler 306a, which couples the first input photonic signal 310 received from the first dielectric window 1604a into the dielectric waveguide 104 and transmits the first output photonic signal 310 received from the dielectric waveguide 104 through the first dielectric window 1604a. Similarly, the second photonic coupler 112b may include a second grating coupler 306a, which couples the second input photonic signal 310 received from the second dielectric window 1604b into the dielectric waveguide 104 and transmits the second output photonic signal 310 received from the dielectric waveguide 104 through the second dielectric window 1604b.

[0307] In a further embodiment, the first photonic coupler 112a may include a first angled reflector 306c, which couples the first input photonic signal 310 received from the first dielectric window 1604a into the dielectric waveguide 104 and transmits the first output photonic signal 310 received from the dielectric waveguide 104 through the first dielectric window 1604a. Similarly, the second photonic coupler 112b may include a second angled reflector 306c, which couples the second input photonic signal 310 received from the second dielectric window 1604b into the dielectric waveguide 104 and transmits the second output photonic signal 310 received from the dielectric waveguide 104 through the second dielectric window 1604b.

[0308] In other embodiments, the first dielectric window 1604a may be located on the second surface 1608b of the photonic interconnect wafer 502, with the second surface 1608b perpendicular to the first surface 1608a of the photonic interconnect wafer 502. The second dielectric window 1604b may be located on the third surface 1608c of the photonic interconnect wafer 502, with the third surface 1608c perpendicular to the first surface 1608a of the photonic interconnect wafer 502, such that the third surface 1608c of the photonic interconnect wafer 502 is parallel and opposite to the second surface 1608b. In this embodiment, the first photonic coupler 112a and the second photonic coupler 112b can couple the photonic signal 310 into and out of the photonic interconnect wafer 502 through the first dielectric window 1604a and the second dielectric window 1604b, respectively.

[0309] According to a specific embodiment, the first photonic coupler 112a may include a first edge coupler 306b that couples a first input photonic signal 310 received from a first dielectric window 1604a into the dielectric waveguide 104 and transmits a first output photonic signal 310 received from the dielectric waveguide 104 through the first dielectric window 1604a. Similarly, the second photonic coupler 112b may include a second edge coupler 306b that couples a second input photonic signal 310 received from a second dielectric window 1604b into the dielectric waveguide 104 and transmits a second output photonic signal 310 received from the dielectric waveguide 104 through the second dielectric window 1604b. In some embodiments, each of the first edge coupler 306b and the second edge coupler 306b may include a tapered end 1702 of the dielectric waveguide 104 in contact with the enclosing dielectric material 1704.

[0310] According to a particular embodiment, each of the first edge coupler 306b and the second edge coupler 306b may include a transition edge coupler 1616. The core portion 524 may include a first material having a first refractive index, while the cladding portion 522 may include a second material having a second refractive index, the second refractive index being less than the first refractive index. In some embodiments, the core portion 524 may include silicon, while the cladding portion 522 may include silicon dioxide. In other embodiments, the core portion 524 may include a first polymer material, while the cladding portion 522 may include a second polymer material.

[0311] Referring to all the accompanying drawings and various embodiments of the present invention, an electronic / photonic package (400, 500, 700, 800, 900, 1000, 1100, 1200, 1300) is provided. The electronic / photonic package (400, 500, 700, 800, 900, 1000, 1100, 1200, 1300) may include a first photonic component (200a, 402a), a second photonic component (200b, 402b), and a photonic interconnect chip 502. The first photonic component (200a, 402a) includes a first photonic signal channel (310, 514a), the second photonic component (200b, 402b) includes a second photonic signal channel (310b, 514b), and the photonic interconnect chip 502 includes a plurality of dielectric waveguides 104. The photonic interconnect chip 502 can be coupled to the first photonic component (200a, 402a) and the second photonic component (200b, 402b), so that the first photonic signal channel (310, 514a) is optically coupled to the second photonic signal channel (310b, 514b) through multiple dielectric waveguides 104.

[0312] The electronic / photonic package (400, 500, 700, 800, 900, 1000, 1100, 1200, 1300) may further include an interconnect 408, such that the first photonic component (200a, 402a) and the second photonic component (200b, 402b) are formed as separate wafers and attached to and electrically coupled to the interconnect 408. A first portion 526a of the photonic interconnect wafer 502 may be mechanically and optically coupled to the first photonic component (200a, 402a), and a second portion 526b of the photonic interconnect wafer 502 may be mechanically and optically coupled to the second photonic component (200b, 402b), thereby configuring the photonic interconnect wafer 502 as an in-package photonic coupler (502a, 502c, see...). Figure 8B ).

[0313] In a further embodiment, the electronic / photonic package (400, 500, 700, 800, 900, 1000, 1100, 1200, 1300) may include a first interconnect 408a and a second interconnect 408b, such that a first photonic component (200a, 402a) is attached to and electrically coupled to the first interconnect 408a, while a second photonic component (200b, 402b) is attached to and electrically coupled to the second interconnect 408b. In this regard, a first portion 526a of the photonic interconnect chip 502 may be mechanically and optically coupled to the first photonic component (200a, 402a), and a second portion 526b of the photonic interconnect chip 502 may be mechanically and optically coupled to the second photonic component (200b, 402b), thereby configuring the photonic interconnect chip 502 as an inter-package photonic coupler 502b (see [link to documentation]). Figure 8B ).

[0314] According to various embodiments, the photonic interconnect chip 502 may further include a substrate 520, a covering portion 522 formed on the substrate 520, a plurality of dielectric waveguide core portions 524 formed within the covering portion, a plurality of first photonic couplers 112a, and a plurality of second photonic couplers 112b. According to various embodiments, each of the plurality of first photonic couplers 112a and the plurality of second photonic couplers 112b is coupled to a first end and a second end of a corresponding dielectric waveguide core portion 524. Furthermore, the plurality of first photonic couplers 112a and the plurality of second photonic couplers 112b may be configured to guide photonic signals 310 into and out of the photonic interconnect chip 502, such that corresponding photonic signal paths (310c, 524) connect each dielectric waveguide 104 to a corresponding one of the plurality of first photonic couplers 112a and the plurality of second photonic couplers 112b. In some embodiments, a plurality of dielectric waveguides 104 may be formed on a common planar substrate 520 and may include a fan-out configuration (see Figure 19D Alternatively, multiple dielectric waveguides 104 may be arranged in a three-dimensional configuration within the covering portion 522 (see...). Figure 15C ).

[0315] Referring to all the accompanying drawings and various embodiments of the present invention, a method for forming a photonic interconnect chip is provided, comprising the following steps: forming a waveguide cladding portion on a substrate; forming a waveguide core portion within the waveguide cladding portion; forming a first photonic coupler at a first end of the waveguide core portion; and forming a second photonic coupler at a second end of the waveguide core portion.

[0316] According to various embodiments, forming a waveguide cladding portion on a substrate and forming a waveguide core portion within the waveguide cladding portion further includes the following steps: forming a silicon-on-insulator substrate, the silicon-on-insulator substrate including a silicon substrate, a first silicon dioxide layer formed on the silicon substrate, and a silicon layer formed on the first silicon dioxide layer; patterning and etching the silicon layer to form the silicon waveguide core portion; forming a second silicon dioxide layer above the waveguide core portion such that the waveguide core portion is surrounded by silicon dioxide, thus the waveguide cladding portion includes the first silicon dioxide layer and the second silicon dioxide layer.

[0317] According to various embodiments, forming a waveguide cladding portion on a substrate and forming a waveguide core portion within the waveguide cladding portion further includes the following steps: forming a first layer of a first polymer material over the substrate; forming a second layer of a second polymer material over the substrate; patterning the second layer of the second polymer material to form the waveguide core portion; and forming a third layer of the first polymer material over the waveguide core portion, wherein the first and third layers of the first polymer material comprise the waveguide cladding portion.

[0318] According to various embodiments, forming a waveguide cladding portion on a substrate and forming a waveguide core portion within the waveguide cladding portion further includes the following steps: A radiation-curable polymer material is formed above the substrate. During a laser writing operation, a region of the radiation-curable polymer material is irradiated with laser radiation to form the waveguide core portion of the waveguide, wherein the unirradiated portion of the radiation-curable polymer material includes the waveguide cladding portion.

[0319] Embodiments of the utility model provide a photonic interconnect chip 502 that allows photonic signals 310 to propagate between a first photonic component (200a, 402a) and a second photonic component (200b, 402b) within an electronic / photonic package (400, 500, 700, 800, 900, 1000, 1100, 1200, 1300). Integrating optical / photonic signal functionality into the electronic / photonic package (400, 500, 700, 800, 900, 1000, 1100, 1200, 1300) can provide lower signal delay and ohmic loss. In this regard, in certain embodiments, it may be advantageous to transmit the signal as a photonic signal 310 along a portion of the signal path to avoid long electrical signal paths and associated delays and ohmic losses.

[0320] This can be achieved by converting an electrical signal into a photonic signal 310 at a first point along the signal path, propagating the photonic signal a certain distance, and then converting the photonic signal back into an electrical signal at a second point along the signal path. In a further embodiment, the ability to convert electrical signals into photonic signals 310 and vice versa may be advantageous in photonic (quantum or classical) computing operations. The use of photonic interconnect chip 502 allows various electronic and photonic components (200, 402) to be fabricated separately as independent chips. These chips can then be assembled into electronic / photonic packages (400, 500, 700, 800, 900, 1000, 1100, 1200, 1300), and photonic components can be coupled to each other via photonic interconnect chip 502.

[0321] The foregoing outlines features of numerous embodiments to enable those skilled in the art to better understand the present invention from various aspects. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the concept and scope of the present invention. Various changes, substitutions, or modifications can be made to the present invention without departing from its concept and scope.

Claims

1. A photonic interconnect chip, characterized in that, Photonic interconnect chips include: substrate; A dielectric waveguide, comprising a core portion and a cladding portion, is formed on a substrate; A first photonic coupler is formed at the first end of the dielectric waveguide; and The second photonic coupler is formed at the second end of the dielectric waveguide. The dielectric waveguide contains a planar geometry within the cladding portion, such that the surface of the dielectric waveguide is parallel to the first surface of the photonic interconnect wafer, and The first photonic coupler and the second photonic coupler each couple multiple photonic signals into and out of the photonic interconnect chip, so that the photonic signal channel connects the first photonic coupler, the dielectric waveguide and the second photonic coupler.

2. The photonic interconnect chip as described in claim 1, characterized in that, Photonic interconnect chips also include: The first dielectric window is located at a first position on the first surface of the photonic interconnect chip; and The second dielectric window is located at a second position on the first surface of the photonic interconnect wafer. The first photonic coupler and the second photonic coupler each couple multiple photonic signals into and out of the photonic interconnect chip through the first dielectric window and the second dielectric window, respectively.

3. The photonic interconnect chip as described in claim 2, characterized in that: The first photonic coupler includes a first grating coupler, which couples multiple first input photonic signals received from a first dielectric window into a dielectric waveguide, and transmits multiple first output photonic signals received from the dielectric waveguide through the first dielectric window; and The second photonic coupler includes a second grating coupler, which couples multiple second input photonic signals received from the second dielectric window into the dielectric waveguide and transmits multiple second output photonic signals received from the dielectric waveguide through the second dielectric window.

4. The photonic interconnect chip as described in claim 2, characterized in that: The first photonic coupler includes a first angled reflector, which couples multiple first input photonic signals received from a first dielectric window into a dielectric waveguide, and transmits multiple first output photonic signals received from the dielectric waveguide through the first dielectric window; and The second photonic coupler includes a second angled reflector, which couples multiple second input photonic signals received from the second dielectric window into the dielectric waveguide and transmits multiple second output photonic signals received from the dielectric waveguide through the second dielectric window.

5. The photonic interconnect chip as described in claim 1, characterized in that, Photonic interconnect chips also include: A first dielectric window is located on the second surface of the photonic interconnect chip, and the second surface is perpendicular to the first surface of the photonic interconnect chip; and The second dielectric window is located on the third surface of the photonic interconnect wafer. The third surface is perpendicular to the first surface of the photonic interconnect wafer and parallel to and opposite to the second surface. The first photonic coupler and the second photonic coupler each couple multiple photonic signals into and out of the photonic interconnect chip through the first dielectric window and the second dielectric window, respectively.

6. The photonic interconnect chip as described in claim 5, characterized in that: The first photonic coupler includes a first edge coupler, which couples multiple first input photonic signals received from a first dielectric window into a dielectric waveguide, and transmits multiple first output photonic signals received from the dielectric waveguide through the first dielectric window; and The second photonic coupler includes a second edge coupler, which couples multiple second input photonic signals received from the second dielectric window into the dielectric waveguide and transmits multiple second output photonic signals received from the dielectric waveguide through the second dielectric window.

7. An electronic / photonic package, characterized in that, Electronic / photonic packaging includes: The first photonic component includes multiple first photonic signal channels; The second photonic component includes multiple second photonic signal channels; and Photonic interconnect chip, containing multiple dielectric waveguides, The photonic interconnect chip is coupled to the first photonic component and the second photonic component, so that multiple first photonic signal channels are optically coupled to multiple second photonic signal channels through multiple dielectric waveguides.

8. The electronic / photonic packaging as described in claim 7, characterized in that, Electronic / photonic packaging also includes: Interconnector The first photonic component and the second photonic component are formed as separate wafers and are attached to and electrically coupled to the interconnect. The first part of the photonic interconnect wafer is mechanically and optically coupled to a first photonic component, while the second part of the photonic interconnect wafer is mechanically and optically coupled to a second photonic component, such that the photonic interconnect wafer is configured as an in-package photonic coupler.

9. The electronic / photonic packaging as described in claim 7, characterized in that, Photonic interconnect chips also include: substrate; The covered portion is formed on the substrate; Multiple dielectric waveguide core components are formed within the cladding portion; Multiple first photonic couplers; and Multiple second photonic couplers, Each of the multiple first photonic couplers and multiple second photonic couplers is coupled to its respective first and second ends in the core portion of the multiple dielectric waveguides, and Multiple first photonic couplers and multiple second photonic couplers guide multiple photonic signals into and out of the photonic interconnect chip, such that the corresponding photonic signal channel connects each dielectric waveguide to one of the multiple first photonic couplers and multiple second photonic couplers.

10. The electronic / photonic packaging as described in claim 9, characterized in that: Multiple dielectric waveguides are formed on a coplanar substrate and include a fan-out configuration, or Multiple dielectric waveguides are arranged in a three-dimensional configuration within the cladding portion.

Images