Electronic package and substrate structure thereof
By designing stress concentration areas and setting stress extension lines in the substrate structure, the overlap of surface circuits with the substrate is avoided, and the width of the conductive traces in the stress concentration areas is widened, thus solving the problem of circuit damage in the ball grid array packaging structure and maintaining the stability and reliability of the substrate.
Patent Information
- Application Number
- CN202520174016.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2025-01-21
- Filing Date
- 2025-01-26
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-01-26
AI Technical Summary
Existing ball grid array packaging structures are prone to green paint cracking or surface circuit breakage on the packaging substrate surface, and solutions that change the material or appearance size are difficult for customers to accept.
Stress concentration areas are designed in the substrate structure and stress extension lines are set on them. The layout direction of the surface circuit does not overlap with the stress extension lines. The width of the conductive traces is widened in the stress concentration areas to avoid circuit damage.
This effectively avoids the problems of green paint cracking and surface circuit breakage on the packaging substrate, maintaining the stability of the substrate material and appearance dimensions.
Smart Images
Figure CN223844296U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor structure, and more particularly to an electronic package and its substrate structure. Background Technology
[0002] With the evolution of semiconductor packaging technology, different packaging methods have been developed for semiconductor devices. Among them, ball grid array (BGA), such as PBGA, EBGA, and FCBGA, is an advanced semiconductor packaging technology. Its feature is that a packaging substrate is used to place the semiconductor chip, and a number of solder balls arranged in a grid array are placed on the back of the packaging substrate. This allows more input / output connections to be accommodated on the same unit area of the carrier to meet the needs of highly integrated semiconductor chips.
[0003] like Figure 1 The diagram shown is a cross-sectional view of a prior art ball grid array package structure. In this package structure, a semiconductor chip 110 is disposed on one surface of a package substrate 100, and a plurality of solder balls 120 are arranged in an array on the other surface of the package substrate 100 for subsequent connection to a circuit board.
[0004] Furthermore, with the rapid development of the semiconductor industry, in response to the demand for multi-functional integration and high capacity in electronic products, larger chips are often placed in the packaging structure. This not only tests the circuit design capabilities of the packaging substrate and the packaging process capabilities, but also causes excessive stress on the overall structure, which may even lead to abnormal reliability. Common problems include cracking of the green paint on the surface of the packaging substrate or breakage of the surface circuit on the side with solder balls.
[0005] To solve the problems of cracked green paint or broken surface circuits on the packaging substrate, it is often necessary to change the material of the packaging substrate or change the appearance and size of the semiconductor chip (such as changing the thickness and size of the semiconductor chip). However, this change is a major process change, which customers usually cannot accept.
[0006] Therefore, how to overcome the various problems of the existing technology without changing the materials and appearance dimensions has become an urgent issue to be addressed. Utility Model Content
[0007] In view of the various deficiencies of the prior art, this application provides a substrate structure, including: a substrate body having a first side and a second side opposite to each other, the first side defining a crystal placement area and a peripheral area adjacent to the crystal placement area, the second side defining a projected crystal placement area and a projected peripheral area adjacent to the projected crystal placement area, wherein the projected crystal placement area corresponds to the vertical projection position of the crystal placement area, the projected peripheral area corresponds to the vertical projection position of the peripheral area, a stress concentration area is further defined in the corner of the projected peripheral area corresponding to the projected crystal placement area, and a stress extension line is further defined in the stress concentration area; and a surface circuit formed on the second side of the substrate body and including conductive traces, wherein the arrangement direction of the conductive traces does not overlap with the stress extension line.
[0008] This application also provides an electronic package, including: a substrate structure comprising: a substrate body having a first side and a second side opposite to each other, the first side defining a die-placement area and a peripheral area adjacent to the die-placement area, the second side defining a projected die-placement area and a projected peripheral area adjacent to the projected die-placement area, wherein the projected die-placement area corresponds to a vertical projection position of the die-placement area, the projected peripheral area corresponds to a vertical projection position of the peripheral area, a stress concentration area is further defined in the corner of the projected peripheral area corresponding to the projected die-placement area, and a stress extension line is further defined in the stress concentration area; and surface wiring formed on the second side of the substrate body and including conductive traces, wherein the routing direction of the conductive traces does not overlap with the stress extension line; and electronic components disposed in the die-placement area of the substrate structure.
[0009] In the aforementioned electronic package and its substrate structure, the first side of the substrate body is the crystal side for carrying electronic components, and the second side of the substrate body is the ball side for connecting multiple conductive components.
[0010] In the aforementioned electronic package and its substrate structure, the length and width of the stress concentration area are the widths of the three conductive elements, respectively.
[0011] In the aforementioned electronic package and its substrate structure, the angle between the stress extension line and one side of the adjacent projected crystal placement area is 135 degrees.
[0012] In the aforementioned electronic package and its substrate structure, the width of the conductive traces in the stress concentration area of the surface circuit is greater than the width of the conductive traces in other areas.
[0013] In the aforementioned electronic package and its substrate structure, the width of the conductive trace in the stress concentration area of the surface circuit is twice the width of the conductive trace in other areas.
[0014] In the aforementioned electronic package and its substrate structure, the substrate body includes a dielectric layer and a circuit layer bonded to the dielectric layer, and the surface circuit is electrically connected to the circuit layer.
[0015] In the aforementioned electronic package and its substrate structure, the surface circuit also includes an electrical connection pad connected to the conductive trace.
[0016] As can be seen from the above, the electronic package and its substrate structure of this application mainly ensure that the conductive traces of the surface circuits formed on the second side of the substrate body do not overlap with the stress extension lines in the stress concentration area on the second side of the substrate body, and can further widen the width of the surface circuits located in the stress concentration area to avoid surface circuit damage. Attached Figure Description
[0017] Figure 1 This is a cross-sectional schematic diagram of an existing ball grid array packaging structure.
[0018] Figure 2 This is a cross-sectional schematic diagram of the electronic package and its substrate structure according to this application.
[0019] Figure 3 This is a partial bottom view of the first embodiment of the substrate structure of this application.
[0020] Figure 4 This is a partial bottom view schematic diagram of a second embodiment of the substrate structure of this application.
[0021] Explanation of reference numerals in the attached figures
[0022] 100 package substrate
[0023] 110 Semiconductor Chips
[0024] 120 welding balls
[0025] 2a Substrate Structure
[0026] 20 substrate body
[0027] 20a First side
[0028] 20b Second side
[0029] 202 Dielectric Layer
[0030] 203 Line Layer
[0031] 21 Surface Lines
[0032] 211 Electrical connection pad
[0033] 212, 212a, 212b Conductive traces
[0034] 3 Electronic Packages
[0035] 30 Electronic components
[0036] 30a Working surface
[0037] 30b Non-operating surface
[0038] 31 Conductive bumps
[0039] 32 base rubber
[0040] 33 Conductive elements
[0041] A Crystal Placement Area
[0042] B. Outer Zone
[0043] A' Projection Crystal Placement Area
[0044] B' Projection perimeter area
[0045] C Stress Concentration Area
[0046] L-stress extension line
[0047] The angle between X and Y. Detailed Implementation
[0048] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0049] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0050] Please also refer to Figure 2 and Figure 3 ,in, Figure 2 This is a cross-sectional schematic diagram of the electronic package and its substrate structure according to this application. Figure 3 This is a partial bottom view of the substrate structure of this application.
[0051] The electronic package 3 includes a substrate structure 2a and electronic components 30 disposed on the substrate structure 2a.
[0052] The substrate structure 2a includes a substrate body 20 and surface circuitry 21 formed on the substrate body 20.
[0053] The substrate body 20 has a first side 20a and a second side 20b, wherein the first side 20a of the substrate body 20 can serve as a crystal placement side for carrying electronic components 30, and the second side 20b of the substrate body 20 can serve as a ball placement side for connecting conductive components 33.
[0054] The substrate body 20 is, for example, a packaged substrate with a core layer or a coreless packaged substrate, which includes a dielectric layer 202 and a circuit layer 203 bonded to the dielectric layer 202.
[0055] The surface layer circuit 21 is formed on the first side 20a and the second side 20b of the substrate body 20 and is electrically connected to the circuit layer 203. In this embodiment, the surface layer circuit 21 includes a plurality of interconnected electrical connection pads 211 and conductive traces 212. One end of the conductive trace 212 is connected to the electrical connection pad 211, and the other end can be connected to a conductive blind via, thereby electrically connecting to the circuit layer 203 through the conductive blind via.
[0056] The circuit layer 203 and the surface circuit 21 can be formed, for example, by a redistribution layer (RDL) fabrication method. The material forming the circuit layer 203 and the surface circuit 21 is copper, and the material forming the dielectric layer 202 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0057] The first side 20a of the substrate body 20 defines a die placement area A and a peripheral area B adjacent to the die placement area A, wherein the surface layer circuit 21 formed on the first side 20a of the substrate body 20 can span the die placement area A and the peripheral area B. The die placement area A is used to place electronic components, and the peripheral area B is disposed around the die placement area A and can be used to place passive components or heat sinks.
[0058] The second side 20b of the substrate body 20 defines a projection crystal placement area A' and a projection peripheral area B' adjacent to the projection crystal placement area A'. The projection crystal placement area A' corresponds to the vertical projection position of the crystal placement area A, and the projection peripheral area B' corresponds to the vertical projection position of the peripheral area B. The surface layer line 21 formed on the second side 20b of the substrate body 20 can span the projection crystal placement area A' and the projection peripheral area B'.
[0059] The electronic component 30 is an active component such as a semiconductor chip. In this embodiment, the electronic component 30 has an active surface 30a and a non-active surface 30b, and the active surface 30a has a plurality of electrode pads, so that the electronic component 30 is electrically connected to the electrical connection pads 211 of the surface layer circuit 21 of the first side 20a of the substrate body 20 via a plurality of conductive bumps 31 containing solder material in a flip-chip manner, and then the conductive bumps 31 are covered with a primer 32.
[0060] In addition, the electronic package 3 also includes a plurality of conductive elements 33 disposed on the substrate structure 2a (the second side 20b of the substrate body 20).
[0061] In this embodiment, the conductive element 33 is, for example, a solder ball, which is disposed on the electrical connection pad 211 of the surface line 21 on the second side 20b of the substrate body 20, so that the electronic package 3 can be electrically connected to an external device (e.g., a circuit board) through the plurality of conductive elements 33.
[0062] In addition, a stress concentration area C is defined in the corner of the projection periphery area B' of the second side 20b of the substrate body 20, corresponding to the projection crystal placement area A'. The stress concentration area C is the area where the substrate body 20 is subjected to stress during the packaging process, and its length and width are each about the width of three conductive elements 33 (solder balls).
[0063] Furthermore, a stress extension line L is further defined in the stress concentration area C. The stress extension line L is the extension direction of the stress concentration area C with greater stress. The surface circuit 21 (conductive trace 212) formed on the second side 20b of the substrate body 20 does not overlap with the stress extension line L to avoid cracking of the surface circuit 21 on the second side 20b of the substrate body 20.
[0064] In one embodiment, such as Figure 3 As shown, the angle X between the stress extension line L and one side of the adjacent projected crystal placement area A' is approximately 135 degrees, while the arrangement direction of the conductive trace 212 of the surface circuit 21 formed on the second side 20b of the substrate body 20 is approximately 90 degrees with one side of the adjacent projected crystal placement area A'. The two angles are different to avoid overlap.
[0065] In another embodiment, such as Figure 4 As shown, the width of the conductive trace 212a of the surface circuit 21 formed on the second side 20b of the substrate body 20 in the stress concentration region C is greater than the width of the conductive trace 212b in other regions. For example, the width of the conductive trace 212a of the surface circuit 21 in the stress concentration region C is about twice the width of the conductive trace 212b in other regions, so as to avoid the surface circuit 21 from cracking.
[0066] In summary, the electronic package and its substrate structure of this application mainly ensure that the conductive traces of the surface circuits formed on the second side of the substrate body do not overlap with the stress extension lines in the stress concentration area on the second side of the substrate body, and can further widen the width of the surface circuits located in the stress concentration area to avoid surface circuit damage.
[0067] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. A substrate structure, characterized in that, include: The substrate body has a first side and a second side opposite to each other. The first side defines a die-placement area and a peripheral area adjacent to the die-placement area. The second side defines a projected die-placement area and a projected peripheral area adjacent to the projected die-placement area. The projected die-placement area corresponds to a vertical projection position of the die-placement area, and the projected peripheral area corresponds to a vertical projection position of the peripheral area. A stress concentration area is further defined at a corner of the projected peripheral area corresponding to the projected die-placement area, and a stress extension line is further defined within the stress concentration area. The surface circuit is formed on the second side of the substrate body and includes conductive traces, wherein the arrangement direction of the conductive traces does not overlap with the stress extension line.
2. The substrate structure as described in claim 1, characterized in that, The first side of the substrate body is the crystal side for carrying electronic components, and the second side of the substrate body is the ball side for attaching multiple conductive components.
3. The substrate structure as described in claim 2, characterized in that, The length and width of the stress concentration zone are the widths of the three conductive elements, respectively.
4. The substrate structure as described in claim 1, characterized in that, The angle between the stress extension line and one side of the adjacent projected crystallization region is 135 degrees.
5. The substrate structure as described in claim 1, characterized in that, The width of the conductive trace in the stress concentration area of the surface circuit is greater than the width of the conductive trace in other areas.
6. The substrate structure as described in claim 1, characterized in that, The width of the conductive trace in the stress concentration area of the surface circuit is twice the width of the conductive trace in other areas.
7. The substrate structure as described in claim 1, characterized in that, The substrate body includes a dielectric layer and a circuit layer bonded to the dielectric layer, and the surface circuit is electrically connected to the circuit layer.
8. The substrate structure as described in claim 1, characterized in that, The surface circuit also includes an electrical connection pad that is connected to the conductive trace.
9. An electronic package, characterized in that, include: The substrate structure includes: The substrate body has a first side and a second side opposite to each other. The first side defines a die-placement area and a peripheral area adjacent to the die-placement area. The second side defines a projected die-placement area and a projected peripheral area adjacent to the projected die-placement area. The projected die-placement area corresponds to a vertical projection position of the die-placement area, and the projected peripheral area corresponds to a vertical projection position of the peripheral area. A stress concentration area is further defined at a corner of the projected peripheral area corresponding to the projected die-placement area, and a stress extension line is further defined in the stress concentration area. Surface wiring, formed on the second side of the substrate body and including conductive traces, wherein the arrangement direction of the conductive traces does not overlap with the stress extension line; and Electronic components are disposed in the crystal placement area of the substrate structure.
10. The electronic package as claimed in claim 9, characterized in that, The first side of the substrate body is the crystal side for carrying the electronic component, and the second side of the substrate body is the ball side for attaching multiple conductive components.
11. The electronic package as claimed in claim 10, characterized in that, The length and width of the stress concentration zone are the widths of the three conductive elements, respectively.
12. The electronic package as claimed in claim 9, characterized in that, The angle between the stress extension line and one side of the adjacent projected crystallization region is 135 degrees.
13. The electronic package as claimed in claim 9, characterized in that, The width of the conductive trace in the stress concentration area of the surface circuit is greater than the width of the conductive trace in other areas.
14. The electronic package as claimed in claim 9, characterized in that, The width of the conductive trace in the stress concentration area of the surface circuit is twice the width of the conductive trace in other areas.
15. The electronic package as claimed in claim 9, characterized in that, The substrate body includes a dielectric layer and a circuit layer bonded to the dielectric layer, and the surface circuit is electrically connected to the circuit layer.
16. The electronic package as claimed in claim 9, characterized in that, The surface circuit also includes an electrical connection pad that is connected to the conductive trace.