Integrated circuit

Abstract

The utility model provides an integrated circuit. The integrated circuit comprises a semiconductor substrate and an interconnection structure. The interconnect structure is disposed on the semiconductor substrate. The interconnection structure includes a signal transmission structure and a heat dissipation structure. The heat dissipation structure is disposed on the signal transmission structure and includes a composite dielectric layer and a first conductive feature. Each composite dielectric layer includes a seed layer and a heat dissipation layer disposed on the seed layer. The first conductive feature is embedded in the composite dielectric layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present utility model relate to an integrated circuit. More particularly, embodiments of the present utility model relate to an integrated circuit with a heat dissipation structure. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each having greater complexity than the one before it. These generations of ICs have generally included relatively smaller feature sizes (i.e., the smallest component (or line) that can be created using a process) and greater functionality and complexity. As the semiconductor industry has progressed, the dimensions of circuit features have continually decreased while the complexity of the features to be created has continuously increased. This drive for increased functionality and complexity in ICs has resulted in the evolution of design and fabrication processes used to create ICs. SUMMARY

[0003] An integrated circuit includes a semiconductor substrate and an interconnect structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes a signal transmission structure and a heat dissipation structure. The heat dissipation structure is disposed on the signal transmission structure and includes a composite dielectric layer and a first conductive feature. Each of the composite dielectric layers includes a seed layer and a heat dissipation layer disposed on the seed layer. The first conductive feature is embedded in the composite dielectric layer.

[0004] An integrated circuit includes a first circuit component, a second circuit component, a bonding layer, and a via. The first circuit component includes a first semiconductor substrate and a first interconnect structure disposed on the first semiconductor substrate. The first interconnect structure includes first dielectric layers, first seed layers, and first diamond layers. The first dielectric layers are stacked on one another. The first seed layers and the first diamond layers are alternately stacked on one another on the first dielectric layers. The second circuit component includes a second semiconductor substrate and a second interconnect structure disposed on the second semiconductor substrate. The second interconnect structure includes second dielectric layers, second seed layers, and second diamond layers. The second dielectric layers are stacked on one another. The second seed layers and the second diamond layers are alternately stacked on one another on the second dielectric layers. The bonding layer is interposed between the first circuit component and the second circuit component. The via passes through the second circuit component, the bonding layer, the first seed layers, and the first diamond layers. BRIEF DESCRIPTION OF DRAWINGS

[0005] The embodiments of the disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It is to be noted, however, that the description proceeds with detailed examples for the purpose of making a disclosure of the principles and conceptual aspects of the present disclosure. It will be apparent that the embodiments of the disclosure can be practiced differently and can be implemented in various components, regardless of the type of system in which they are incorporated. It is to be noted that the various features of the disclosure are not necessarily in all combinations, and that they can be combined in other ways, by one of ordinary skill in the art, to achieve the objects of the present disclosure. The scope of the present disclosure is not to be understood as being limited to the illustrated and described embodiments.

[0006] Figures 1A-1L is a schematic cross-sectional view of a manufacturing flow of an integrated circuit according to some embodiments of the present disclosure.

[0007] Figures 2A-2E is a schematic cross-sectional view of a manufacturing flow of an integrated circuit according to some alternative embodiments of the present disclosure.

[0008] Figure 3 is a schematic cross-sectional view of a manufacturing flow of an integrated circuit according to some alternative embodiments of the present disclosure.

[0009] Figures 4A-4E is a schematic cross-sectional view of a manufacturing flow of an integrated circuit according to some alternative embodiments of the present disclosure. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features, such that the first and second features can not be in direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0011] Also for ease of explanation, spatial relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein to describe the orientation of one element or feature to another element or feature, as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0012] Other features and processes can also be included. For example, test structures can be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. The test structures can include, for example, test pads formed in a redistribution layer or on a substrate to enable testing of 3D packages or 3DICs, use of probes and / or probe cards, and the like. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with testing methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0013] Figures 1A-1L is a schematic cross-sectional view of a manufacturing flow of an integrated circuit 10 according to some embodiments of the present disclosure. Referring to Figure 1A , a semiconductor substrate 100 is provided. In some embodiments, semiconductor substrate 100 is made of an elemental semiconductor material, such as crystalline silicon, diamond (carbon), or germanium; a compound semiconductor material, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or an alloy semiconductor material, such as silicon germanium, silicon carbide germanium, gallium arsenide phosphide, or gallium indium phosphide. Semiconductor substrate 100 can be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0014] As shown in Figure 1A , a plurality of transistors 200 are formed on semiconductor substrate 100. In some embodiments, each transistor 200 includes a source / drain region 202 and a gate 204. In some embodiments, each transistor 200 further includes a channel region (not shown) under gate 204. In some embodiments, a channel region is also located between source / drain regions 202 to serve as a path for electrons to travel when transistor 200 is turned on.

[0015] In some embodiments, semiconductor substrate 100 includes various doped regions depending on circuit requirements (e.g., p-type semiconductor substrate or n-type semiconductor substrate). In some embodiments, the doped regions are doped with p-type or n-type dopants. For example, p-type dopants (e.g., boron or BF 2)The doped regions are doped with n-type dopants (e.g., phosphorus or arsenic) and / or combinations thereof. In some embodiments, these doped regions serve as the source / drain regions of transistor 200. Depending on the type of dopant in the doped regions, transistor 200 may be referred to as an n-type transistor or a p-type transistor.

[0016] In some embodiments, gate 204 comprises copper, titanium, tantalum, tungsten, aluminum, zirconium, hafnium, cobalt, titanium aluminum, tantalum aluminum, tungsten aluminum, zirconium aluminum, hafnium aluminum, titanium nitride, other suitable metallic materials, or combinations thereof. In some embodiments, gate 204 further comprises a material for fine-tuning the corresponding work function. For example, gate 204 may also comprise a p-type work function material (e.g., Ru, Mo, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or combinations thereof) or an n-type work function material (e.g., Ag, TaCN, Mn, or combinations thereof).

[0017] like Figure 1A As shown, the source / drain region 202 is embedded in the semiconductor substrate 100, and the gate 204 is located above the semiconductor substrate 100. However, this disclosure is not limited thereto. In some alternative embodiments, both the source / drain region 202 and the gate 204 are located above the semiconductor substrate 100. In some embodiments, the transistors 200 may be separated by shallow trench isolation (STI, not shown) between two adjacent transistors 200. In some embodiments, the transistors 200 are formed using a suitable front-end-of-line (FEOL) process.

[0018] Reference Figure 1BA signal transmission structure 300 is formed on a semiconductor substrate 100 and a transistor 200. In some embodiments, the signal transmission structure 300 includes a plurality of dielectric layers 310 and a plurality of conductive features 320. In some embodiments, the dielectric layers 310 are stacked on top of each other. For example, adjacent dielectric layers 310 are in physical contact with each other. In some embodiments, the material of the dielectric layers 310 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. Alternatively, the dielectric layers 310 may be formed of oxides or nitrides such as silicon oxide, silicon nitride, hafnium oxide, hafnium zirconium oxide, or similar materials. In some embodiments, different dielectric layers 310 are formed of the same material. However, this disclosure is not limited thereto. In some alternative embodiments, different dielectric layers 310 may be formed of different materials. The dielectric layer 310 can be formed using suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or similar techniques. In some embodiments, the number of dielectric layers 310 is four or more.

[0019] In some embodiments, the conductive feature 320 includes a plurality of vias 322 and a plurality of conductive patterns 324. For example... Figure 1B As shown, conductive feature 320 is embedded in dielectric layer 310. That is, via 322 and conductive pattern 324 are embedded in dielectric layer 310. For example, dielectric layer 310 laterally encloses via 322 and conductive pattern 324. In some embodiments, conductive pattern 324 extends horizontally. Meanwhile, via 322 extends vertically to connect conductive patterns 324 located at different horizontal heights. In other words, conductive patterns 324 are electrically connected to each other through via 322. In some embodiments, bottom via 322 is connected to transistor 200. For example, bottom via 322 is connected to source / drain region 202 and gate 204 of transistor 200. In other words, bottom via 322 establishes an electrical connection between transistor 200 and conductive pattern 324. That is, conductive feature 320 is electrically connected to transistor 200. In some embodiments, bottom via 322 may be referred to as "contact structure" of transistor 200.

[0020] In some embodiments, the conductive pattern 324 and the via 322 are made of aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The conductive pattern 324 and the via 322 can be formed by electroplating, deposition, and / or photolithography and etching. In some embodiments, the conductive pattern 324 and the underlying via 322 are formed separately. However, this disclosure is not limited thereto. In some alternative embodiments, the conductive pattern 324 and the underlying via 322 can be formed simultaneously. Figure 1B As shown, the via 322 and the underlying conductive pattern 324 are embedded in the same dielectric layer 310. In other words, the top surface of each via 322 is coplanar with the top surface of the corresponding dielectric layer 310. Simultaneously, the top surface of each conductive pattern 324 is located at a lower horizontal height than the top surface of the corresponding dielectric layer 310. That is, the top surface of the conductive pattern 324 is covered by the dielectric layer 310.

[0021] Reference Figure 1B as well as Figure 1C The top dielectric layer 310 is planarized until the top conductive pattern 324 is exposed. In other words, after the planarization process, the top surface T of the top conductive pattern 324 is exposed. 324 With the top surface T of the top dielectric layer 310 310 Coplanar. In some embodiments, the planarization process makes the top surface T of the topmost conductive pattern 324 coplanar. 324 Surface roughness and the top surface T of the top dielectric layer 310 310 The surface roughness is reduced to less than 1 nm. In some embodiments, the planarization process includes mechanical grinding, chemical mechanical polishing (CMP), etc.

[0022] Reference Figure 1D A seed layer 412a is deposited on the signal transmission structure 300. For example, the seed layer 412a is formed on the topmost dielectric layer 310 and the topmost conductive pattern 324. Figure 1D As shown, the seed layer 412a and the top surface T of the top dielectric layer 310 310 And the top surface T of the topmost conductive pattern 324 324 Physical contact. As described above, the top surface T of the topmost conductive pattern 324 324 Surface roughness and the top surface T of the top dielectric layer 310 310The surface roughness is less than 1 nm. Therefore, the seed layer 412a is deposited on a substantially flat surface. In some embodiments, the seed layer 412a is made of a dielectric material. However, the material of the seed layer 412a is different from the material of the dielectric layer 310. In some embodiments, the seed layer 412a is made of a material that matches the diamond lattice. For example, the material of the seed layer 412a includes cubic boron nitride (c-BN), etc. In some embodiments, the seed layer 412a is deposited on the signal transmission structure 300 through CVD, physical vapor deposition (PVD), etc. In some embodiments, the seed layer 412a is formed to have a thickness in the range of about 10 nm to about 50 nm. As mentioned above, the material of the seed layer 412a is different from the material of the dielectric layer 310. Therefore, there is an interface between the seed layer 412a and the topmost dielectric layer 310, such as Figure 1D As shown.

[0023] Reference Figure 1E After forming a seed layer 412a on the signal transmission structure 300, a diamond layer 414a is grown on the seed layer 412a. In some embodiments, the material of the diamond layer 414a is different from the material of the dielectric layer 310. For example, the material of the diamond layer 414a includes diamond. In some embodiments, the diamond layer 414a is formed on the seed layer 412a by CVD, microwave plasma chemical vapor deposition (MPCVD), etc. In some embodiments, the process temperature for growing the diamond layer 414a is 400°C or lower. In some embodiments, since the lattice of the material of the seed layer 412a (i.e., cubic boron nitride) matches the lattice of the material of the diamond layer 414a (i.e., diamond), the diamond layer 414a can be effectively epitaxially grown on the seed layer 412a at low temperatures. In some embodiments, the diamond layer 414a is formed to have a thickness in the range of about 100 nm to about 5,000 nm. In some embodiments, after forming a diamond layer 414a on the seed layer 412a, a planarization process is performed on the diamond layer 414a. In some embodiments, the planarization process includes a mechanical polishing process, a CMP process, etc. After the planarization process, the diamond layer 414a has a substantially flat top surface. It is worth noting that the planarization process here may be optional and may be omitted in some embodiments.

[0024] In some embodiments, since both the seed layer 412a and the diamond layer 414a are made of dielectric material, the seed layer 412a and the diamond layer 414a can be collectively referred to as the composite dielectric layer 410a. That is, the composite dielectric layer 410a is grown on the topmost dielectric layer 310 and the topmost conductive pattern 324.

[0025] Through execution Figures 1D-1E The steps shown allow for easy growth of a composite dielectric layer 410a on the signal transmission structure 300. In some embodiments, the signal transmission structure 300 and the composite dielectric layer 410a are considered to be formed during a back-end-of-line (BEOL) process. Traditionally, the thermal budget (process temperature window) of the BEOL process is low. As described above, by first depositing a seed layer 412a on the signal transmission structure 300 and then growing a diamond layer 414a on the seed layer 412a, the process temperature for forming the composite dielectric layer 410a can be lower (i.e., 400°C or lower) and fall within the thermal budget of the BEOL process. In other words, by employing the seed layer 412a, the diamond layer 414a can be integrated into the subsequently formed integrated circuit 10 while remaining compatible with the BEOL thermal budget.

[0026] Reference Figure 1E as well as Figure 1F The seed layer 412a and the diamond layer 414a are patterned to form a plurality of openings OP1 in the seed layer 412a and the diamond layer 414a. That is, the openings OP1 are formed in the composite dielectric layer 410a. In some embodiments, the openings OP1 penetrate the composite dielectric layer 410a. For example, the openings OP1 penetrate the seed layer 412a and the diamond layer 414a to partially expose the underlying conductive pattern 324. That is, the openings OP1 partially expose the topmost conductive pattern 324. In some embodiments, the patterning process of the seed layer 412a and the diamond layer 414a includes a photolithography process and an etching process. The etching process includes a dry etching process. For example, the seed layer 412a and the diamond layer 414a can be patterned by reactive ion etching (RIE), inductively coupled plasma (ICP) etching, electron cyclotron resonance (ECR) etching, neutral beam etching (NBE), etc. In some embodiments, oxygen can be used as the etching gas during the dry etching process.

[0027] Reference Figure 1GConductive material (not shown) is deposited in the opening OP1 to form a plurality of vias 422. For example, the conductive material is conformally formed on the composite dielectric layer 410a. In some embodiments, the conductive material also fills the opening OP1. In some embodiments, the conductive material includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. In some embodiments, the conductive material is deposited into the opening OP1 by means of PVD, ion beam deposition (IBD), CVD, ALD, molecular beam epitaxy (MBE), electro-chemical plating (ECP), electroless deposition (ELD), etc. Then, the conductive material is planarized until the diamond layer 414a is exposed to form vias 422 in the opening OP1. In some embodiments, the planarization process includes mechanical polishing, CMP, etc. After the planarization process, the top surface T of the via 422 is planarized. 422 With the top surface T of diamond layer 414a 414a Coplanar. In other words, the composite dielectric layer 410a laterally encloses the via 422 and exposes the top surface T of the via 422. 422 In some embodiments, the planarization process flattens the top surface T of the via 422. 422 Surface roughness and the top surface T of diamond layer 414a 414a The surface roughness is reduced to less than 1 nm.

[0028] Reference Figure 1H A composite dielectric layer 410b is formed on the composite dielectric layer 410a and the via 422. In some embodiments, the composite dielectric layer 410b includes a seed layer 412b and a diamond layer 414b disposed on the seed layer 412b. Figure 1H The seed layer 412b and the diamond layer 414b in the middle are respectively with Figure 1E The seed layer 412a and diamond layer 414a are similar, so their detailed description is omitted here. In some embodiments, they can be obtained through a similar Figures 1D-1E The steps shown form a composite dielectric layer 410b on the composite dielectric layer 410a and the via 422.

[0029] Reference Figure 1H as well as Figure 1IThe seed layer 412b and the diamond layer 414b are patterned to form a plurality of openings OP2 in the seed layer 412b and the diamond layer 414b. That is, the openings OP2 are formed in the composite dielectric layer 410b. In some embodiments, the openings OP2 penetrate the composite dielectric layer 410b. For example, the openings OP2 penetrate the seed layer 412b and the diamond layer 414b to expose the underlying via 422. In some embodiments, the openings OP2 also partially expose the underlying composite dielectric layer 410a. In some embodiments, the patterning process of the seed layer 412b and the diamond layer 414b includes a photolithography process and an etching process. The etching process includes a dry etching process. For example, the seed layer 412b and the diamond layer 414b can be patterned by RIE, ICP etching, ECR etching, NBE, etc. In some embodiments, oxygen can be used as the etching gas during the dry etching process.

[0030] Reference Figure 1J Conductive material (not shown) is deposited in the opening OP2 to form multiple conductive patterns 424. For example, the conductive material is conformally formed on the composite dielectric layer 410b. In some embodiments, the conductive material also fills the opening OP2. In some embodiments, the conductive material includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. In some embodiments, the conductive material is deposited on the composite dielectric layer 410b and in the opening OP2 via PVD, IBD, CVD, ALD, MBE, ECP, ELD, etc. Subsequently, the conductive material is planarized until the diamond layer 414b is exposed to form conductive patterns 424 in the opening OP2. In some embodiments, the planarization process includes mechanical polishing, CMP, etc. After the planarization process, the top surface T of the conductive pattern 424 is... 424 Top surface T of diamond layer 414b 414b Coplanar. In other words, the composite dielectric layer 410b laterally encapsulates the conductive pattern 424 and exposes the top surface T of the conductive pattern 424. 424 In some embodiments, the planarization process flattens the top surface T of the conductive pattern 424. 424 Surface roughness and the top surface T of diamond layer 414b 414b The surface roughness is reduced to less than 1 nm.

[0031] like Figure 1J As shown, each conductive pattern 424 passes through a composite dielectric layer (i.e., composite dielectric layer 410b), while each via 422 passes through another composite dielectric layer (i.e., composite dielectric layer 410a). For example, each conductive pattern 424 passes through a seed layer (i.e., seed layer 412b) and a diamond layer (i.e., diamond layer 414b), while each via 422 passes through another seed layer (i.e., seed layer 412a) and another diamond layer (i.e., diamond layer 414a).

[0032] Reference Figure 1K ,Will Figures 1D-1J The steps shown are repeated multiple times to form a heat dissipation structure 400 on the signal transmission structure 300. In some embodiments, the heat dissipation structure 400 includes a plurality of composite dielectric layers 410a, 410b, 410c, 410d, 410e and a plurality of conductive features 420. In some embodiments, the composite dielectric layers 410a, 410b, 410c, 410d, 410e are stacked on top of each other. For example, adjacent composite dielectric layers 410a, 410b, 410c, 410d, 410e are in physical contact with each other. In some embodiments, composite dielectric layer 410c includes a seed layer 412c and a diamond layer 414c disposed on the seed layer 412c, composite dielectric layer 410d includes a seed layer 412d and a diamond layer 414d disposed on the seed layer 412d, and composite dielectric layer 410e includes a seed layer 412e and a diamond layer 414e disposed on the seed layer 412e. Figure 1K The seed layers 412c, 412d, and 412e and the diamond layers 414c, 414d, and 414e are respectively with Figure 1E The seed layer 412a and the diamond layer 414a are similar, so a detailed description of them is omitted here. Figure 1K As shown, seed layers 412a, 412b, 412c, 412d, 412e and diamond layers 414a, 414b, 414c, 414d, 414e are alternately stacked on top of dielectric layer 310.

[0033] In some embodiments, the conductive feature 420 includes a via 422 and a conductive pattern 424. In some embodiments, the conductive feature 420 is embedded in composite dielectric layers 410a, 410b, 410c, 410d, and 410e. Figure 1KAs shown, the via 422 is embedded in the composite dielectric layer 410a, 410c, 410e. On the other hand, the conductive pattern 424 is embedded in the composite dielectric layer 410b, 410d. For example, the via 422 is embedded in the seed layer 412a, 412c, 412e and the diamond layer 414a, 414c, 414e, while the conductive pattern 424 is embedded in the seed layer 412b, 412d and the diamond layer 414b, 414d. In some embodiments, the conductive pattern 424 extends horizontally. Meanwhile, the via 422 extends vertically to connect the conductive pattern 424 at different horizontal levels. In other words, the conductive patterns 424 are electrically connected to each other through the via 422. In some embodiments, the via 422 and the conductive pattern 424 penetrate through different composite dielectric layers 410a, 410b, 410c, 410d, 410e. For example, the via 422 penetrates through the corresponding composite dielectric layer 410a, 410c, 410e, while the conductive pattern 424 penetrates through the corresponding composite dielectric layer 410b, 410d. As shown, the top surface of each diamond layer 414a, 414b, 414c, 414d, 414e is coplanar with the top surface of the corresponding conductive feature 420. Meanwhile, the top surface of each seed layer 412a, 412b, 412c, 412d, 412e is at a lower horizontal level than the top surface of the corresponding conductive feature 420. Figure 1K

[0034] In some embodiments, since the diamond layer 414a, 414b, 414c, 414d, 414e is made of diamond, the thermal conductivity of the diamond layer 414a, 414b, 414c, 414d, 414e is high. For example, the thermal conductivity of the diamond layer 414a, 414b, 414c, 414d, 414e is 200 W / (m-K) or higher. Accordingly, heat generated during the operation of the subsequently formed integrated circuit 10 can be sufficiently dissipated by the diamond layer 414a, 414b, 414c, 414d, 414e. Thus, in some embodiments, the diamond layer 414a, 414b, 414c, 414d, 414e can be referred to as a heat dissipation layer. By incorporating these heat dissipation layers (i.e., the diamond layer 414a, 414b, 414c, 414d, 414e), the performance and the lifetime of the subsequently formed integrated circuit 10 can be substantially improved.

[0035] ​In some embodiments, the heat dissipation structure 400 is in physical contact with the signal transmission structure 300. For example, the topmost dielectric layer 310 of the signal transmission structure 300 is in physical contact with the bottommost seed layer (i.e., seed layer 412a) of the heat dissipation structure 400. Simultaneously, the bottommost conductive feature 420 (i.e., the bottommost via 422) of the heat dissipation structure 400 is in physical contact with the topmost conductive feature 320 (i.e., the topmost conductive pattern 324) of the signal transmission structure 300. In other words, the conductive feature 420 of the heat dissipation structure 400 is electrically connected to the conductive feature 320 of the signal transmission structure 300. For example, the via 322, the conductive pattern 324, the via 422, and the conductive pattern 424 are electrically connected to each other. In some embodiments, the conductive feature 420 is electrically connected to the transistor 200 through the conductive feature 320.

[0036] Since the conductive feature 420 of the heat dissipation structure 400 is electrically connected to the conductive feature 320 of the signal transmission structure 300, the heat dissipation structure 400 also has the function of signal transmission in addition to heat dissipation.

[0037] In some embodiments, the signal transmission structure 300 and the heat dissipation structure 400 are collectively referred to as the interconnect structure INT. That is, the interconnect structure INT is disposed on the semiconductor substrate 100. For example... Figure 1K As shown, transistor 200 is partially embedded in the interconnect structure INT. For example, the gate 204 of transistor 200 is embedded in the signal transmission structure 300 of the interconnect structure INT.

[0038] It is worth noting that, Figure 1K The number of composite dielectric layers 410a, 410b, 410c, 410d, 410e, vias 422, and conductive patterns 424 shown are for illustrative purposes only, and this disclosure is not limited thereto. In some alternative embodiments, depending on the circuit design, fewer or more layers of composite dielectric layers 410a, 410b, 410c, 410d, 410e, vias 422, and conductive patterns 424 may be formed.

[0039] Reference Figure 1L Multiple under-bump metallurgy (UBM) patterns 500 are formed on the heat dissipation structure 400. For example, the UBM patterns 500 are formed on the composite dielectric layer 410e and the topmost via 422. In some embodiments, the UBM patterns 500 are in physical contact with the topmost via 422 to achieve electrical connection with the interconnect structure INT. In some embodiments, the UBM patterns 500 are formed through sputtering, PVD, electroplating, or other processes. In some embodiments, the UBM patterns 500 are made of aluminum, titanium, copper, tungsten, and / or their alloys.

[0040] After the UBM pattern 500 is formed on the heat dissipation structure 400, a plurality of conductive terminals 600 are configured on the UBM pattern 500. In some embodiments, the conductive terminals 600 are attached to the UBM pattern 500 through flux. In some embodiments, the conductive terminals 600 are, for example, solder balls, ball grid array (BGA) balls, or controlled collapse chip connection (C4) bumps. In some embodiments, the conductive terminals 600 are made of a low-resistivity conductive material, such as Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof.

[0041] After that, a singulation process is performed on the heat dissipation structure 400, the signal transmission structure 300, and the semiconductor substrate 100 to obtain a plurality of integrated circuits 10. In some embodiments, the singulation process generally involves cutting using a rotating blade and / or a laser beam. In other words, the singulation process includes a laser cutting process, a mechanical cutting process, a laser grooving process, other suitable processes, or a combination thereof.

[0042] Figures 2A-2E is a schematic cross-sectional view of a manufacturing flow of an integrated circuit 20 according to some alternative embodiments of the present disclosure. Referring to Figure 2A , a circuit component CS1 is provided. In some embodiments, the circuit component CS1 is similar to the structure shown in Figure 1K , thus similar components are denoted by the same reference numerals, and detailed description thereof is omitted here. In some embodiments, the circuit component CS1 is formed by performing the steps shown in Figures 1A-1K . It is noted that, in some embodiments, the topmost via 422 embedded in the composite dielectric layer 410e is optional and can be omitted. That is, in some embodiments, the composite dielectric layer 410e is a continuous layer and does not have any conductive features embedded therein.

[0043] Referring to Figure 2BA bonding layer 700 is formed on the circuit assembly CS1. For example, the bonding layer 700 is formed on the heat dissipation structure 400. In some embodiments, the bonding layer 700 is in physical contact with the topmost composite dielectric layer (i.e., composite dielectric layer 410e) and the topmost conductive feature 420 (i.e., topmost via 422). For example, the bonding layer 700 is in physical contact with the topmost diamond layer (i.e., diamond layer 414e) and the topmost conductive feature 420 (i.e., topmost via 422). In some embodiments, the material of the bonding layer 700 includes a metal oxide or a metal nitride. For example, the material of the bonding layer 700 includes aluminum oxide or aluminum nitride. However, this disclosure is not limited thereto. In some alternative embodiments, other materials with adhesive properties may also be used as the material of the bonding layer 700. In some embodiments, the bonding layer 700 is formed by a suitable manufacturing technique such as spin coating, CVD, PECVD, etc. In some embodiments, after the bonding layer 700 is formed on the circuit assembly CS1, the bonding layer 700 is subjected to a planarization process to reduce its surface roughness.

[0044] Reference Figure 2C A circuit component CS2 is provided. In some embodiments, the circuit component CS2 is coupled with... Figure 2A The circuit component CS1 is similar to that in the circuit component CS1. In some embodiments, the circuit component CS2 includes a semiconductor substrate 100', a plurality of transistors 200', and an interconnect structure INT'. In some embodiments, the semiconductor substrate 100' of the circuit component CS2 is similar to the semiconductor substrate 100 of the circuit component CS1, and therefore will not be described again here. Each transistor 200' includes a source / drain region 202' and a gate 204'. In some embodiments, the transistors 200', source / drain regions 202', and gate 204' of the circuit component CS2 are similar to those of the transistors 200, source / drain regions 202, and gate 204 of the circuit component CS1, respectively, and therefore will not be described again here. Figure 2CAs shown, the interconnect structure INT' includes a signal transmission structure 300' and a heat dissipation structure 400'. The signal transmission structure 300' includes multiple dielectric layers 310' and multiple conductive features 320'. The conductive features 320' include multiple vias 322' and multiple conductive patterns 324'. The vias 322' and conductive patterns 324' of circuit component CS2 are similar to those of circuit component CS1, and therefore will not be described in detail here. The heat dissipation structure 400' includes multiple composite dielectric layers 410a', 410b', 410c', 410d', 410e' and multiple conductive features 420'. The composite dielectric layer 410a' includes a seed layer 412a' and a diamond layer 414a', the composite dielectric layer 410b' includes a seed layer 412b' and a diamond layer 414b', the composite dielectric layer 410c' includes a seed layer 412c' and a diamond layer 414c', the composite dielectric layer 410d' includes a seed layer 412d' and a diamond layer 414d', and the composite dielectric layer 410e' includes a seed layer 412e' and a diamond layer 414e'. The conductive feature 420' includes a plurality of vias 422' and a plurality of conductive patterns 424'. The seed layers 412a', 412b', 412c', 412d', 412e', diamond layers 414a', 414b', 414c', 414d', 414e', vias 422', and conductive patterns 424' of circuit component CS2 are similar to those of circuit component CS1, and therefore their detailed descriptions are omitted here.

[0045] like Figure 2C As shown, circuit component CS2 is placed on and bonded to circuit component CS1. In some embodiments, circuit component CS2 is attached to circuit component CS1 through bonding layer 700. That is, bonding layer 700 is sandwiched between circuit component CS1 and circuit component CS2. Figure 2C As shown, the bonding layer 700 is in physical contact with the diamond layer 414e of the circuit assembly CS1 and the semiconductor substrate 100' of the circuit assembly CS2.

[0046] In some embodiments, before attaching the circuit component CS2 to the circuit component CS1, the circuit component CS2 can be placed on a carrier board (not shown). Thereafter, the semiconductor substrate 100' of the circuit component CS2 can be thinned to reduce the overall thickness of the circuit component CS2. The thinning process includes a mechanical grinding process, a CMP process, etc. After the semiconductor substrate 100' of the circuit component CS2 is thinned, the circuit component CS2 is placed on the bonding layer 700 to be bonded with the circuit component CS1. In some embodiments, the bonding between the circuit component CS1 and the circuit component CS2 is referred to as face-to-face bonding.

[0047] Referring to Figure 2D , a plurality of vias 800 are formed. In some embodiments, the material of the vias 800 includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The vias 800 can be formed by electroplating, deposition, and / or photolithography and etching. As shown, the vias 800 penetrate the circuit component CS2, the bonding layer 700, the diamond layers 414e, 414d, 414c, 414b, 414a, and the seed layers 412e, 412d, 412c, 412b, 412a to be in physical contact with the topmost conductive pattern 324. In other words, the vias 800 are electrically connected with the signal transmission structure 300 of the circuit component CS1. Figure 2D

[0048] Referring to Figure 2E , a plurality of UBM patterns 500 are formed on the heat dissipation structure 400' and the vias 800. For example, the UBM patterns 500 are formed on the composite dielectric layer 410e', the topmost via hole 422', and the vias 800. In some embodiments, the UBM patterns 500 in the composite dielectric layer 410e' are similar to the UBM patterns 500 in the composite dielectric layer 410e, and thus the detailed description thereof is omitted here. In some embodiments, the UBM patterns 500 are in physical contact with the topmost via hole 422' to achieve electrical connection with the interconnect structure INT' of the circuit component CS2. Meanwhile, the UBM patterns 500 are also in physical contact with the vias 800 to achieve electrical connection with the interconnect structure INT of the circuit component CS1. Figure 2E Figure 1L

[0049] As shown, a plurality of conductive terminals 600 are configured on the UBM patterns 500. Figure 2E Figure 2E The conductive terminals 600 in the composite dielectric layer 410e' are similar to the conductive terminals 600 in the composite dielectric layer 410e, and thus the detailed description thereof is omitted here. In some embodiments, the conductive terminals 600 are in physical contact with the topmost via hole 422' to achieve electrical connection with the interconnect structure INT' of the circuit component CS2. Meanwhile, the conductive terminals 600 are also in physical contact with the vias 800 to achieve electrical connection with the interconnect structure INT of the circuit component CS1. Figure 1L ​​​​The conductive terminals 600 in the integrated circuit 20 are similar to the conductive terminals 600 in the integrated circuit 10, and thus similar components are denoted by the same reference numerals, and detailed descriptions thereof are omitted herein.

[0050] In some embodiments, the composite dielectric layers 410a, 410a', 410b, 410b', 410c, 410c', 410d, 410d', 410e, 410e' can be formed by similar steps as shown in FIGS. 6A-6E. Thus, by first depositing seed layers (i.e., the seed layers 412a, 412a', 412b, 412b', 412c, 412c', 412d, 412d', 412e, 412e') on the signal transmission structure 300, 300' and subsequently growing diamond layers (i.e., the diamond layers 414a, 414a', 414b, 414b', 414c, 414c', 414d, 414d', 414e, 414e') on the seed layers, the diamond layers can be integrated into the integrated circuit 20 under the premise of being compatible with the thermal budget of the BEOL. Moreover, by introducing the heat dissipation layers (i.e., the diamond layers 414a, 414a', 414b, 414b', 414c, 414c', 414d, 414d', 414e, 414e'), the performance and lifetime of the integrated circuit 20 can be substantially improved. Figures 1D-1E

[0051] Figure 3 FIG. 1 is a schematic cross-sectional view of an integrated circuit 10 according to some alternative embodiments of the present disclosure. Referring to FIG. 1, the integrated circuit 10 includes a semiconductor substrate 100, a signal transmission structure 300, a heat dissipation structure 400, and a plurality of conductive terminals 600. The semiconductor substrate 100 includes a plurality of semiconductor devices 110. The signal transmission structure 300 includes a plurality of signal transmission lines 310. The heat dissipation structure 400 includes a plurality of heat dissipation layers 420. The conductive terminals 600 are electrically connected to the semiconductor devices 110 and the signal transmission lines 310. Figure 3 Figure 3 The integrated circuit 30 in FIG. 3 is similar to the integrated circuit 10 in FIG. 1, and thus similar components are denoted by the same reference numerals, and detailed descriptions thereof are omitted herein. Figure 1L The integrated circuit 30 in FIG. 3 is similar to the integrated circuit 10 in FIG. 1, and thus similar components are denoted by the same reference numerals, and detailed descriptions thereof are omitted herein. Figure 3 The integrated circuit 30 in FIG. 3 is similar to the integrated circuit 10 in FIG. 1, and thus similar components are denoted by the same reference numerals, and detailed descriptions thereof are omitted herein. Figure 1L The integrated circuit 30 in FIG. 3 is similar to the integrated circuit 10 in FIG. 1, and thus similar components are denoted by the same reference numerals, and detailed descriptions thereof are omitted herein. Figure 3 The integrated circuit 30 in FIG. 3 is similar to the integrated circuit 10 in FIG. 1, and thus similar components are denoted by the same reference numerals, and detailed descriptions thereof are omitted herein. Figure 3 The seed layers 412 and the diamond layers 414 in FIG. 3 are similar to the seed layers 412 and the diamond layers 414 in FIG. 2, respectively, and thus similar components are denoted by the same reference numerals, and detailed descriptions thereof are omitted herein. Figure 1E ​​The seed layer 412a and diamond layer 414a are similar, so they will not be described in detail here. Meanwhile, Figure 3 The through hole 422 and Figure 1G The via 422 is similar, so it will not be described in detail here.

[0052] In some embodiments, it can be achieved through similar means Figures 1D-1E The steps shown form a composite dielectric layer 410 on the signal transmission structure 300. Therefore, by first depositing a seed layer 412 on the signal transmission structure 300 and then growing a diamond layer 414 on the seed layer 412, the diamond layer 414 can be integrated into the integrated circuit 30 while maintaining thermal budget compatibility with BEOL. Furthermore, by introducing a heat dissipation layer (i.e., the diamond layer 414), the performance and lifespan of the integrated circuit 30 can be significantly improved.

[0053] Figures 4A-4E This is a schematic cross-sectional view of the manufacturing process of an integrated circuit 40 according to some alternative embodiments of this disclosure. (Refer to...) Figure 4A A circuit component CS3 is provided. In some embodiments, the circuit component CS3 is connected to... Figure 3 The integrated circuit 30 shown is similar; therefore, similar components are indicated by the same reference numerals, and their detailed descriptions are omitted here. However, Figure 3 The UBM pattern 500 and conductive terminals 600 of the integrated circuit 30 are in Figure 4A The circuit component CS3 is omitted. It is worth noting that in some embodiments, the via 422 embedded in the composite dielectric layer 410 is optional and can be omitted. That is, in some embodiments, the composite dielectric layer 410 is a continuous layer and no conductive features are embedded therein.

[0054] Reference Figure 4B A bonding layer 700 is formed on the circuit component CS3. For example, the bonding layer 700 is formed on the heat dissipation structure 400. In some embodiments, Figure 4B In the bonding layer 700 and Figure 2B The bonding layer 700 is similar to that in the circuit assembly CS3, so its detailed description is omitted here. In some embodiments, the bonding layer 700 is in physical contact with the composite dielectric layer 410 and the conductive feature 420 (i.e., the via 422). For example, the bonding layer 700 is in physical contact with the diamond layer 414 and the via 422. In some embodiments, after the bonding layer 700 is formed on the circuit assembly CS3, the bonding layer 700 is planarized to reduce its surface roughness.

[0055] Reference Figure 4C A circuit component CS4 is provided. In some embodiments, the circuit component CS4 is connected to... Figure 4AThe circuit component CS4 is similar to the circuit component CS3. In some embodiments, the circuit component CS4 includes a semiconductor substrate 100', a plurality of transistors 200', and an interconnect structure INT'. In some embodiments, the semiconductor substrate 100' of the circuit component CS4 is similar to the semiconductor substrate 100 of the circuit component CS3, and is not described again here. Each transistor 200' includes a source / drain region 202' and a gate 204'. In some embodiments, the transistors 200', the source / drain regions 202', and the gates 204' of the circuit component CS4 are similar to the transistors 200, the source / drain regions 202, and the gates 204 of the circuit component CS3, respectively, and are not described again here. As shown in FIG. 2A, the interconnect structure INT' includes a signal transmission structure 300' and a heat dissipation structure 400'. The signal transmission structure 300' includes a plurality of dielectric layers 310' and a plurality of conductive features 320'. The conductive features 320' include a plurality of vias 322' and a plurality of conductive patterns 324'. The vias 322' and the conductive patterns 324' of the circuit component CS4 are similar to the vias 322 and the conductive patterns 324 of the circuit component CS3, respectively, and are not described again here. The heat dissipation structure 400' includes a composite dielectric layer 410' and a plurality of conductive features 420'. The composite dielectric layer 410' includes a seed layer 412' and a diamond layer 414'. The conductive features 420' include a plurality of vias 422'. The seed layer 412', the diamond layer 414', and the vias 422' of the circuit component CS4 are similar to the seed layer 412, the diamond layer 414, and the vias 422 of the circuit component CS3, respectively, and are not described again here. Figure 4C

[0056] As shown in FIG. 2B, the circuit component CS4 is placed on and bonded with the circuit component CS3. In some embodiments, the circuit component CS4 is attached to the circuit component CS3 through the bonding layer 700. That is, the bonding layer 700 is sandwiched between the circuit component CS3 and the circuit component CS4. As shown in FIG. 2B, the bonding layer 700 is in physical contact with both the diamond layer 414 of the circuit component CS3 and the semiconductor substrate 100' of the circuit component CS4. Figure 4C Figure 4C

[0057] In some embodiments, before attaching the circuit component CS4 to the circuit component CS3, the circuit component CS4 can be placed on a carrier (not shown). Thereafter, the semiconductor substrate 100' of the circuit component CS4 can be thinned to reduce the overall thickness of the circuit component CS4. The thinning process includes a mechanical grinding process, a CMP process, etc. After the semiconductor substrate 100' of the circuit component CS4 is thinned, the circuit component CS4 is placed on the bonding layer 700 to be bonded with the circuit component CS3. In some embodiments, the bonding between the circuit component CS4 and the circuit component CS3 is referred to as a face-to-face bonding.​​​

[0058] Reference Figure 4D This forms multiple through holes 800. In some embodiments, Figure 4D Through hole 800 and Figure 2D The through-hole 800 is similar, therefore a detailed description of it is omitted here. For example... Figure 4D As shown, via 800 penetrates circuit assembly CS4, bonding layer 700, diamond layer 414, and seed layer 412 to make physical contact with the topmost conductive pattern 324. In other words, via 800 is electrically connected to the signal transmission structure 300 of circuit assembly CS3.

[0059] Reference Figure 4E Multiple UBM patterns 500 are formed on the heat dissipation structure 400' and the via 800. For example, the UBM patterns 500 are formed on the composite dielectric layer 410', the via 422', and the via 800. In some embodiments, Figure 4E UBM pattern 500 and Figure 2E Similar to the UBM pattern 500 in the example, its detailed description is omitted here. In some embodiments, the UBM pattern 500 is in physical contact with the via 422' to achieve electrical connection with the interconnect structure INT' of the circuit component CS4. Simultaneously, the UBM pattern 500 is also in physical contact with the via 800 to achieve electrical connection with the interconnect structure INT of the circuit component CS3.

[0060] like Figure 4E As shown, multiple conductive terminals 600 are arranged on the UBM pattern 500. Figure 4E The conductive terminal 600 in the middle and Figure 2E The conductive terminals 600 are similar and will not be described again here. Subsequently, a monomerization process is performed on the heat dissipation structure 400', signal transmission structure 300', semiconductor substrate 100', bonding layer 700, heat dissipation structure 400, signal transmission structure 300, and semiconductor substrate 100 to obtain multiple integrated circuits 40. In some embodiments, the monomerization process typically involves cutting using a rotating blade and / or a laser beam. In other words, the monomerization process includes laser cutting, mechanical cutting, laser grooving, other suitable processes, or combinations thereof.

[0061] In some embodiments, the composite dielectric layers 410, 410' can be transmitted through and Figures 1D-1EThe steps shown are similar to the steps formed on the signal transmission structure 300, 300'. Thus, by first depositing seed layers (i.e., seed layers 412, 412') on the signal transmission structure 300, 300' and then growing diamond layers (i.e., diamond layers 414, 414') on the seed layers, the diamond layers can be integrated into the integrated circuit 40 under the premise of being compatible with the thermal budget of the BEOL. Moreover, by introducing the heat spreading layers (i.e., diamond layers 414, 414'), the performance and lifetime of the integrated circuit 40 can be substantially improved.

[0062] According to some embodiments of the present disclosure, an integrated circuit includes a semiconductor substrate and an interconnect structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes a signal transmission structure and a heat spreading structure. The heat spreading structure is disposed on the signal transmission structure and includes composite dielectric layers and first conductive features. Each of the composite dielectric layers includes a seed layer and a heat spreading layer disposed on the seed layer. The first conductive features are embedded in the composite dielectric layers.

[0063] According to some embodiments of the present disclosure, the signal transmission structure includes dielectric layers and second conductive features. The material of the dielectric layers is different from the material of the seed layers and the material of the heat spreading layers. The second conductive features are embedded in the dielectric layers.

[0064] According to some embodiments of the present disclosure, the material of the seed layers includes cubic boron nitride and the material of the heat spreading layers includes diamond.

[0065] According to some embodiments of the present disclosure, the integrated circuit further includes a transistor disposed on the semiconductor substrate, and the first conductive features are electrically connected to the transistor through the second conductive features.

[0066] According to some embodiments of the present disclosure, a bottommost first conductive feature is in physical contact with a topmost second conductive feature.

[0067] According to some embodiments of the present disclosure, a topmost dielectric layer is in physical contact with a bottommost seed layer.

[0068] According to some embodiments of the present disclosure, the number of the dielectric layers is more than four.

[0069] According to some embodiments of the present disclosure, the top surface of each of the heat spreading layers is coplanar with the top surface of the corresponding first conductive feature.

[0070] According to some embodiments of this disclosure, the first conductive features include conductive patterns and vias. The conductive patterns extend horizontally. The vias extend vertically to connect the conductive patterns at different horizontal levels. Each of the conductive patterns passes through one of the composite dielectric layers, and each of the vias passes through another one of the composite dielectric layers.

[0071] According to some alternative embodiments of this disclosure, an integrated circuit includes a first circuit component, a second circuit component, a bonding layer, and a via. The first circuit component includes a first semiconductor substrate and a first interconnect structure disposed on the first semiconductor substrate. The first interconnect structure includes first dielectric layers, first seed layers, and first diamond layers. The first dielectric layers are stacked on top of one another. The first seed layers and the first diamond layers are alternately stacked on top of one another on the first dielectric layers. The second circuit component includes a second semiconductor substrate and a second interconnect structure disposed on the second semiconductor substrate. The second interconnect structure includes second dielectric layers, second seed layers, and second diamond layers. The second dielectric layers are stacked on top of one another. The second seed layers and the second diamond layers are alternately stacked on top of one another on the second dielectric layers. The bonding layer is sandwiched between the first circuit component and the second circuit component. The via passes through the second circuit component, the bonding layer, the first seed layers, and the first diamond layers.

[0072] According to some alternative embodiments of this disclosure, the first circuit component further includes first conductive patterns, first vias, second conductive patterns, and second vias. The first conductive patterns and the first vias are embedded in the first dielectric layers. The second conductive patterns and the second vias are embedded in the first seed layers and the first diamond layers. The first conductive patterns, the first vias, the second conductive patterns, and the second vias are electrically connected to one another.

[0073] According to some alternative embodiments of this disclosure, the via is in physical contact with a topmost one of the first conductive patterns.

[0074] According to some alternative embodiments of this disclosure, a material of the first dielectric layers is different from a material of the first seed layers.

[0075] According to some alternative embodiments of this disclosure, the material of the first seed layers includes cubic boron nitride.

[0076] According to some alternative embodiments of this disclosure, the bonding layer is in physical contact with the second semiconductor substrate and a topmost one of the first diamond layers.

[0077] According to some embodiments of the present disclosure, a method of fabricating an integrated circuit includes at least the following. A semiconductor substrate is provided. An interconnect structure is formed on the semiconductor substrate. The interconnect structure is formed at least by the following. A signal transmission structure is formed on the semiconductor substrate. A heat dissipation structure is formed on the signal transmission structure. The heat dissipation structure is formed at least by the following. A seed layer is deposited on the signal transmission structure. A diamond layer is grown on the seed layer. A first conductive feature is formed in the seed layer and the diamond layer.

[0078] According to some embodiments of the present disclosure, the seed layer is formed of cubic boron nitride.

[0079] According to some embodiments of the present disclosure, forming the first conductive feature in the seed layer and the diamond layer includes at least the following. The seed layer and the diamond layer are patterned to form an opening in the seed layer and the diamond layer. A conductive material is deposited in the opening to form the first conductive feature.

[0080] According to some embodiments of the present disclosure, a top surface of the first conductive feature is formed coplanar with a top surface of the diamond layer.

[0081] According to some embodiments of the present disclosure, forming the signal transmission structure includes at least the following. A dielectric layer is formed on the semiconductor substrate. A second conductive feature is formed in the dielectric layer, and the first conductive feature is electrically connected with the second conductive feature.

[0082] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the present disclosure. Those skilled in the art should also realize that the equivalent structures to those described herein and other equivalent structures do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, characterized by Comprising: a semiconductor substrate; and an interconnect structure disposed on the semiconductor substrate, comprising: a signal transmission structure; and a heat dissipation structure disposed on the signal transmission structure, comprising: a plurality of composite dielectric layers, wherein each of the composite dielectric layers comprises a seed layer and a heat dissipation layer disposed on the seed layer; and a first conductive feature embedded in the composite dielectric layers.

2. The integrated circuit of claim 1, wherein, The signal transmission structure comprises: a dielectric layer; and a second conductive feature embedded in the dielectric layer.

3. The integrated circuit of claim 2, wherein, Further comprising a transistor disposed on the semiconductor substrate, wherein the first conductive feature is electrically connected to the transistor through the second conductive feature.

4. The integrated circuit of claim 2, wherein, A bottommost first conductive feature is in physical contact with a topmost second conductive feature.

5. The integrated circuit of claim 2, wherein, A topmost dielectric layer is in physical contact with a bottommost seed layer.

6. The integrated circuit of claim 1, wherein, A top surface of each of the heat dissipation layers is coplanar with a top surface of a corresponding first conductive feature.

7. An integrated circuit, characterized by Comprising: a first circuit component, comprising: a first semiconductor substrate; and a first interconnect structure disposed on the first semiconductor substrate, comprising: a plurality of first dielectric layers stacked on each other; and a plurality of first seed layers and first diamond layers alternately stacked on the first dielectric layers; a second circuit component, comprising: a second semiconductor substrate; and a second interconnect structure disposed on the second semiconductor substrate, comprising: a plurality of second dielectric layers stacked on each other; and a plurality of second seed layers and second diamond layers alternately stacked on the second dielectric layers; a bonding layer interposed between the first circuit component and the second circuit component; and 8. The integrated circuit of claim 7, wherein, a via through the second circuit component, the bonding layer, the first seed layers, and the first diamond layers. The first circuit component further comprises: a first conductive pattern and a first via embedded in the first dielectric layers; and 9. The integrated circuit of claim 8, wherein, a second conductive pattern and a second via embedded in the first seed layers and the first diamond layers, wherein the first conductive pattern, the first via, the second conductive pattern, and the second via are electrically connected to each other.

10. The integrated circuit of claim 7, wherein, The via is in physical contact with a topmost first conductive pattern. The bonding layer is in physical contact with the second semiconductor substrate and a topmost first diamond layer.

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