Memory device

Abstract

A memory device includes: a device layer; and an interconnect structure on the device layer, the interconnect structure including a resistive random access memory (RRAM) device. The resistive random access memory device includes: an electrode layer higher than a device layer; an oxide semiconductor layer on the electrode layer; a gate structure surrounding the oxide semiconductor layer; an insulating layer on the gate structure; and a resistor. The resistor includes: a bottom electrode on an oxide semiconductor layer; a dielectric layer on the bottom electrode; and a top electrode on the dielectric layer.

Description

Technical Field

[0001] Several embodiments of this disclosure relate to resistive memory devices. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the development of ICs, functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while geometric dimensions (i.e., the smallest component (or line) that can be produced using manufacturing processes) have decreased. This shrinkage typically benefits production efficiency and reduces associated costs. However, such shrinkage also increases the complexity of handling and manufacturing ICs. Utility Model Content

[0003] Multiple embodiments of this disclosure provide a memory device including: a device layer and an interconnect structure on the device layer, the interconnect structure including a resistive random access memory (RRAM) device. The resistive RRAM device includes: an electrode layer above the device layer, an oxide semiconductor layer on the electrode layer, a gate structure surrounding the oxide semiconductor layer, an insulating layer on the gate structure, and a resistor. The resistor includes: a bottom electrode on the oxide semiconductor layer, a dielectric layer on the bottom electrode, and a top electrode on the dielectric layer.

[0004] Multiple embodiments of this disclosure provide a memory device including: a device layer and an interconnect structure on the device layer, the interconnect structure including a resistive random access memory (RRAM) device. The resistive RRAM device includes a resistor comprising: a top electrode above the device layer, a dielectric layer on the top electrode, and a bottom electrode on the dielectric layer. The resistive RRAM device further includes: an oxide semiconductor layer on the bottom electrode, a first insulating layer on the resistor, a gate structure on the first insulating layer, a second insulating layer on the gate structure, and an electrode layer on the oxide semiconductor layer above the gate structure. The gate structure surrounds the oxide semiconductor layer.

[0005] Multiple embodiments of this disclosure provide a memory device including: a device layer and an interconnect structure on the device layer, the interconnect structure including a resistive random access memory (RRAM) device. The resistive RRAM device includes a resistor comprising: a top electrode above the device layer, a dielectric layer on the top electrode, and a bottom electrode on the dielectric layer. The resistive RRAM device further includes: an oxide semiconductor layer on the bottom electrode, a first insulating layer on the resistor, a gate structure on the first insulating layer, a second insulating layer on the gate structure, an electrode layer on the oxide semiconductor layer above the gate structure, and an oxygen storage layer between the dielectric layer and the top electrode. The gate structure surrounds the oxide semiconductor layer. Attached Figure Description

[0006] Several aspects of this disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 1R These are views of various embodiments of an integrated circuit device at various stages of manufacturing, based on various aspects of this disclosure;

[0008] Figure 2A and Figure 2B These are schematic cross-sectional views and circuit diagrams of various embodiments of an integrated circuit device according to multiple aspects of this disclosure;

[0009] Figures 3A to 3U These are views of various embodiments of an integrated circuit device at various stages of manufacturing, based on various aspects of this disclosure;

[0010] Figure 4A and Figure 4B These are schematic cross-sectional views and circuit diagrams of various embodiments of an integrated circuit device according to multiple aspects of this disclosure;

[0011] Figure 5 and Figure 6 This is a flowchart of a method for forming an integrated circuit device according to various embodiments.

[0012] [Symbol Explanation]

[0013] 10: Integrated circuit devices

[0014] 10A: Integrated Circuit Device

[0015] 16: Gate Structure

[0016] 18: Fuse assembly

[0017] 18A: Fuse assembly

[0018] 18M: Fuse Device

[0019] 20: Memory devices (nanostructure devices, resistive random access memory devices)

[0020] 20A: Memory device (resistive random access memory device)

[0021] 20M: Memory device (resistive random access memory)

[0022] 22: Nanostructures (channels)

[0023] 33: Multiple parts of the upper surface

[0024] 35: Opening

[0025] 36: Gate structure

[0026] 37: Opening

[0027] 38: Fuse assembly

[0028] 40: Resistive Random Access Memory Device

[0029] 41: Gate spacer

[0030] 74: Internal spacers

[0031] 80: Nanostructured devices (nanostructured transistors, transistors)

[0032] 82: Source / Drain (Source / Drain Region, Source / Drain Characteristics)

[0033] 82P: Source / Drain (Source / Drain Region)

[0034] 110:Substrate

[0035] 160: Oxide layer (dielectric layer, first dielectric layer)

[0036] 162: Electrode layer

[0037] 162C: Electrode contact portion

[0038] 164: Channel layer (oxide semiconductor layer)

[0039] 164C: Channel

[0040] 164H: Horizontal section

[0041] 164L: Oxide semiconductor layer

[0042] 164L': Oxide semiconductor layer

[0043] 166: Dielectric layer (gate dielectric layer)

[0044] 166H: Horizontal section

[0045] 166L: Gate dielectric layer

[0046] 166L': Gate dielectric layer

[0047] 166V: Vertical section

[0048] 168: Gate conductive layer

[0049] 168H: Horizontal section

[0050] 168L: Gate conductive layer

[0051] 168L': Gate conductive layer

[0052] 168V: Vertical section

[0053] 170: Oxide layer (masking layer)

[0054] 172: Oxide layer

[0055] 174: Insulation layer

[0056] 180: Bottom electrode

[0057] 180A: Bottom electrode

[0058] 180B: Horizontal section

[0059] 180L: Bottom Electrode Layer

[0060] 180M: Bottom Electrode

[0061] 180S: Sidewall section

[0062] 180V: V-shaped part

[0063] 182: Switching Layer

[0064] 182A: Switching Layer

[0065] 182B: Horizontal section

[0066] 182L: Switching Layer

[0067] 182M: Switching Layer

[0068] 182S: Sidewall section

[0069] 182V: V-shaped part

[0070] 184: Ion Conducting Layer

[0071] 184A: Ion Conducting Layer

[0072] 184B: Horizontal section

[0073] 184L: Ion-conducting layer (optional layer)

[0074] 184M: Ion Conducting Layer

[0075] 184S: Sidewall portion

[0076] 184V: V-shaped part

[0077] 186: Top Electrode

[0078] 186A: Top Electrode

[0079] 186B: Horizontal section

[0080] 186L: Top electrode layer

[0081] 186S: Sidewall portion

[0082] 186V: V-shaped part

[0083] 186M: Top Electrode

[0084] 188L: Spacer

[0085] 188M: Spacer material layer

[0086] 188U: Spacer

[0087] 190BL: Opening

[0088] 190G: Open

[0089] 190WL: Open

[0090] 192: Oxide layer

[0091] 194: Contact

[0092] 196: Contact

[0093] 198: Contact

[0094] 200: Gate structure

[0095] 200P: Gate structure

[0096] 210: Electrical conductivity characteristics

[0097] 260: Transistor

[0098] 270: Resistor (memristor)

[0099] 300: Planar transistor (planar device)

[0100] 352: Fourth dielectric layer

[0101] 360: First dielectric layer

[0102] 364: Oxide Semiconductor Channel (Channel)

[0103] 364L: Oxide semiconductor layer

[0104] 366: Gate dielectric layer

[0105] 366L: Gate dielectric layer

[0106] 366L': Gate dielectric layer

[0107] 368: Gate electrode layer (gate conductive layer)

[0108] 368L: Gate conductive layer

[0109] 368L': Gate conductive layer

[0110] 370: Mask layer

[0111] 372B: Second dielectric layer

[0112] 372L: Second dielectric layer

[0113] 374: Insulation layer

[0114] 374L: Insulation layer

[0115] 380: Bottom electrode

[0116] 380L: Bottom electrode layer (layer)

[0117] 382: Switching Layer

[0118] 382L: Switching Layers

[0119] 384: Ion Conducting Layer

[0120] 384L: Ion-conducting layer (optional layer, layer)

[0121] 386: Top electrode (layer)

[0122] 386C: Electrode contact portion

[0123] 392: Third dielectric layer

[0124] 392L: Third dielectric layer

[0125] 393: Second Insulation Layer

[0126] 394: Contact

[0127] 395: Electrode layer

[0128] 395L: Electrode layer

[0129] 396: Contacts

[0130] 398: Contact

[0131] 460: Transistor

[0132] 470: Resistor

[0133] 500: Masking layer (dielectric layer)

[0134] 700: Front interconnect structure

[0135] 700A: Front-side interconnect structure

[0136] 710: Device Layer

[0137] 710A: Device Layer

[0138] 720: Dielectric layer

[0139] 730: Conductivity characteristics

[0140] 730A: Conductivity Characteristics

[0141] 730B: Conductivity Characteristics

[0142] 740: Conductive via

[0143] 800: Backside interconnect structure

[0144] 810: Dielectric layer

[0145] 820: Conductivity characteristics

[0146] 820A: Conductivity Characteristics

[0147] 820B: Power rail (conductivity characteristics)

[0148] 820C: First power rail (power rail)

[0149] 830: Conductive via

[0150] 840: Backside guide hole

[0151] 850: Trap

[0152] 900: Semiconductor layer

[0153] 1000: Method

[0154] 1010: Action

[0155] 1020: Action

[0156] 1030: Action

[0157] 1040: Action

[0158] 1050: Action

[0159] 1060: Action

[0160] 1070: Action

[0161] 1080: Action

[0162] 2000: Method

[0163] 2010: Action

[0164] 2020: Action

[0165] 2030: Action

[0166] 2040: Action

[0167] 2050: Action

[0168] 2060: Action

[0169] 2070: Action

[0170] BL: Bitline

[0171] D1: Distance

[0172] R: Resistor

[0173] WL: Character Line

[0174] X: Direction

[0175] Y: direction

[0176] Z: Direction Detailed Implementation

[0177] The following disclosure provides numerous different implementations or embodiments for carrying out various features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify this disclosure. These are, of course, merely embodiments and not limiting. For example, in the following description, forming a first feature above or on top of a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for the purpose of simplification and clarity, and the repetition itself does not imply a relationship between the various implementations and / or configurations discussed.

[0178] Furthermore, to facilitate the description of the relationship between one element or feature and another, as illustrated in the accompanying drawings, spatially relative terms such as “below,” “lower,” “lower,” “higher,” “upper,” and similar terms may be used herein. In addition to the directions depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0179] Terms indicating relative degree, such as “about,” “basically,” and the like, should be understood as what a person skilled in the art would understand based on current technical specifications.

[0180] The terms “first,” “second,” “third,” etc., may be used in this document to describe a sequence of multiple events or the order of multiple elements, but they may be interchanged or varied in some cases. For example, a second layer may be formed on top of a first layer (e.g., sequentially after the first layer), but in some cases, the first layer may be referred to as “second layer,” “third layer,” “fourth layer,” or similar, while the second layer may be referred to as “first layer,” “third layer,” “fourth layer,” or similar.

[0181] The term "surrounding" may be used herein to describe, for example, in three-dimensional space, a structure that completely or partially surrounds another element or structure. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) but not on two vertical sides (e.g., top and bottom). In another embodiment, the first structure may partially surround the second structure, for example, by surrounding three sides (e.g., top, front, and back), while exposing other sides (e.g., left, right, and bottom).

[0182] "Source / drain region" can refer to the source or drain, individually or collectively, depending on the context.

[0183] This disclosure generally relates to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured FETs, such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), and the like.

[0184] Integrated memory refers to memory technology that is built directly onto a microchip or integrated circuit, rather than as multiple separate or “discrete” components. One such technology is resistive random access memory (RRAM), also known as ReRAM (Resistive RAM) or memristor-based memory. Resistive random access memory is a non-volatile memory technology with several advantages, including high density, low power consumption, and fast access.

[0185] Resistive random access memory (RAM) operates on the principle of resistance switching. The materials used in resistive RAM change their resistance between a high-resistance (off) state and a low-resistance (on) state depending on the applied voltage. These materials typically have a thin insulating layer sandwiched between two electrodes. By applying a voltage pulse of selected amplitude, the resistance of the insulating layer can switch between the different states. Resistive RAM is a non-volatile memory technology, meaning it retains stored data even when power is off. Resistive RAM devices use relatively low power to switch resistance states, which contributes to energy-efficient operation in integrated circuits. Compared to some other non-volatile memory technologies, resistive RAM devices have the potential to provide fast read and write access times, making them suitable for applications requiring rapid data retrieval. Resistive RAM can be integrated into advanced semiconductor manufacturing processes, facilitating integration into modern microchips without significant modifications to existing manufacturing processes. Planar memory devices can include two separate planar devices, typically consisting of a single transistor (IT) and a single resistor (IR) located in two separate metal layers. Therefore, increasing device density becomes difficult.

[0186] In several embodiments, grounded resistors or "grounded fuse devices" are stacked on the source / drain to reduce passive device area for further device density improvements. The resistive random access memory (RAM) device according to various embodiments can be a vertical resistive RAM device and can be referred to as a vertical RRAM device. For example, the resistive RAM device can be used with front-end process (FEOL) planar, fin field-effect transistor, or gate all-ring field-effect transistor (GAAFET) logic devices. The interconnect between the resistive RAM device and the logic device can be via back-end process (BEOL) metal wiring. The vertical resistive RAM device can be inserted as a vertical gate all-ring resistive RAM device between two metal layers in an interconnect structure (e.g., back-end process or back-side interconnect), such as between Mx and Mx+1 metal layers (e.g., M3 and M4, M6 and M7, or similar). Vertical resistive random access memory devices may include metal-insulator-metal (MIM) fuse devices located on top of or below oxide semiconductor channels (e.g., indium-gallium-zinc-oxide (IGZO) channels).

[0187] Nanostructured transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual or multiple patterning processes. Generally, dual or multiple patterning processes combine photolithography and self-aligned processes, allowing the pattern to be created to have, for example, a smaller pitch (smaller than the pitch obtained using a single direct photolithography process). For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A plurality of spacers are formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0188] Figures 1A to 1R These are views of various embodiments of multiple memory devices 20, 20A, 20M at different stages of manufacturing according to various aspects of this disclosure. Figure 2A and Figure 2B These are schematic cross-sectional views and circuit diagrams of various embodiments of integrated circuit devices 10 and 10A, including memory devices 20, 20A, and 20M, according to various aspects of this disclosure. Figure 5 This is a flowchart of a method 1000 for forming a memory device according to various embodiments.

[0189] Figure 5A flowchart illustrating a method 1000 for forming an integrated circuit device or part thereof from a workpiece according to one or more aspects of this disclosure is provided. Method 1000 is merely one embodiment and is not intended to limit this disclosure to the content explicitly illustrated in method 1000. Additional actions may be provided before, during, and after method 1000, and some described actions may be replaced, deleted, or moved for additional embodiments of this method. For simplicity, not all actions are described in detail herein. Method 1000 is described below with reference to partial perspective and / or cross-sectional views of a workpiece at different stages of manufacturing according to various embodiments of method 1000, as shown in [examples omitted]. Figures 1A to 1R As shown in the figures. To avoid ambiguity, in all figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X and Y directions. Note that because the workpiece can be manufactured as a semiconductor device, it may be referred to as a semiconductor device depending on the context.

[0190] exist Figure 1A In this configuration, a first electrode layer 162 is formed on a first dielectric layer 160 of an integrated circuit or integrated wafer (IC) device. The first dielectric layer 160 may be formed on or included in a first portion of an interconnect structure above or below the device layer, as will be referred to... Figure 2A and Figure 2B A more detailed description follows. In short, the device layer may include one or more integrated devices, such as planar field-effect transistors, fin field-effect transistors, nanostructured field-effect transistors, metal-oxide-semiconductor (MOS) capacitors, and the like. Interconnect structures may be on the device layer and may include mid-end-of-line (MEOL) and / or back-end-of-line (BEOL) interconnect structures that provide electrical connections between the multiple integrated devices and to other devices outside the integrated devices. Alternatively or additionally, the interconnect structures may include back-side interconnect structures on the back side of the device layer. Figure 2A and Figure 2B Examples of front-side interconnect structure 700 and back-side interconnect structure 800, as well as planar field-effect transistor and nanostructure transistor device layers 710 and 710A, are shown respectively. (See reference...) Figure 2A and Figure 2B The actions 1010 and 1020 of method 1000 are described in more detail, including forming a device layer (action 1010) and forming a first portion of an interconnect structure on the device layer (action 1020).

[0191] The first dielectric layer 160 may be or includes an oxide, such as silicon oxide, and may be included in an interconnect structure above or below the device layer. The first dielectric layer 160 may be formed via a suitable deposition operation, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. The first dielectric layer 160 may be present on a metallization layer, which includes metallic features (e.g., contacts, traces, wires, vias, or the like) embedded within an intermetallic dielectric (IMD). The intermetallic dielectric may be or include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), porous dielectric materials, or the like.

[0192] A first electrode layer 162 is formed on the first dielectric layer 160. In some embodiments, the first electrode layer 162 is or includes a transition metal nitride. For example, the first electrode layer 162 may be or includes TiN, TaN, WN, HfN, or the like, and may be formed via a suitable deposition operation, such as physical vapor deposition (PVD), chemical vapor deposition, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like.

[0193] After forming the first electrode layer 162 on the first dielectric layer 160, an oxide semiconductor layer 164L may be formed on the first electrode layer 162, corresponding to operation 1030 of method 1000. The oxide semiconductor layer 164L may be or include indium gallium zinc oxide (IGZO). In some embodiments, the oxide semiconductor layer 164L is or includes one or more of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), hafnium indium zinc oxide (HIZO), gallium zinc oxide (GZO), indium gallium oxide (IGO), zinc indium tin oxide (ZITO), combinations thereof, and the like. The oxide semiconductor layer 164L may be formed via a suitable deposition operation, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, electron beam evaporation, or the like.

[0194] exist Figure 1BIn this process, after the formation of the oxide semiconductor layer 164L, a patterned oxide semiconductor layer 164L' including a channel 164C is formed by patterning the oxide semiconductor layer 164L. The channel 164C may have a columnar shape. That is, the channel 164C may have a circular, square, rectangular, irregular shape, or similar cross-sectional profile in the XY plane. The height of the channel 164C in the Z-axis direction relative to the width of the channel 164C in the X-axis or Y-axis direction may be referred to as the aspect ratio of the channel 164C. The aspect ratio of the channel 164C may be in the range of about 1.5 to about 20, about 2 to about 15, about 4 to about 10, or another suitable range. An aspect ratio exceeding about 20 may cause the channel 164C to collapse. An aspect ratio below about 1.5 may not provide sufficient channel length.

[0195] exist Figures 1C to 1F In the middle, a gate structure 16 is formed around channel 164C (see Figure 1F This corresponds to action 1040 of method 1000. The gate structure 16 includes a dielectric layer 166 and a gate conductive layer 168.

[0196] exist Figure 1C In this process, after forming a channel 164C with a columnar shape, a gate dielectric layer 166L is formed on an oxide semiconductor layer 164L' including the channel 164C. The gate dielectric layer 166L surrounds and covers the channel 164C. That is, the gate dielectric layer 166L can be in direct contact with multiple sidewalls and the top surface of the channel 164C. The gate dielectric layer 166L can be or includes at least one dielectric material, such as SiO2. 2， Alternatively, a high-dielectric-constant gate dielectric material may refer to a dielectric material having a higher dielectric constant than that of silicon oxide (k≈3.9). Examples of high-dielectric-constant dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer 166L comprises one or more of SiO2, HfO, La, SiON, SiCON, Zn, or Zr. In some embodiments, the gate dielectric layer 166L has a thickness of about 5 angstroms (Å) to about 100 angstroms. The high-dielectric-constant dielectric material can be deposited via atomic layer deposition, chemical vapor deposition, physical vapor deposition, molecular beam epitaxy (MBE), or similar methods.

[0197] See further Figure 1CAfter the formation of the gate dielectric layer 166L, a gate conductive layer 168L is formed on the gate dielectric layer 166L. The gate conductive layer 168L may be in direct contact with the gate dielectric layer 166L. For example, the gate conductive layer 168L may be in direct contact with multiple sidewalls and the top surface of the gate dielectric layer 166L. The gate conductive layer 168L may include a conductive material, such as polysilicon, silicon, titanium, tantalum, aluminum, tungsten, nickel, zinc, indium, gallium, germanium, carbon, cobalt, ruthenium, iridium, molybdenum, copper, or combinations thereof. The conductive material may be deposited via a suitable deposition operation, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, electron beam evaporation, or similar methods. In some embodiments, the gate conductive layer 168L has a thickness of about 5 angstroms to about 100 angstroms.

[0198] exist Figure 1D In the process, after the formation of the gate conductive layer 168L, in Figure 1C A masking layer 170 is formed on the structure shown. The masking layer 170 may be or include an oxide layer. The oxide layer 170 may be a blanket layer that covers the gate conductive layer 168L. The oxide layer 170 may be formed via any of the methods described above with reference to the oxide layer 160.

[0199] exist Figure 1E In the process, after the deposition of oxide layer 170, oxide layer 170 is patterned to expose electrode contact portion 162C. Figure 1E Highlighted by dashed lines. After patterning the oxide layer 170, multiple exposed portions of the gate conductive layer 168L, the gate dielectric layer 166L, and the oxide semiconductor layer 164L' are removed to expose the electrode contact portion 162C. Etching of the oxide layer 170 can be performed via reactive ion etching (RIE), wet etching, plasma etching, inductively coupled plasma (ICP) etching, or similar methods. After patterning the oxide layer 170, the exposed portions of the gate conductive layer 168L can be etched, for example, via reactive ion etching, inductively coupled plasma etching, or similar methods using an etchant such as CF4, to produce the gate conductive layer 168L'. Then, etching of the gate dielectric layer 166L can be performed, for example, via dry etching (e.g., reactive ion etching, inductively coupled plasma etching, or similar methods) using a chlorine or fluorine-based etchant, to produce the gate dielectric layer 166L'. Then, etching the oxide semiconductor layer 164L' can produce the channel layer 164, for example, by dry etching (such as reactive ion etching, inductively coupled plasma etching, or the like) using chlorine-based or fluorine-based etchants.

[0200] exist Figure 1FIn this process, after forming the gate conductive layer 168L', the gate dielectric layer 166L', and the channel layer 164, multiple portions of the gate conductive layer 168L' and the gate dielectric layer 166L' on the upper region of the channel 164C are removed. In some embodiments, in Figure 1F Following this operation, oxide layer 170 is removed and another oxide layer 172 is formed. Oxide layer 172 is then recessed below the level of the upper surface of channel 164C, for example, via chemical mechanical planarization (CMP), anisotropic etching, a combination thereof, or the like. After recessing, multiple portions of the gate conductive layer 168L' and the gate dielectric layer 166L' in the upper region of channel 164C are exposed. In some embodiments, the height of a portion of channel 164C protruding from oxide layer 172 ranges from approximately 1 / 10 to approximately 2 / 3 of the total height of channel 164C.

[0201] After the oxide layer 172 is recessed, multiple exposed portions of the gate conductive layer 168L' and the gate dielectric layer 166L' on the upper region of channel 164C are removed. This removal can be similar to that described in the reference. Figure 1E The described removal includes similar etching processes and chemicals. After the removal of multiple exposed portions, the gate conductive layer 168 and the gate dielectric layer 166 are retained, resulting in a structure as shown in Figure 1F As depicted in the figure. The gate dielectric layer 166 includes a vertical portion 166V and a horizontal portion 166H, the vertical portion surrounding the channel 164C, and the horizontal portion 166H covering the horizontal portion 164H of the oxide semiconductor layer 164. The gate conductive layer 168 includes a vertical portion 168V and a plurality of horizontal portions 168H, the vertical portion 168V surrounding the channel 164C, and the plurality of horizontal portions 168H respectively covering the horizontal portion 166H of the gate dielectric layer 166 and the horizontal portion 164H of the oxide semiconductor layer 164.

[0202] exist Figures 1G to 1I In the process, corresponding to action 1050 of method 1000, a fuse device 18 is formed on the exposed upper portion of channel 164C. The fuse device 18 may be a metal-insulator-metal (MIM) device. The fuse device 18 may be a memristor and may include one or more of the following layers: bottom electrode, active or switching layer (insulator), blocking or buffering or ion-conducting layer (optional), top electrode, passivation layer (optional), and encapsulation (optional).

[0203] exist Figure 1GIn this process, an insulating layer 174 is formed covering the gate dielectric layer 166 and the gate conductive layer 168. The insulating layer 174 provides electrical insulation between the gate structure 16 and the fuse device 18 formed in subsequent operations. In some embodiments, the insulating layer 174 is a dielectric layer including one or more of SiN, SiCN, SiON, SiOCN, SiOC, or the like. The insulating layer 174 can be formed via... Figure 1F The structure depicted is covered with a conformal layer of one or more of the aforementioned dielectric materials. The deposition can be performed using a suitable deposition operation, such as chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam epitaxy, or similar methods. The insulating layer 174 can be recessed after deposition to expose the upper region of the channel 164C.

[0204] exist Figure 1H In the process, after the deposition of the insulating layer 174, multiple material layers for forming the fuse device 18 can be deposited sequentially as multiple blanket-covered conformal layers covering the channel 164C and the insulating layer 174.

[0205] First, a bottom electrode layer 180L may be formed. The bottom electrode layer 180L may include a transition metal nitride, such as TiN, or another conductive material. The bottom electrode layer 180L may be formed via a suitable deposition operation, such as atomic layer deposition, chemical vapor deposition, or similar.

[0206] After the formation of the bottom electrode layer 180L, an active or switching layer 182L may be formed. The switching layer 182L may be a high-dielectric-constant dielectric layer and may include at least one of a variety of dielectric materials having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-dielectric-constant dielectric materials include TiO2, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof (e.g., multilayers). The switching layer 182L may be formed via a suitable deposition operation, such as atomic layer deposition, chemical vapor deposition, or the like.

[0207] After the formation of the switching layer 182L, an optional barrier, buffer, or ion-conducting layer 184L may be formed. The ion-conducting layer 184L may also be referred to as an "oxygen storage layer." The optional layer 184L may be a titanium or tantalum layer. The titanium or tantalum layer may be formed via a suitable deposition operation on the switching layer 182L, such as via atomic layer deposition, chemical vapor deposition, or similar methods.

[0208] After the formation of optional layer 184L or switching layer 182L, a top electrode layer 186L may be formed thereon. The top electrode layer 186L may comprise a transition metal nitride, such as TiN, or another conductive material. The top electrode layer 186L may be formed via a suitable deposition operation, such as atomic layer deposition, chemical vapor deposition, or the like. In some embodiments, the top electrode layer 186L is made of the same or substantially the same material as the bottom electrode layer 180L.

[0209] exist Figure 1I In this process, after forming the bottom electrode layer 180L, the switching layer 182L, the optional barrier, buffer, or ion-conducting layer 184L, and the top electrode layer 186L, a patterning operation is performed to form the fuse device 18. Patterning may include one or more etching operations that remove portions of each of the bottom electrode layer 180L, the switching layer 182L, the optional barrier, buffer, or ion-conducting layer 184L, and the top electrode layer 186L between adjacent channels 164C, to form individual fuse devices 18 that are electrically and physically isolated from each other over each channel 164C. Furthermore, removing material from the bottom electrode layer 180L, the switching layer 182L, the optional barrier, buffer, or ion-conducting layer 184L, and the top electrode layer 186L between the channels 164C opens up space for forming multiple contacts to the first electrode layer 162 and the gate conductive layer 168, as will be described in the following reference. Figures 1L to 1N A more detailed description follows. The removal of the bottom electrode layer 180L, the switching layer 182L, the optional barrier, buffer, or ion-conducting layer 184L, and the top electrode layer 186L can be achieved via reactive ion etching, inductively coupled plasma etching, or similar methods. Figure 1I The resulting structure is depicted in the figure, wherein the fuse device 18 includes a bottom electrode 180, a switching layer 182, an optional blocking, buffering or ion-conducting layer 184, and a top electrode 186.

[0210] exist Figure 1J and Figure 1K In the process, corresponding to action 1060 of method 1000, a plurality of spacers 188U, 188L are formed on the fuse device 18. The spacers 188U, 188L include an upper spacer 188U and a lower spacer 188L respectively surrounding an upper portion and a lower portion of the fuse device 18. The spacers 188U, 188L facilitate providing protection during contact formation and, after formation, provide physical and electrical isolation between the fuse device 18 and the contacts.

[0211] exist Figure 1JIn this process, a spacer material layer 188M is formed on the fuse assembly 18 and the insulating layer 174. The spacer material layer 188M may be or contain SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, or ZrAlO2. x HfAlO x HfSiO x Al2O3, or other suitable materials, or one or more thereof. The spacer material layer 188M can be formed via a suitable deposition operation, such as low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition (HDPCVD), atomic layer deposition, or similar methods. The spacer material layer 188M can be deposited as a conformal thin layer over the exposed areas of the fuse device 18 and the insulating layer 174, thereby creating a layer in… Figure 1J The structure shown.

[0212] exist Figure 1K In this process, the spacer material layer 188M is etched to remove multiple horizontal portions covering the top electrode 186 and the insulating layer 174. Etching may include reactive ion etching, inductively coupled plasma etching, wet etching, or another suitable etching operation. After etching, the upper spacer 188U and the lower spacer 188L remain on the fuse assembly 18, as shown in... Figure 1K As depicted in the diagram. The upper spacer 188U may surround the upper region of the fuse assembly 18 and may be located on the horizontal portion of the top electrode 186. The lower spacer 188L may surround the lower region of the fuse assembly 18, may be located on the sidewalls or ends (and in direct contact with) multiple horizontal portions of the top electrode 186, the ion-conducting layer 184, the switching layer 182, and the bottom electrode 180, and may be located on the upper surface of the insulating layer 174. Both the upper spacer 188U and the lower spacer 188L may each have a circular profile. That is, after the etching operation, their multiple outer sidewalls may be circular rather than vertical.

[0213] exist Figures 1L to 1NIn the process, corresponding to operation 1070 of method 1000, a plurality of contacts 194, 196, and 198 are formed respectively connected to the electrode contact portion 162C, the top electrode 186, and the gate conductive layer 168. Contacts 194, 196, and 198 provide electrical connections to the resistive random access memory device 20. For example, bit lines (BL), word lines (WL), and ground (or other bias voltage) can be connected to the resistive random access memory device 20 via contacts 194, 196, and 198, which can carry voltages applied to the electrode contact portion 162C, the top electrode 186, and the gate conductive layer 168 for programming, erasing, or otherwise operating the resistive random access memory device 20. Figure 10 This is a simplified circuit diagram of the resistive random access memory device 20 according to various embodiments.

[0214] exist Figure 1L In this process, a masking layer 500 is formed on the fuse device 18 and the insulating layer 174. The masking layer 500 may be or may contain an oxide layer, such as silicon oxide, and may be deposited via any of the methods described above for the masking layer 170.

[0215] exist Figure 1M In this structure, multiple openings 190BL, 190G, and 190WL are formed in the mask layer 500 and the underlying structure to expose the electrode contact portion 162C, the top electrode 186, and the gate conductive layer 168. For example, the openings 190BL, 190G, and 190WL may initially be formed through the mask layer 500 and seated on the insulating layer 174 and the top electrode 186. The remaining mask layer 500 is referred to as the oxide layer 192. The openings 190BL and 190WL may then extend through the insulating layer 174 and the oxide layer 172 to expose the electrode contact portion 162C and the gate conductive layer 168. The openings 190BL, 190G, and 190WL may be formed via one or more suitable etching operations, such as reactive ion etching, inductively coupled plasma, or similar methods.

[0216] exist Figure 1NIn this configuration, source / drain contacts 194, gate contacts 198, and top electrode contacts 196 (or collectively referred to as "contacts 194, 196, 198") are formed in openings 190BL, 190WL, and 190G, respectively. Contacts 194, 196, and 198 may be or include one or more of a liner layer, a barrier layer, an adhesive layer, a conductive core layer, and the like. In some embodiments, contacts 194, 196, and 198 comprise one or more of Cu, Co, Al, Ni, W, Ru, Ti, TiN, Ta, TaN, alloys thereof, multilayers thereof, combinations thereof, or the like. The layers forming contacts 194, 196, and 198 may be formed via one or more suitable deposition operations, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like.

[0217] exist Figure 10 In this circuit, the resistive random access memory device 20 can be represented in simple circuit form as a 1T1R ("one transistor, one resistor") circuit, which includes a transistor 260 and a resistor 270, which may be a memristor 270. A gate conductive layer 168, a gate dielectric layer 166, and a channel 164C may be included in the transistor 260. The gate electrode of the gate conductive layer 168 or the transistor 260 may be connected to the word line WL via contact 198. The source / drain electrodes of the transistor 260 may be electrode layer 162, which may be connected to the bit line BL via contact 194. The top electrode 186 of the fuse device 18 (which may be a memristor 270) may be connected to a bias voltage (e.g., ground) via contact 196.

[0218] After contacts 194, 196, and 198 are formed, a second part of the interconnection structure can be formed on contacts 194, 196, and 198, corresponding to operation 1080 of method 1000. Figure 2A and Figure 2B The diagram depicts a front interconnect structure 700 and a back interconnect structure 800, which include a first part and a second part, and a resistive random access memory device 20 between them.

[0219] Figures 1P to 1R These are schematic diagrams illustrating fuse devices 18A and 18M according to various embodiments. Figure 1P In the middle, the fuse device 18A has an angular shape. Figure 1Q and Figure 1R In the middle, the fuse device 18M has an M-shaped cross-sectional profile.

[0220] exist Figure 1PIn this embodiment, the fuse device 18A has an angular or pointed cross-sectional profile in the XZ and / or YZ planes. The angularity may be due to etching of the upper portion of the channel 164C, which protrudes above the insulating layer 174. In some embodiments, after etching the upper portion, the upper portion of the channel 164C has a conical or pyramidal shape in a perspective view, such that subsequent layers formed thereon inherit the conical or pyramidal shape, as in... Figure 1P As depicted in the diagram, each of the bottom electrode 180A, switching layer 182A, ion-conducting layer 184A, and top electrode 186A may have multiple tapered sidewalls that intersect at corresponding points above channel 164C. Due to the angular or pointed profile of the top electrode 186A, the contact area between contact 196 and the top electrode 186A can be increased, which may help reduce the contact resistance therebetween and improve the performance of the resistive random access memory device 20A, including fuse device 18A.

[0221] exist Figure 1Q In the embodiment, the fuse device 18M has an M-shaped cross-sectional profile in the XZ and / or YZ planes. The M-shape may be due to the etching of the upper portion of the channel 164C, which protrudes above the insulating layer 174. That is, in the perspective view, the central region of the upper portion may be recessed to have an inverted conical or inverted pyramidal cutout shape. In some embodiments, after etching the upper portion, subsequent layers formed thereon inherit the inverted conical or inverted pyramidal shape, as in... Figure 1Q As shown in the diagram. That is, each of the bottom electrode 180M, switching layer 182M, ion-conducting layer 184M, and top electrode 186M may have multiple tapered sidewalls that intersect at corresponding points within the channel 164C. Due to the angular or pointed profile of the top electrode 186M, the contact area between the contact 196 and the top electrode 186M can be increased, which helps to reduce the contact resistance therebetween and improve the performance of the resistive random access memory device 20M, including the fuse device 18M.

[0222] Figure 1R It is based on the various implementation methods Figure 1Q A detailed view of the fuse assembly 18M of the resistive random access memory device 20M. As depicted, each of the bottom electrode 180M, switching layer 182M, ion conduction layer 184M, and top electrode 186M may respectively include horizontal portions 180B, 182B, 184B, 186B, vertical sidewall portions 180S, 182S, 184S, 186S, and V-shaped portions 180V, 182V, 184V, 186V. The V-shaped portions 180V, 182V, 184V, 186V are V-shaped in cross-section, but may be conical or pyramidal in perspective view.

[0223] The V-shaped portion 180V increases the contact area between the channel 164C and the bottom electrode 180M, thereby improving (e.g., reducing) the contact resistance therebetween and enhancing device performance. That is, in addition to contacting the channel 164C via the vertical sidewall portion 180S (e.g., direct contact), the contact area between the upper surface of the channel 164C and the bottom electrode 180M is increased by the V-shaped portion 180V extending into the channel 164C. In some embodiments, the V-shaped portion 180V of the bottom electrode 180M may extend a distance D1 below its horizontal portion 180B. The distance D1 may be in the range of about 10 angstroms to about 10 nanometers. In some embodiments, the V-shaped portion 180V extends to the same level as the lower surface of the horizontal portion 180B, or extends to a height above the lower or upper surface of the horizontal portion 180B. Although the V-shaped portion 180V is depicted as having a pointed tip, in some embodiments, the V-shaped portion 180V may alternatively have a rounded or blunt tip. In some implementations, instead of forming a V-shaped portion 180V, a U-shaped portion is formed.

[0224] Figure 2A and Figure 2B This is a schematic cross-sectional view of the resistive random access memory device 20 included in the integrated circuit devices 10 and 10A according to various embodiments. Figure 2A In this configuration, a resistive random access memory device 20 is included in the front-side interconnect structure 700. Figure 2B In this embodiment, resistive random access memory (RAM) device 20 is included in the back-side interconnect structure 800. It should be understood that some embodiments of the integrated circuit device may include the resistive RAM device 20 in both the front-side interconnect structure and the back-side interconnect structure, which may be advantageous for increasing the density of resistive RAM devices per unit area of ​​the integrated circuit device. It should also be understood that, for illustrative purposes only, in... Figure 2A The diagram depicts a planar transistor 300, in Figure 2B The image depicts a nanostructured transistor 80 (e.g., a gate-to-all-ring field-effect transistor). The nanostructured transistor 80 can also be used in… Figure 2A In the configuration depicted, the planar transistor 300 can also be used in Figure 2B In the configurations depicted, according to various embodiments, other transistor types (e.g., fin field-effect transistors) may be included in the integrated circuit devices 10, 10A instead of the planar transistor 300 and the nanostructure transistor 80.

[0225] exist Figure 2AIn the integrated circuit device 10, there is a substrate 110, a device layer 710 on and / or within the substrate 110, and a front interconnect structure 700 on the device layer 710, the front interconnect structure 700 including a resistive random access memory device 20. Figure 2A Device layer 710 is depicted as including planar transistors 300. In some embodiments, device layer 710 may include fin transistors, nanostructure transistors (e.g., gate all-ring field-effect transistors (GAAFETs)), and the like.

[0226] Substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, or similar, and may be doped (e.g., p-type or n-type dopant) or undoped. The semiconductor material of substrate 110 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; other compound semiconductors including gallium, zinc, indium, and / or oxygen; or combinations thereof. Other substrates may be used, such as single-layer substrates, multilayer substrates, or gradient substrates.

[0227] The planar transistor 300 includes a source / drain 82P and a gate structure 200P, which can be formed on and within a well 850 in the substrate 110.

[0228] The source / drain 82P can be a heavily doped region of the substrate 110 within the well 850, doped with impurities to form an n-type semiconductor (with donor impurities such as phosphorus or arsenic) for NMOS, or a p-type semiconductor (with acceptor impurities such as boron) for PMOS. Between the multiple source / drain regions 82P is a channel lightly doped with the opposite type of impurity. For example, an NMOS may have a p-type channel (e.g., with boron), and a PMOS may have an n-type channel (e.g., with phosphorus). In some embodiments, the source / drain 82P is doped with carbon.

[0229] The gate structure 200P may be or include polycrystalline silicon (“polycrystalline silicon”) or a metal such as tungsten. The gate structure 200P may include an insulating layer or “gate dielectric”, which may be or include silicon dioxide (SiO2) or a high dielectric constant dielectric, such as hafnium oxide (HfO2), which is beneficial for reducing leakage and improving performance.

[0230] Although not in Figure 2AThe contact is depicted separately, but multiple contacts may exist providing electrical connections to the source / drain 82P and the gate structure 200P. The contacts may include tungsten (W), aluminum (Al), or another suitable conductive material. The contacts may include one or more barrier layers (e.g., titanium nitride) and an adhesion layer (which can be used to improve physical contact and reduce diffusion).

[0231] The front interconnect structure 700 is located on the gate structure 200P, source / drain 82P, and substrate 110. The front interconnect structure 700 may include a plurality of conductive features 730 embedded within a dielectric layer 720. For example, the front interconnect structure 700 may include one or more metal layers (e.g., M0, M1, M2, ..., MN), each of which includes a dielectric layer 720, which may be an intermetallic dielectric (IMD) layer. Each IMD layer may be or include one or more of silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiOxCy), spin-on glass (SOG), or combinations thereof. The plurality of conductive features 730 may be interconnected via conductive vias 740. For example, the first conductive feature 730A may be connected to the second conductive feature 730B via a conductive via 740. The conductive features 730, 730A, 730B and the conductive via 740 may be or include one or more of the following: metals (e.g., copper, aluminum, tin, TaN, Ta), graphene, carbon nanotubes, conductive polymers, combinations thereof, and the like.

[0232] The resistive random access memory (RAM) device 20 may be located between two or more metal layers. For example, the resistive RAM device 20 may be located between a third metal layer (M3) and a fourth metal layer (M4). In some embodiments, the resistive RAM device 20 is located between two metal layers that are more than one level apart. For example, the resistive RAM device 20 may be located between a fourth metal layer (M4) and a sixth metal layer (M6) or a seventh metal layer (M7).

[0233] exist Figure 2B In this configuration, the resistive random access memory device 20 is located within the back-side interconnect structure 800. The back-side interconnect structure 800 is similar in many respects to... Figure 2A The front interconnect structure 700 can be formed on the front side of the device layer 710A, but it can also be formed on the back side of the device layer 710A. For example, as in Figure 2AAs depicted, the substrate 110 can be partially or completely removed, and the source / drain 82 can be contacted from the back side. The back-side interconnect structure 800 may include a plurality of conductive features 820 embedded within the dielectric layer 810. Figure 2B The diagram depicts a front-side interconnect structure 700A. The front-side interconnect structure 700A is similar in most respects to the front-side interconnect structure 700 and includes a plurality of conductive features 730 embedded within a dielectric layer 720. The plurality of conductive features 730 are electrically connected to the gate structure 200 via conductive features 210. In some embodiments, a semiconductor layer 900 is located on the front-side interconnect structure 700A opposite to the device layer 710A. The semiconductor layer 900 may be undoped silicon.

[0234] Figure 2B Device layer 710A is also depicted, which includes nanostructured devices 80 instead of planar devices 300. A single nanostructured device 80 is described below. The nanostructured device 80 may be or include one or more N-type field-effect transistors (NFETs) or P-type field-effect transistors (PFETs). Multiple nanostructured devices 80 may be separated from each other (e.g., physically and / or electrically isolated) via shallow trench isolation (STI), deep trench isolation (DTI), local oxidation of silicon (LOCOS), or similar methods.

[0235] Nanostructure device 80 is formed above and / or within substrate 110, and typically includes a gate structure 200 that spans and / or surrounds multiple semiconductor channels or multiple nanostructures 22. Gate structure 200 controls the current flowing through channels 22.

[0236] The nanostructure device 80 is shown as comprising four channels 22 laterally adjacent to the source / drain feature or source / drain region 82 and covered and surrounded by a gate structure 200. Typically, the number of channels 22 is two or more, such as three or four or more. Based on the voltage applied at the gate structure 200 and at the source / drain feature 82, the gate structure 200 controls the flow of current through the channels 22 into and out of the source / drain feature 82.

[0237] In some embodiments, the nanostructured device includes an NFET, whose source / drain feature 82 includes silicon-phosphorus (SiP), SiAs, SiSb, SiPAs, SiP:As:Sb, combinations thereof, or the like. In some embodiments, the nanostructured device 20 includes a PFET, and its source / drain feature 82 includes silicon-germanium (SiGe), which may be undoped or doped to form, for example, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or another suitable semiconductor material. Typically, the source / drain feature 82 may include any combination of a suitable semiconductor material and a suitable dopant.

[0238] Each of the multiple channels 22 comprises a semiconductor material, such as silicon or a silicon compound, like silicon germanium, or the like. The channels 22 are nanostructures (e.g., in the size range of a few nanometers) and may each have an elongated shape and extend in the X direction. In some embodiments, each channel 22 has a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of the channel 22 may be rectangular, circular, square, elliptical, hexagonal, or a combination thereof.

[0239] In some implementations, the lengths of the channels 22 (e.g., measured in the X direction) may differ from one another, for example, due to tapering during the fin etching process. The channels 22 may not have a uniform thickness (e.g., along the X-axis), for example, due to channel trimming processes used to increase the spacing between the channels 22 (e.g., measured in the Z-axis) to increase the gate structure fabrication process window. For example, the middle portion of each channel 22 may be thinner than its two ends. Such shapes may be collectively referred to as "dog bone" shapes.

[0240] In some embodiments, the spacing between the plurality of channels 22 in the vertical direction ranges from about 8 nanometers (nm) to about 12 nanometers. In some embodiments, the thickness of each of the plurality of channels 22 (e.g., measured in the Z direction) ranges from about 5 nanometers to about 8 nanometers. In some embodiments, the width of each of the plurality of channels 22 (e.g., measured in the Y direction) is at least about 8 nanometers.

[0241] Gate structures 200 are disposed above and between a plurality of channels 22. In some embodiments, the gate structure 200 is disposed above and between the plurality of channels 22, which are silicon channels for N-type devices or silicon-germanium channels for P-type devices. In some embodiments, the gate structure 200 includes an interfacial layer (IL), one or more gate dielectric layers, one or more work function tuning layers, and a metal core layer.

[0242] The interface layer may be an oxide of the material of channel 22, formed on the exposed region of channel 22. The interface layer promotes adhesion between the gate dielectric layer and channel 22. In some embodiments, the interface layer has a thickness of about 5 angstroms to about 50 angstroms. In some embodiments, the interface layer has a thickness of about 10 angstroms. An interface layer that is too thin may result in voids or insufficient adhesion. An interface layer that is too thick will consume the gate fill window, which is related to threshold voltage tuning and resistance. In some embodiments, the interface layer is doped with dipoles, such as lanthanum, for threshold voltage tuning.

[0243] In some embodiments, the gate dielectric layer includes at least one high-dielectric-constant gate dielectric material, which may refer to a dielectric material having a higher dielectric constant than that of silicon oxide (k≈3.9). Examples of high-dielectric-constant dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer has a thickness of about 5 angstroms to about 100 angstroms. The gate dielectric layer may be a single layer or multiple layers formed on an interface layer.

[0244] The gate structure 200 also includes a metal core layer on the gate dielectric layer. The metal core layer may include a conductive material, such as Co, W, Ru, combinations thereof, or the like. In some embodiments, the metal core layer is or includes a compound or alloy based on Co, W, or Ru, comprising one or more elements, such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, or the like. Between the plurality of channels 22, the metal core layer is circumferentially surrounded by one or more work function metal layers (in the cross-sectional view), then the work function metal layers are circumferentially surrounded by the gate dielectric layer, which is circumferentially surrounded by an interface layer. The gate structure 200 may also include an adhesive layer formed between the one or more work function layers and the metal core layer to increase adhesion. For simplicity, in Figure 2B The adhesive layer is not specifically depicted in the drawing.

[0245] The nanostructure device 80 may include gate spacers 41 and internal spacers 74. Gate spacers 41 are disposed on multiple sidewalls of the metal core layer, gate dielectric layer, and interface layer above the uppermost channel 22. Internal spacers 74 are disposed on multiple sidewalls of the interface layer and / or gate dielectric layer between the multiple channels 22. Internal spacers 74 are also disposed between the multiple channels 22. Figure 2B In the embodiments depicted, the gate spacer 41 comprises two spacer layers. In some embodiments, the gate spacer 41 comprises a single spacer layer or three or more spacer layers. The first and second spacer layers may each comprise a dielectric material, such as a low-dielectric-constant material, such as SiOCN, SiON, SiN, SiCN, SiOC, or the like. In some embodiments, the second spacer layer is absent. The materials of the first and second spacer layers may be the same or different from each other. Typically, the upper portion of the second spacer layer (or the first spacer layer when the second spacer layer is absent) may be partially or completely removed to increase the aspect ratio of the opening through which the source / drain region 82 is formed.

[0246] The source / drain 82 can be contacted from the back side of the device layer 710A via a conductive back-side via 840. The back-side via 840 can contact one or more source / drains 82 and conductive features 820 in the back-side metal layer (e.g., "BM0", "BM1", or similar).

[0247] The resistive random access memory (RAM) device 20 may be located between two back metal layers, for example, between a second back metal layer (BM2) and a third or fourth back metal layer (BM3, BM4). A conductive via 830 may extend adjacent to the resistive RAM device 20 and may connect conductive features 820A of the metal layer above the resistive RAM device 20 to conductive features 820B of the metal layer below the resistive RAM device 20. In this description, "above" and "below" may refer to the orientation of the page and are interchangeable based on the orientation of the integrated circuit device 10A. That is, when the back side of the integrated circuit device 10A is facing upwards, as in... Figure 2B As described, conductive feature 820A is "superior" to conductive feature 820B.

[0248] In some embodiments, conductive feature 820B is a power rail of back-side interconnect structure 800. Back-side interconnect structure 800 may include at least two power rails 820B, 820C. A first power rail 820C is connected to multiple logic devices (e.g., transistors 80), and a second power rail 820B is connected to resistive random access memory (RAM) device 20. The size of the first power rail 820C may be equal to or smaller than the size of the second power rail 820B. For example, the second power rail 820B used to drive the resistive RAM device 20 may carry a voltage exceeding that carried by the first power rail 820C. A larger size of the second power rail 820B may improve reliability under higher voltages carried thereon. In some embodiments, power rails 820B, 820C are or include W, Ru, Ir, Mo, or the like.

[0249] Reference Figures 1A to 2B In the various embodiments described, contact 194 (via the bit line BL connecting electrode layer 162 to transistor 260) is connected to the upper metal layer. In some embodiments, this is not the case. Figure 2A and Figure 2B Instead of connecting to the upper metal layer as depicted, contacts 194 can be formed before the resistive random access memory device 20 is formed, allowing electrode layer 162 to connect to the lower metal layer. In such an embodiment, the connection to the upper metal layer can be omitted. Figure 1E The operations described in the document.

[0250] Figures 3A to 3T These are views of various embodiments of the resistive random access memory device 40 at various stages of manufacturing, according to various aspects of this disclosure. Figure 3U This is a circuit diagram of a resistive random access memory device 40. Figure 4A and Figure 4B These are schematic cross-sectional views of various embodiments of the integrated circuit devices 10, 10A according to various aspects of this disclosure. Figure 6 This is a flowchart of a method 2000 for forming an integrated circuit device according to various embodiments.

[0251] Figure 6A flowchart illustrating a method 2000 for forming an integrated circuit device or part of an integrated circuit device from a workpiece, according to one or more aspects of this disclosure, is provided. Method 2000 is merely one embodiment and is not intended to limit this disclosure to the content explicitly illustrated in method 2000. Additional actions may be provided before, during, and after method 2000, and some described actions may be replaced, deleted, or moved for additional embodiments of this method. For simplicity, not all actions are described in detail herein. Method 2000 is described below in conjunction with partial perspective and / or cross-sectional views of a workpiece at different manufacturing stages according to various embodiments of method 2000, as shown in... Figures 3A to 3T As shown in the figures. To avoid ambiguity, in all figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X and Y directions. Note that because the workpiece can be manufactured as a semiconductor device, it may be referred to as a semiconductor device depending on the context.

[0252] exist Figures 3A to 3T In this method, a fuse device 38 is formed before the transistors forming the resistive random access memory device 40. Some operations of method 2000 are similar in many respects to... Figure 5 The method 1000 is described in detail, and a relevant description will be provided for reference.

[0253] exist Figure 3A In this process, the first dielectric layer 360 is formed, which in most respects is similar to... Figure 1A The first dielectric layer 160 is similar. After the formation of the first dielectric layer 360, an opening 37 can be formed in the first dielectric layer 360, in which a fuse device 38 will be formed. Before the formation of the first dielectric layer 360, a device layer of the integrated circuit device 10 can be formed, as referenced above. Figure 1A , Figure 2A and Figure 2B This corresponds to action 2010 of method 2000. Then, corresponding to action 2020 of method 2000, a first portion of the interconnect structure can be formed on the device layer. That is, the resistive random access memory device 40 can be formed on a metal layer of the interconnect structure.

[0254] exist Figures 3B to 3E In the process of forming an opening 37 in the first dielectric layer 360, a fuse device 38 is formed on the first dielectric layer 360, including the opening 37, corresponding to operation 2030 of method 2000. The fuse device 38 may be a memristor and may include one or more of the following layers: a bottom electrode, an active or switching layer (insulator), a blocking or buffering or ion-conducting layer (optional), a top electrode, a passivation layer (optional), and an encapsulation (optional).

[0255] exist Figure 3BIn this process, multiple material layers used to form the fused wire device 38 can be deposited sequentially as a blanket-covered conformal layer.

[0256] First, a top electrode 386 may be formed, comprising a transition metal nitride (e.g., TiN) or another conductive material. The top electrode 386 may be formed via a suitable deposition operation, such as atomic layer deposition, chemical vapor deposition, or similar.

[0257] After the top electrode 386 is formed, an optional barrier, buffer, or ion-conducting layer 384L may be formed. The optional layer 384L may be a layer of titanium. The titanium layer may be formed by a suitable deposition operation on the top electrode 386, such as by atomic layer deposition, chemical vapor deposition, or similar methods.

[0258] Following the formation of the optional ion-conducting layer 384L or the top electrode 386, an active or switching layer 382L may be formed. The switching layer 382L may be a high-dielectric-constant dielectric layer and may include at least one of a variety of dielectric materials having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-dielectric-constant dielectric materials include TiO2, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof (e.g., multilayers). The switching layer 382L may be formed via a suitable deposition operation, such as atomic layer deposition, chemical vapor deposition, or the like.

[0259] After the formation of the switching layer 382L, a bottom electrode layer 380L may be formed. The bottom electrode layer 380L may include a transition metal nitride, such as TiN, or another conductive material. The bottom electrode layer 380L may be formed via a suitable deposition operation, such as atomic layer deposition, chemical vapor deposition, or the like. In some embodiments, the bottom electrode layer 380L is made of the same or substantially the same material as the top electrode 386.

[0260] exist Figure 3C In this process, a masking layer 370 is formed on multiple layers 380L, 382L, 384L, and 386, as shown in the figure. The masking layer 370 is, in most respects, similar to... Figure 1D The mask layer is 170.

[0261] exist Figure 3D In this process, multiple portions of the masking layer 370 above the opening 37 are removed via a suitable removal operation (e.g., chemical mechanical planarization). After chemical mechanical planarization, the upper surface of the bottom electrode layer 380L outside the opening 37 is exposed.

[0262] exist Figure 3EIn this process, the electrode contact portion 386C of the exposed top electrode 386 can be exposed by a suitable etching operation. For example, a patterned mask can be formed covering the top electrode 386 and the mask layer 370 and having openings corresponding to the electrode contact portion 386C. Multiple exposed portions of the bottom electrode layer 380L, the switching layer 382L, and the optional ion-conducting layer 384L can be etched using the patterned mask, as shown in the reference. Figure 1I The described content. The exposed electrode contact portion 386C results in the formation of the bottom electrode 380, switching layer 382, ​​and optional ion conduction layer 384 of the fuse device 38 as shown in the figure.

[0263] exist Figure 3F In the process of exposing the electrode contact portion 386C, a second dielectric layer 372L is formed on the electrode contact portion 386C in the opening 37, the bottom electrode 380, and the masking layer 370. The second dielectric layer 372L is similar in most respects to the reference layer. Figure 1A The first dielectric layer 160 is described.

[0264] exist Figure 3G In the process, after the formation of the second dielectric layer 372L, a suitable removal operation (e.g., chemical mechanical planarization) is performed to remove multiple portions of the second dielectric layer 372L from above the bottom electrode 380, leaving the second dielectric layer 372B above the electrode contact portion 386C. After chemical mechanical planarization, the multiple upper surfaces of the second dielectric layer 372B, the bottom electrode 380, and the masking layer 370 can be coplanar.

[0265] exist Figure 3H In this process, after planarizing the second dielectric layer 372B, the bottom electrode 380, and the masking layer 370, an insulating layer 374L can be formed on multiple planarized upper surfaces of the second dielectric layer 372B, the bottom electrode 380, and the masking layer 370. The insulating layer 374L is similar in most respects to the reference layer. Figure 1G The insulating layer 174 is described. The insulating layer 374L provides electrical and physical isolation between the fuse device 38 and the gate electrode layer 368 formed in subsequent operations.

[0266] exist Figures 3I to 3K In the middle, corresponding to action 2040 of method 2000, an oxide semiconductor channel 364 is formed on the fuse device 38.

[0267] exist Figure 3I An opening 35 is formed extending through the insulating layer 374. The opening 35 is extended by removing the masking layer 370. Figure 3IIn this embodiment, the insulating layer 374 exposed by the opening 35 and the plurality of sidewalls of the bottom electrode 380 are substantially coplanar in the vertical direction. In some embodiments, the sidewalls of the insulating layer 374 are positioned slightly rearward from the sidewalls of the bottom electrode 380, such that at least a portion of the upper surface of the bottom electrode 380 is exposed by the opening 35. The formation of the opening 35 may include a first etching that penetrates through the insulating layer 374, followed by a second etching that removes the masking layer 370. The first etching may be anisotropic etching, such as reactive ion etching or inductively coupled plasma etching through a patterned mask. The second etching may be anisotropic or isotropic, such as reactive ion etching, inductively coupled plasma etching, wet etching, or other suitable etching that is selective to the material of the masking layer 370 and substantially does not corrode the material of the insulating layer 374. The outline of the opening 35 in the XY plane may be any suitable shape, such as circular, square, rectangular, or similar.

[0268] exist Figure 3J In the process, after the formation of opening 35, an oxide semiconductor layer 364L is formed in opening 35 and on insulating layer 374. The oxide semiconductor layer 364L is similar in most respects to the reference layer. Figure 1A The oxide semiconductor layer 164L is described and may be or include IGZO or another suitable oxide semiconductor.

[0269] exist Figure 3K In the process, after the formation of the oxide semiconductor layer 364L, the oxide semiconductor layer 364L is patterned to create a channel 364, as shown in the figure. The channel 364 may include a lower portion and an upper portion, the lower portion being below the upper surface of the insulating layer 374 and in contact with the fuse device 38, and the upper portion protruding above the insulating layer 374. The width of the upper portion in the X-axis direction may exceed the width of the lower portion in the X-axis direction. For example, the upper portion may partially cover the upper surface of the insulating layer 374. The lower portion may inherit the shape of the opening 35. The upper portion may have the same or different shape as the lower portion (e.g., cross-sectional profile in the XY plane). For example, the lower portion may have a rectangular shape, while the upper portion may have a circular shape.

[0270] exist Figures 3L to 3P In the middle, the adjacent channel 364 forms a gate structure 36, corresponding to the operation 2050 of method 2000.

[0271] exist Figure 3L In this configuration, a gate dielectric layer 366L and a gate conductive layer 368L are formed on the upper portion of channel 364. The formation of the gate dielectric layer 366L and the gate conductive layer 368L is similar in most respects to that of the reference configuration. Figure 1CThe formation of the gate dielectric layer 166L and the gate conductive layer 168L is described. The gate dielectric layer 366L may cover the upper surface of the channel 364 and multiple sidewalls, as well as the upper surface of the insulating layer 374. The gate conductive layer 368L covers the gate dielectric layer 366L.

[0272] exist Figure 3M In this process, the gate conductive layer 368L and the gate dielectric layer 366L are patterned to remove multiple portions that overlap with the electrode contact portion 386C of the top electrode 386, and to expose multiple portions 33 of the upper surface of the insulating layer 374. The gate conductive layer 368L' and the gate dielectric layer 366L' are formed by removing multiple portions that overlap with the electrode contact portion 386C.

[0273] exist Figure 3N In this process, a third dielectric layer 392L is formed to cover the gate conductive layer 368L' and the insulating layer 374. The formation of the third dielectric layer 392L is similar in most respects to that of the reference layer. Figure 1A The formation of the oxide layer 160 as described.

[0274] exist Figure 3O In this process, the third dielectric layer 392L is recessed to form the third dielectric layer 392 and exposes multiple portions of the gate conductive layer 368L' and the gate dielectric layer 366L'. As shown, the upper surface of the third dielectric layer 392 may be lower than multiple upper surfaces of the channel 364, the gate dielectric layer 366L', and the gate conductive layer 368L'. This is advantageous because, after the formation of the second insulating layer 393, at least a portion of the channel 364 may protrude above the second insulating layer 393 for forming the electrode layer 395L thereon.

[0275] exist Figure 3P In this process, multiple exposed portions of the gate conductive layer 368L' and the gate dielectric layer 366L' above the third dielectric layer 392L are removed. After the removal of the multiple exposed portions, the gate electrode layer 368 and the gate dielectric layer 366 are retained. Then, a second insulating layer 393 is formed. The second insulating layer 393 may be similar in most respects to the reference. Figure 1G and Figure 3H The insulating layers 174 and 374 are described. The second insulating layer 393 may be deposited as a conformal layer covering the channel 364 and the third dielectric layer 392. Then, multiple portions of the second insulating layer 393 on the upper surface of the channel 364 may be removed to obtain the structure depicted in Figure 3P.

[0276] exist Figure 3Q In this process, after the formation of the second insulating layer 393, an electrode layer 395L may be formed on multiple exposed surfaces of the channel 364 and the second insulating layer 393. The electrode layer 395L may be similar in most respects to the reference [reference]. Figure 1AThe first electrode layer 162 is described.

[0277] exist Figure 3R In this process, electrode layer 395L is patterned to form electrode layer 395, thereby obtaining the structure shown. Electrode layer 395 is in contact with the upper surface of channel 364 and may contact portions of multiple sidewalls of channel 364 that protrude above the second insulating layer 393. Multiple horizontal portions of electrode layer 395 are on the upper surface of second insulating layer 393.

[0278] exist Figure 3S and Figure 3T In the process, corresponding to action 2060 of method 2000, word line contacts, bit line contacts, and ground contacts are formed, which are connected to the gate structure, source / drain, and fuse device of the resistive random access memory device. Figure 3U This is a circuit diagram of a resistive random access memory device 40 according to various embodiments. The resistive random access memory device 40 includes a transistor 460 and a resistor 470.

[0279] exist Figure 3S In this configuration, a fourth dielectric layer 352 is formed over the electrode layer 395 and the second insulating layer 393. The fourth dielectric layer 352 can, in most respects, be similar to the reference layers 395 and 393, respectively. Figure 1A and Figure 1L The first dielectric layer 160 and dielectric layer 500 are described.

[0280] exist Figure 3T Multiple contacts 394, 396, and 398 are formed in the structure. Contact 394 is connected to electrode layer 395, which may be the drain electrode of transistor 460 (including channel 364). Contact 396 extends through fourth dielectric layer 352, second insulating layer 393, third dielectric layer 392, insulating layer 374, and second dielectric layer 372B, and is connected to electrode contact portion 386C of top electrode 386. Contact 398 extends through fourth dielectric layer 352, second insulating layer 393, and third dielectric layer 392, and is connected to gate conductive layer 368. Contacts 394, 396, and 398 are similar in most respects to the reference design. Figure 1N The contacts 194, 196, and 198 are described. After the formation of contacts 394, 396, and 398, a second part of the interconnection structure can be formed on contacts 394, 396, and 398, corresponding to action 2070 of method 2000.

[0281] Figure 4A and Figure 4B This is a schematic cross-sectional view of integrated circuit devices 10 and 10A, including resistive random access memory device 40. Integrated circuit devices 10 and 10A are similar in most respects to reference [reference image]. Figure 2B , Figure 2A The described integrated circuit devices 10 and 10A do not include resistive random access memory device 20, but include resistive random access memory device 40. Resistive random access memory device 40 may be located in front interconnect structure 700 or back interconnect structure 800, or both.

[0282] Multiple implementations offer multiple advantages. The resistive random access memory devices 20, 40 have grounded resistors (or memristors) stacked on the source / drain, which reduces the area of ​​the resistive random access memory devices 20, 40 and increases the device density.

[0283] According to at least one embodiment, a memory device includes: a device layer; and an interconnect structure on the device layer, the interconnect structure including a resistive random access memory (RRAM) device. The resistive RRAM device includes: an electrode layer above the device layer; an oxide semiconductor layer on the electrode layer; a gate structure surrounding the oxide semiconductor layer; an insulating layer on the gate structure; and a resistor. The resistor includes: a bottom electrode on the oxide semiconductor layer; a dielectric layer on the bottom electrode; and a top electrode on the dielectric layer.

[0284] In some implementations, the memory device further includes a first contact, a second contact, and a third contact.

[0285] The first contact extends through the insulating layer and then onto the electrode layer. The second contact then onto the top electrode.

[0286] The third contact extends through the insulating layer and then onto the gate structure.

[0287] In some embodiments, the resistive random access memory device further includes at least one spacer on a plurality of sidewalls of the top electrode.

[0288] In some embodiments, in a memory device, at least one spacer includes an upper spacer and a lower spacer. The upper spacer is located on multiple sidewalls of the top electrode. The lower spacer is located on multiple sidewalls of the top electrode, the dielectric layer, and the bottom electrode, and on the upper surface of the insulating layer.

[0289] In some embodiments, the resistive random access memory device includes an oxygen storage layer between a dielectric layer and a top electrode.

[0290] In some implementations, in the memory device, the resistive random access memory device has a pointed profile in a cross-sectional side view.

[0291] In some implementations, in the memory device, the resistive random access memory device has an M-shaped profile in a cross-sectional side view.

[0292] According to at least one embodiment, a memory device includes: a device layer; and an interconnect structure on the device layer, the interconnect structure including a resistive random access memory (RRAM) device. The resistive RRAM device includes a resistor, the resistor including: a top electrode above the device layer; a dielectric layer on the top electrode; and a bottom electrode on the dielectric layer. The resistive RRAM device further includes: an oxide semiconductor layer on the bottom electrode; a first insulating layer on the resistor; a gate structure on the first insulating layer, the gate structure surrounding the oxide semiconductor layer; a second insulating layer on the gate structure; and an electrode layer on the oxide semiconductor layer above the gate structure.

[0293] In some embodiments, the memory device further includes a first contact, a second contact, and a third contact. The first contact extends through a first insulating layer and a second insulating layer and is connected to a top electrode. The second contact is connected to an electrode layer. The third contact extends through a second insulating layer and is connected to a gate structure.

[0294] In some embodiments, in the memory device, the interconnect structure includes a second dielectric layer and an opening in the second dielectric layer; and the top electrode, bottom electrode, dielectric layer, and oxide semiconductor layer of the resistive random access memory device extend into the opening.

[0295] In some embodiments, in a memory device, a second portion of the oxide semiconductor layer above the opening has a width that exceeds the width of the first portion of the oxide semiconductor layer in the opening.

[0296] In some implementations, the resistive random access memory device includes an oxygen storage layer between a dielectric layer and a top electrode.

[0297] In some embodiments, the memory device further includes a second interconnect structure on the front side of the device layer. The interconnect structure is a back-side interconnect structure located on the back side of the device layer opposite to the front side.

[0298] In some embodiments, in the memory device, the device layer includes a nanostructured transistor comprising a stack of multiple nanostructured channels and a source / drain; and the interconnect structure includes a first power rail and a second power rail. The first power rail is connected to the source / drain. The second power rail is on the first power rail and connected to the resistive random access memory device, and the second power rail has a dimension that exceeds that of the first power rail.

[0299] According to at least one embodiment, a method of manufacturing a memory device includes: forming a device layer on a substrate; forming a first portion of an interconnect structure on the device layer; and forming a resistive random access memory (RRAM) device on the first portion, including: forming an oxide semiconductor layer; forming a gate structure surrounding the oxide semiconductor layer; and forming a resistor, wherein the resistor and the oxide semiconductor layer are stacked in a vertical direction. The method further includes forming a second portion of the interconnect structure on the resistive random access memory device.

[0300] In some embodiments, in the method of manufacturing a memory device, a resistor is formed after an oxide semiconductor layer is formed.

[0301] In some embodiments, forming a resistor in a method of manufacturing a memory device includes: forming a bottom electrode on an oxide semiconductor layer; forming a switching layer on the bottom electrode; and forming a top electrode on the switching layer.

[0302] In some embodiments, in a method of manufacturing a memory device, forming a resistor includes forming a bottom electrode, a switching layer, and a top electrode with a pointed profile in a cross-sectional side view.

[0303] In some embodiments, in a method of manufacturing a memory device, forming a resistor includes forming a bottom electrode, a switching layer, and a top electrode having an M-shaped profile in a cross-sectional side view.

[0304] In some embodiments, in the method of manufacturing a memory device, the first part of forming the interconnect structure is the first part of forming the back-side interconnect structure, and the method further includes forming a front-side interconnect structure before the first part of forming the interconnect structure.

[0305] In some embodiments, a memory device includes: a device layer and an interconnect structure on the device layer, the interconnect structure including a resistive random access memory (RRAM) device. The resistive RRAM device includes a resistor comprising: a top electrode above the device layer, a dielectric layer on the top electrode, and a bottom electrode on the dielectric layer. The resistive RRAM device further includes: an oxide semiconductor layer on the bottom electrode, a first insulating layer on the resistor, a gate structure on the first insulating layer, a second insulating layer on the gate structure, an electrode layer on the oxide semiconductor layer above the gate structure, and an oxygen storage layer between the dielectric layer and the top electrode. The gate structure surrounds the oxide semiconductor layer.

[0306] The foregoing outlines several features of various embodiments, enabling those skilled in the art to better understand the multiple variations of this disclosure. Those skilled in the art should understand that they may readily use this disclosure as the basis for the design or modification of other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, characterized in that, Include: One device layer; as well as An interconnect structure, on the device layer, includes a resistive random access memory (RAM) device, the resistive RAM device comprising: An electrode layer, higher than the device layer; An oxide semiconductor layer is disposed on the electrode layer; A gate structure surrounds the oxide semiconductor layer; An insulating layer is present on the gate structure; and A resistor, comprising: A bottom electrode is located on the oxide semiconductor layer; A dielectric layer on the bottom electrode; and A top electrode is located on the dielectric layer.

2. The memory device as claimed in claim 1, characterized in that, Also includes: A first contact extends through the insulating layer and is attached to the electrode layer; A second contact, which then rests on the top electrode; and A third contact extends through the insulating layer and then onto the gate structure.

3. The memory device as claimed in claim 1, characterized in that, The resistive random access memory device also includes: At least one spacer is located on one of the sidewalls of the top electrode.

4. The memory device as claimed in claim 1, characterized in that, The resistive random access memory device includes: An oxygen storage layer is located between the dielectric layer and the top electrode.

5. The memory device as claimed in claim 1, characterized in that, The resistive random access memory device has a pointed profile in a cross-sectional side view.

6. A memory device, characterized in that, Include: One device layer; as well as An interconnect structure, on the device layer, includes a resistive random access memory (RAM) device, the resistive RAM device comprising: A resistor, comprising: A top electrode, above the device layer; A dielectric layer on the top electrode; and A bottom electrode is located on the dielectric layer. An oxide semiconductor layer is placed on the bottom electrode; A first insulating layer is applied to the resistor; A gate structure is provided on the first insulating layer, the gate structure surrounding the oxide semiconductor layer; A second insulating layer is disposed on the gate structure; and An electrode layer is located on the oxide semiconductor layer above the gate structure.

7. The memory device as claimed in claim 6, characterized in that: The interconnect structure includes a second dielectric layer and an opening in the second dielectric layer; and The top electrode, the bottom electrode, the dielectric layer, and the oxide semiconductor layer of the resistive random access memory device extend into the opening.

8. The memory device as claimed in claim 7, characterized in that, A second portion of the oxide semiconductor layer above the opening has a width that exceeds the width of a first portion of the oxide semiconductor layer in the opening.

9. The memory device as claimed in claim 6, characterized in that, Also includes: A second interconnect structure is located on a front side of the device layer; The interconnect structure is a back-side interconnect structure located on the back side of the device layer opposite to the front side.

10. A memory device, characterized in that, Include: One device layer; as well as An interconnect structure, on the device layer, includes a resistive random access memory (RAM) device, the resistive RAM device comprising: A resistor, comprising: A top electrode, above the device layer; A dielectric layer on the top electrode; and A bottom electrode is located on the dielectric layer. An oxide semiconductor layer is placed on the bottom electrode; A first insulating layer is present on the resistor; A gate structure is provided on the first insulating layer, the gate structure surrounding the oxide semiconductor layer; A second insulating layer is provided on the gate structure; An electrode layer is disposed on the oxide semiconductor layer above the gate structure; and An oxygen storage layer is located between the dielectric layer and the top electrode.

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