Electronic system

Abstract

An electronic system has a mounting substrate with a plurality of layers. The mounting substrate includes a plurality of layers having pad structures, each configured to have a pad within an anti-pad opening. The pad structures are connected with the via holes. The pad structure is configured to reduce the impedance of the via by changing the shape, size, and position of the pad and anti-pad openings. The pads of the pad structure are configured as functional pads and non-functional pads based on impedance targets of the vias.

Description

Technical Field

[0001] The embodiments generally relate to electrical structures for improving performance in electronic circuit packages having ball grid array structures, and more specifically, to electrical printed circuit boards having layer-by-layer anti-pad structures for improving performance and reducing inductance, and methods of manufacturing them. Background Technology

[0002] The methods described in this section are permissible but not necessarily methods that have been previously conceived or employed. Therefore, unless otherwise indicated, no method described in this section should be considered prior art simply by virtue of its inclusion in this section.

[0003] The development of electronic systems and products is influenced by the physical and electrical properties of the materials and structures used to form electronic components and circuits.

[0004] Electronic components must be electrically connected to other electronic components and systems for proper operation. Electronic components can be mounted on multilayer circuit boards and electrically coupled to power distribution networks with vertical vias, signal traces, power traces, and ground traces. The size, shape, power level, and electrical parameters of electronic components can affect operational performance.

[0005] The electrical characteristics of electronic and power distribution components can affect the electrical operating characteristics of circuits and negatively lead to instability, oscillations, signal leakage, reflections, frequency variations, and other unintended effects. Reducing the effects of such electrical configurations can mitigate these adverse effects and improve the overall efficiency of circuit operation. Utility Model Content

[0006] This disclosure provides an electronic system comprising: a mounting substrate having at least a first layer and a second layer; a first pad structure having a first pad within a first anti-pad opening, the first pad structure being on the first layer; a second pad structure having a second pad within a second anti-pad opening, the second pad structure being on the second layer, and the second layer being on the first layer; and a via electrically coupled to the first pad and the second pad.

[0007] In some embodiments, the first pad structure includes a first pad having a circular pad shape and a first anti-pad opening having a rectangular shape, wherein the first pad and the first anti-pad opening are offset by a pad gap offset distance on the nearest side.

[0008] In some embodiments, the first pad structure includes a first pad having a circular pad shape and a first anti-pad opening having a circular shape, wherein the first pad and the first anti-pad opening are offset by a pad gap offset distance on the nearest side.

[0009] In some implementations, the second pad structure includes a second antipad shape that differs from the shape of the first antipad.

[0010] In some embodiments, it further includes a second via within the opening of the first antipad.

[0011] In some embodiments, it further includes an intermediate substrate layer between the first layer and the second layer.

[0012] In some implementations, the intermediate substrate layer includes a non-functional pad directly between the first pad and the second pad.

[0013] In some embodiments, the intermediate substrate layer is a third pad structure having a third pad and a third anti-pad opening.

[0014] In some embodiments, the intermediate substrate layer includes a third pad structure having a third pad and a third antipad opening, and the third antipad opening has a third antipad shape that is different from the first antipad opening.

[0015] In some embodiments, the intermediate substrate layer includes a third pad structure having a third pad and a third anti-pad opening, and vias are electrically coupled to the third pad and the first pad. Attached Figure Description

[0016] The invention is illustrated in the accompanying drawings by way of example rather than limitation, and similar reference numerals refer to similar elements, and in the drawings:

[0017] Figure 1 An example embodiment of the electronic system is described.

[0018] Figure 2 An example of a mounting substrate in an embodiment of an electronic system is depicted.

[0019] Figure 3 An example of a via pad stack 302 in an embodiment of an electronic system is depicted.

[0020] Figure 4A An exemplary embodiment of a via pad stack is depicted.

[0021] Figure 4B An example embodiment of a via-pad stack with non-functional pads is depicted.

[0022] Figure 5A An example embodiment depicting a via with a rectangular antipad and a circular via pad is shown.

[0023] Figure 5B An example embodiment depicting a via with an elliptical anti-pad and a circular via pad is shown.

[0024] Figure 5C An example embodiment depicting a via with a square antipad and a circular via pad is shown.

[0025] Figure 5D An example embodiment depicting a via with a dumbbell-shaped antipad and a circular via pad is shown.

[0026] Figure 5E An example embodiment depicting a via with a circular antipad and a circular via pad is shown.

[0027] Figure 6A An example of a mounting substrate formed of a uniform material is depicted.

[0028] Figure 6B An example of a mounting substrate formed from a hybrid material is depicted.

[0029] Figure 7 An example of a terminal time-domain reflectivity (TDR) impedance diagram for an embodiment of an electronic system is depicted.

[0030] Figure 8 An example of a terminal time-domain reflectivity impedance diagram for another embodiment of an electronic system is depicted.

[0031] Figure 9 Examples of terminal time-domain reflection impedance diagrams for other embodiments of electronic systems are depicted, and

[0032] Figure 10 An example of a manufacturing process flow for an electronic system is depicted in the embodiments. Detailed Implementation

[0033] In the following detailed description, numerous specific details are set forth for illustrative purposes in order to provide a thorough understanding of the invention. However, it will be apparent that the invention can be practiced without these specific details. In other instances, known structures and devices are illustrated in block diagram form to avoid unnecessarily obscuring the invention.

[0034] This document describes an embodiment based on the following summary:

[0035] 1.0. Overview

[0036] 2.0 System Overview

[0037] 3.0 Performance Analysis

[0038] 4.0. Function Overview

[0039] 5.0. Example Implementation

[0040] 6.0. Extensions and Alternatives

[0041] 1.0. Overview

[0042] Methods, techniques, and mechanisms for manufacturing and using the electronic systems discussed herein, including electronic systems having multilayer components and substrates, are disclosed. Electronic systems can improve performance and reduce the electrical operating factor between conductive elements by creating directional current flow structures to compensate for inductance and capacitance factors between and around components in a multilayer substrate. Operating frequency can be increased by reducing the loop inductance between various conductive elements in both the electronic package and the underlying printed circuit board.

[0043] According to an embodiment, the system may include two or more pad structures connected by vias, wherein the pad structures are configured to reduce via impedance. The pad structures may include different configurations of pads within anti-pad openings.

[0044] According to an embodiment, the system may include two or more pad structures having different configurations of pad shape, pad area, anti-pad shape, and anti-pad size.

[0045] According to an embodiment, the system may include two or more pad structures connected by vias, wherein the pad structures are configured to reduce via impedance by varying the distance between the end of the via and the placement of the pad structure.

[0046] According to another embodiment, the electrical system may include attaching electronic components to a mounting substrate. The mounting substrate may include electronic components attached to vias coupled to one or more pad structures in a pad structure to reduce via impedance and improve performance.

[0047] In other respects, the subject matter of this invention encompasses electronic systems configured to implement the aforementioned techniques.

[0048] 2.0. System Overview

[0049] Figure 1 An example embodiment of electronic system 100 is illustrated. Electronic system 100 may have electronic components 104 attached to mounting substrate 102. Mounting substrate 102 may couple electronic components 104 to other electronic components in electronic components 104 and other parts of system 100.

[0050] Electronic system 100 can be a system or a sub-module of a system. For example, electronic system 100 can be an electronic package, a printed circuit board, a motherboard, a daughterboard, a stand-alone system, or other similar systems and devices.

[0051] Electronic system 100 may include one or more electronic components 104 attached to mounting substrate 102. Mounting substrate 102 is a multilayer structure for coupling electronic components 104 to other electronic components 104 and to the remainder of electronic system 100. The layers of mounting substrate 102 may have various configurations. For example, a layer may be a combination of insulating material and conductive traces for transmitting signals or power. Electronic components 104 may be coupled to other components using signal traces 106. Signal traces 106 are conductive paths for transmitting signals and power. In another embodiment, mounting substrate 102 may be a printed circuit board 108 (PCB 108), an electronic package, or other similar element.

[0052] Mounting substrate 102 may have various types of different layers. In some embodiments, mounting substrate 102 may have layers including signal trace layers, power layers, ground plane layers, insulating layers, electromagnetic shielding layers, external connection layers, and / or other similar layers.

[0053] Electronic component 104 is a component used to provide functionality to electronic system 100. Electronic component 104 can be an active component or a passive component. For example, electronic component 104 can be an active component such as an integrated circuit, processor, field-programmable gate array, transistor, ball grid array component, or other similar active component. Electronic component 104 can be a passive component such as a resistor, capacitor, inductor, connector, interface, contact pad, or other similar passive component.

[0054] Mounting substrate 102 may include a plurality of substrate layers 110 formed of insulating and conductive materials. For example, mounting substrate 102 may include a conductive top portion formed on an insulating dielectric portion of substrate layer 110.

[0055] In an illustrative embodiment, the mounting substrate 102 may include a first layer 122, a second layer 124, a third layer 126, a fourth layer 128, a fifth layer 130, a sixth layer 132, and a seventh layer 134. In other embodiments, the mounting substrate 102 may be configured with a different number of layers.

[0056] Mounting substrate 102 can have various configurations. Mounting substrate 102 may include a top layer 142, such as a first layer 122, on the top side of mounting substrate 102. A bottom layer 144 may be on the bottom side of mounting substrate 102, such as a seventh layer 134. Mounting substrate 102 may include one or more inner layers 146 between the top and bottom sides. Mounting substrate 102 may include a ground layer 148 and a power layer 150.

[0057] The substrate layer 102 can be configured in various ways. In some embodiments, the substrate layer 102 may have a conductive layer (such as a copper layer) formed directly on a dielectric layer (such as a glass fiber or prepreg layer). The copper layer may be configured to form conductive traces for conducting signals and power to electronic components.

[0058] The substrate layer 102 can be vertically coupled to vias 110. Vias 110 are vertical conductors that can conduct signals between different layers of the mounting substrate 102. Vias 110 can be through-board vias, internal vias, blind vias, stacked vias, interleaved vias, buried vias, or other similar types of vertical interconnects.

[0059] In some embodiments, via 110 may form a vertical interconnect between two layers. This vertical interconnect may include two or more horizontally offset vertical segments electrically coupled together on an intermediate layer, such as two separate via segments offset from each other but electrically coupled at an intermediate layer between the two via segments. In an illustrative example, the vertical interconnect may include a top via segment offset from an intermediate via segment coupled to a bottom via segment. Each via segment may be a via in via 110, such as an internal via, blind via, stacked via, interleaved via, buried via, or other similar type of vertical interconnect.

[0060] Electronic component 104 can be attached to printed circuit board 108 in various ways. Electronic component 104 and other components can be electrically coupled to traces on printed circuit board 108 by mounting, soldering, pressure bonding, adhesive attachment or other similar techniques.

[0061] In other embodiments, electronic components 104, such as ball grid array packages, may be attached to mounting substrate 102. Connections to printed circuit board 108 can have various configurations. Electronic components 104 may be directly attached to printed circuit board 108, indirectly mounted in a socket, connected to another component, stacked, linked via a network connector, attached via a connector, or attached using other technologies.

[0062] The circuit configuration of electronic system 100 can produce electrical effects that can affect the performance of electronic system 100. Inductance, resistance, reactance, and capacitance are the basic elemental characteristics of all electrical systems.

[0063] Figure 2 An example of a mounting substrate 202 in an embodiment of electronic system 200 is illustrated. The mounting substrate 202 may include a plurality of traces 206 and vias 220.

[0064] Trace 206 is a conductive element used to transmit power and signals between electrical component 104 and other system components. The substrate trace 206 can be formed in various ways. For example, trace 206 can be formed by applying a mask and photolithographically etching a conductive portion of one of the layers.

[0065] Mounting substrate 202 may include vias 220 that provide vertical interconnection between two or more layers. The vias 220 may extend through one or more of the substrate layers 210.

[0066] Via 220 can be electrically coupled to a via pad 222 on a substrate layer 210. The via pad 222 can be located on the top or bottom side of a via in via 220 to provide connectivity to other components. The via pad 222 is a conductive element for connection to via 220.

[0067] Mounting substrate 202 may include various pads as conductive elements. Pads may include via pads, interface pads, contact pads, mounting pads, stack pads, and / or other similar types. The term "pad" may be used interchangeably for different types of pads.

[0068] Via 220 can be formed in various ways. In some embodiments, via 220 can be formed by drilling a via hole 226 and electroplating the inside of the via hole with a conductive material to form a via wall 224.

[0069] In some embodiments, via 220 may be electrically coupled to one or more internal pads 230 embedded in a substrate layer of mounting substrate 202. The internal pads 230 are horizontal interconnect structures that may be electrically coupled to one or more substrate traces in substrate trace 206.

[0070] In other embodiments, via 220 may be configured to operate like a transmission line depending on the frequency of the transmitted signal.

[0071] Figure 3 An example of a via pad stack 302 in an embodiment of electronic system 100 is illustrated. Vias 320 can provide electrical connections between different layers of mounting substrate 102.

[0072] In some embodiments, the top layer of the via pad stack 302 may include a top pad 382. The top pad 382 is a conductive element that can be coupled to a signal trace 106 on the top layer 142. The top pad 382 is electrically coupled to the via 320.

[0073] The via pad stack 302 may include a pad structure 310 on a layer between the top pad 382 and the bottom pad 384. The pad structure 310 may be on a single layer of the mounting substrate 102. The pad structure 310 is a conductive element for interacting with the via 320.

[0074] In some embodiments, the pad structure 310 may be in direct contact with the via 320. The pad structure 310 may also be indirectly coupled to the via 320, for example, by having conductive elements around the via 310 but not in direct contact with it.

[0075] The pad structure 310 can have various configurations. The pad structure 310 may include pads 312 formed within openings in the anti-pad 314. Pads 312 are conductive elements on one layer of the mounting substrate 102. Pads 312 can be electrically coupled to signal traces on the layers of the mounting substrate 102. Pads 312 have a pad shape 320, a pad size 324, and a pad area 332. The pad shape 320 can be configured as circular, square, rectangular, elliptical, or other shape types. The pad size 324 can be a complex value based on the pad shape 320. For example, the pad size 324 can be length and width, radius, diameter, major and minor axes, or other dimensions. The pad area 332 is the area of ​​the pad 312 calculated based on the pad size 324.

[0076] Pad structure 310 may be offset from another pad structure 310 by a distance 328, such as a first offset distance. The offset distance 328 may represent the distance between pad structure 310 and another pad structure 310 on a different layer. The offset distance 328 may represent the distance between two pad structures 310 on adjacent layers or on one or more separate layers. For example, the offset distance 328 (e.g., a second offset distance) may represent the distance between two pad structures 310 separated by two layers. The offset distance 328 may be configured to reduce the via impedance at different locations on the via 320. For example, pad structure 310 may be configured to have a first offset distance between two pad structures at equivalent layers of two separated layers with different pad structures.

[0077] In some embodiments, the layer can have multiple layer heights 330. For some high-speed PBCs, the layer height 330 can vary between 3 mils and 5 mils. The pad structure 310 can be spaced at multiples of the layer height 330. In other embodiments, the layer height 330 can be based on impedance, thickness requirements, routing factors, and other similar factors. The offset distance 328 can be fine-tuned based on the number of layers between the layer height 330 and the pad structure 310.

[0078] In some embodiments, the offset distance 328 may include one or more other pad structures 310 between the two pad structures 310 for determining the offset distance 328. In other embodiments, such a via 320 may be configured to include pad structures, functional pads, non-functional pads, layers without pad structures, or other similar configurations.

[0079] Anti-pad 314 is an opening in the conductive material of one of the layers of the mounting substrate 102. Anti-pad 314 forms a non-conductive region around pad 312. Anti-pad 314 may have anti-pad opening 370 without conductive material, and pad 312 may be located in anti-pad opening 370.

[0080] Anti-pad 314 has anti-pad shape 322, anti-pad size 326, and anti-pad area 334. Anti-pad shape 322 can be configured as circular, square, rectangular, elliptical, dumbbell-shaped, or a combination thereof. Anti-pad size 326 can have multiple values ​​based on anti-pad shape 322 and include multiple individual values. For example, anti-pad size 326 can be length and width, radius, diameter, major axis and minor axis, or other dimensions. Anti-pad area 334 is the area of ​​anti-pad 314 calculated based on anti-pad size 326.

[0081] In some embodiments, the pad structure 310 may include pads 312 configured to surround a circular pad of a via 320 and anti-pads 314 configured to be rectangular. In other embodiments, two or more pads in the pads 312 may be located within a single anti-pad in the anti-pad 314.

[0082] In an embodiment, the pad structure 310 may have a circular pad 312 surrounded by an antipad 314 having a circular or elliptical antipad shape 322. The pad 312 may be centered within or offset from the center of the antipad 314.

[0083] In another embodiment, the pad structure 310 may consist only of anti-pads 314. In this configuration, vias 320 can be formed through the openings in the anti-pads 314 without direct electrical contact with other conductive elements on the layer.

[0084] In another embodiment, the pad structure 310 may include within the anti-pad 314, and wherein the anti-pad shape 322 is configured as two circular pads in a dumbbell-shaped circular pad configuration. The dumbbell shape may be configured as two intersecting and directly connected circular shapes. In other configurations, the dumbbell shape may be configured as two circular shapes offset from each other by an extension member connecting the two circular shapes.

[0085] Figure 4A and Figure 4BAn example of a via pad stack 402 in an embodiment of electronic system 100 is illustrated. Vias 420 can provide electrical connections between different layers of mounting substrate 404.

[0086] Figure 4A An example embodiment of a via pad stack 402 is illustrated. The via pad stack 402 is a set of elements forming a vertical interconnect of vias 420. The via pad stack 402 may include vertical conductive structures that can be coupled to pad structures 310 at different layers of the mounting substrate 404. Pads may be coupled to traces to conduct signals to different layers of the mounting substrate 404.

[0087] The via pad stack 402 may include functional pads 452 and non-functional pads 454. Functional pads 452 may be coupled to some traces at different layers of the mounting substrate 404. Non-functional pads 454 are coupled to one of the vias 420 but not to any trace.

[0088] Figure 4B An example embodiment of a via pad stack 402 with non-functional pads 454 is illustrated. The implementation of adding non-functional pads 454 varies depending on several factors, including PCB material, structure, uniform material stack, mixed material stack, or other similar factors. These factors play an important role in determining the specific method used to incorporate the non-functional pads 454.

[0089] In some embodiments, via 420 can be configured as through via 456. Through via 456 can extend from the top layer to the bottom layer.

[0090] The via 456 can have various configurations. For example, the via 456 can include at least one of the non-functional pads 454. The non-functional pad 454 can be configured to be offset by 470 mils from the top signal pad 462, such as a first pad offset; and another non-functional pad 454 can be configured to be offset by 470 mils from the bottom signal pad 464, such as a second pad offset. If the interval between these two non-functional pads exceeds 20 mils, a third non-functional pad can be added in between.

[0091] In another embodiment, the via can be configured as a back-drilled via 466. The back-drilled via 466 may include one non-functional pad 454 separated by 20 mils from the top signal pad 462 and another non-functional pad 454 separated by 30 mils from the bottom signal pad 464. If the spacing between these two non-functional pads 454 exceeds 20 mils, a third non-functional pad 468 may be added between the other two non-functional pads 454.

[0092] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E An example of a via 520 in an embodiment of electronic system 100 is illustrated. The via 520 can provide electrical connections between different layers of mounting substrate 502.

[0093] Figure 5A An example embodiment of a via 520 with a rectangular antipad 524 and a circular via pad 522 is illustrated. Pad structure 502 may include via 520, which may be coupled to the circular via pad 522.

[0094] Anti-pad 524 is an opening in which conductive material has been removed. Anti-pad 524 can be a rectangular anti-pad. Rectangular anti-pad 524 can have anti-pad size 532. Anti-pad size 532 can be a complex value based on anti-pad shape 544. Anti-pad size 532 can include, for example, length and width, radius, diameter, major axis, minor axis, or other shape-based dimensions that can be used to determine anti-pad area 534. Anti-pad 524 can have anti-pad opening 540.

[0095] Circular via pad 522 is a conductive pad with a circular shape. Circular via pad 522 can be electrically coupled to via 520. Circular via pad 522 can have a via pad size 530 and a via pad area 534. The via pad size 530 can be a complex value based on the via pad shape 542. The via pad size 530 can include, for example, length and width, radius, diameter, major axis, minor axis, or other shape-based dimensions that can be used to determine the via pad area 534.

[0096] The circular via pad 522 can have various parameters. The circular via pad 522 can include, for example, a via pad size 520 such as a diameter. The circular via pad 522 can have a pad gap area 540. The pad gap area 540 is the difference between the anti-pad area 536 and the via pad area 534. The distance between the side of the anti-pad 524 and the via pad 522 can be a pad gap size 538. The relative sizes of the via pad size 530 and the anti-pad size 532 can be configured to achieve desired impedance performance.

[0097] In some embodiments, the via pad area 534 may be approximately the same size as the pad gap area 540. In other embodiments, the via pad area 534 may be smaller than the pad gap area 540. The relative sizes of the via pad area 534 and the pad gap area 540 can be configured based on the desired impedance along the via 520. For example, the impedance along the via 520 can be manipulated by using two identically configured pad structures 502 on adjacent layers, two identically configured pad structures 502 spaced between two or more layers, two differently configured pad structures 502 on adjacent layers, two differently configured pad structures 502 spaced between two or more layers, or combinations thereof. In other examples, the via 520 may be coupled to a different number of pad structures 502 along the via 520. The pad structures 502 may have similar or different configurations regarding shape, size, and area.

[0098] In some embodiments, via 520 may be coupled to two adjacent pad structures 502 having similar or different configurations. Similar configurations may differ from each other in one or more parameters, including size, shape, area, or combinations thereof. In other embodiments, via 520 may be coupled to two or more pad structures 502 with different numbers of layer spacing.

[0099] In yet another embodiment, two vias in a via 520 within a antipad 524 may be spaced apart by a via spacing distance 546 representing the horizontal distance between vias 520. Pad structure 502 may include one or more vias passing through the vias 520 of a antipad 524.

[0100] Figure 5B The illustration shows an example embodiment of a via 520 with an elliptical anti-pad 524 and a circular via pad 522. The via 520 can be coupled to the circular via pad 522.

[0101] Anti-pad 524 may have an elliptical anti-pad shape 544. Anti-pad 524 may have an anti-pad size 532. Anti-pad size 532 may be a complex value based on anti-pad shape 544. Anti-pad size 532 may include, for example, length and width, radius, diameter, major axis, minor axis, or other shape-based dimensions that may be used to determine anti-pad area 534.

[0102] The circular via pad 522 may have a via pad size 530 and a via pad area 534. The via pad size 530 may be a complex value based on the via pad shape 542.

[0103] The circular via pad 522 can have various parameters. The circular via pad 522 can include a via pad size 520 (e.g., diameter). The circular via pad 522 can have a pad gap area 540. The pad gap area 540 can be the difference between the anti-pad area 536 and the via pad area 534.

[0104] An antipad 524 with an elliptical antipad shape 544 can be configured closer to the circular via pad 522. This can result in a smaller pad gap area 540. This may affect the impedance of this configuration.

[0105] Figure 5C The illustration shows an example embodiment of a via 520 with a square antipad 524 and a circular via pad 522. The via 520 may be coupled to the circular via pad 522. In some embodiments, two vias in the via 520 may each have a square antipad 524 and be positioned adjacent to each other.

[0106] The antipad 524 may have a square antipad shape 544. The antipad 524 may have an antipad size 532. The antipad size 532 may be a complex value based on the antipad shape 544. The antipad size 532 may include values ​​that can be used to determine the length and width of the antipad area 534.

[0107] The circular via pad 522 may have a via pad size 530 and a via pad area 534. The via pad size 530 may be a complex value based on the via pad shape 542.

[0108] The circular via pad 522 can have various parameters. The circular via pad 522 can include a via pad size 520 (e.g., diameter). The circular via pad 522 can have a pad gap area 540. The pad gap area 540 can be the difference between the anti-pad area 536 and the via pad area 534.

[0109] An antipad 524 with a square antipad shape 544 can be configured closer to a circular via pad 522. This can result in a smaller pad gap area 540. This may affect the impedance of this configuration.

[0110] Figure 5D The illustration shows an example embodiment of a via 520 with a dumbbell-shaped antipad 524 and a circular via pad 522. The via 520 may be coupled to the circular via pad 522. In some embodiments, two vias in the via 520 may both be within the dumbbell-shaped antipad 524 and positioned adjacent to each other.

[0111] Anti-pad 524 can be a square anti-pad with a dumbbell-shaped anti-pad shape 544. The dumbbell shape can be formed by coupling two circular openings with a rectangular opening. The dumbbell-shaped anti-pad 524 can have an anti-pad size 532. The anti-pad size 532 can be a complex value based on the anti-pad shape 544. The anti-pad size 532 can include values ​​that can be used to determine the length and width of the anti-pad area 534.

[0112] The circular via pad 522 may have a via pad size 530 and a via pad area 534. The via pad size 530 may be a complex value based on the via pad shape 542.

[0113] The circular via pad 522 can have various parameters. The circular via pad 522 can include a via pad size 520 (e.g., diameter). The circular via pad 522 can have a pad gap area 540. The pad gap area 540 can be the difference between the anti-pad area 536 and the via pad area 534.

[0114] An antipad 524 with a square antipad shape 544 can be configured closer to a circular via pad 522. This can result in a smaller pad gap area 540. This may affect the impedance of this configuration.

[0115] Figure 5E The illustration shows an example embodiment of a via 520 with a circular antipad 524 and a circular via pad 522. The via 520 may be coupled to the circular via pad 522. In some embodiments, two vias in the via 520 may each have a circular antipad 524 and be positioned adjacent to each other.

[0116] The antipad 524 may have a circular antipad shape 544. The antipad 524 may have an antipad size 532. The antipad size 532 may be a complex value based on the antipad shape 544. The antipad size 532 may include a value that can be used to determine the diameter of the antipad area 534.

[0117] The circular via pad 522 may have a via pad size 530 and a via pad area 534. The via pad size 530 may be a complex value based on the via pad shape 542.

[0118] The circular via pad 522 can have various parameters. The circular via pad 522 can include a via pad size 520 (e.g., diameter). The circular via pad 522 can have a pad gap area 540. The pad gap area 540 can be the difference between the anti-pad area 536 and the via pad area 534.

[0119] An antipad 524 with a square antipad shape 544 can be configured closer to a circular via pad 522. This can result in a smaller pad gap area 540. This may affect the impedance of this configuration.

[0120] In some embodiments, the configuration of a pad structure positioned along one of the vias can be configured to improve the impedance distribution along the via 520. For example, the via 520 can be configured to have two pad structures 502 spaced apart on adjacent layers, spaced apart by multiple layers, or a combination thereof.

[0121] Figure 6A and Figure 6B An example of a formed anti-pad 620 in an embodiment of electronic system 100 is illustrated. Vias 620 provide electrical connections between different layers of mounting substrate 602. Some of these layers may include different embodiments of the formed anti-pad 620.

[0122] Figure 6A An example of a mounting substrate 602 formed of a uniform material is illustrated. Vias 620 can transmit signals between top signal pads 626 and bottom signal pads 628, and between other intermediate layers. Top signal pads 626 can be coupled to solder balls 612. Vias 620 can function as transmission lines. At each layer, vias 620 can be configured with pad structures 606 to vary the impedance of the vias 620. Vias 620 can be configured such that pad structure 606 is a functional pad 648, a non-functional pad 650, or no pad 652. Pad structure 606 can have via pads 622 combined with anti-pads 624.

[0123] In an illustrative embodiment, the mounting substrate 602 may include multiple layers, each layer having a pad structure 606 to configure the impedance of the via 620. The via 620 may be configured to have two rectangular anti-pads 640, an elliptical anti-pad 642, a dumbbell-shaped anti-pad 644, two circular anti-pads 646, another dumbbell-shaped anti-pad 644, another elliptical anti-pad 642, and two rectangular anti-pads 640. The via 620 can be configured using the pad structure 606 to vary its impedance. The mounting substrate 602 may be implemented using a uniform material for a printed circuit board stack.

[0124] Figure 6B An example of a mounting substrate 602 formed of a composite material is illustrated. The composite material may include a prepreg, a core, or other similar materials used for different layers.

[0125] Mounting substrate 602 may include vias 620 configured to have two rectangular antipads 640, an elliptical antipad 642, four rectangular antipads among the rectangular antipads 640, another elliptical antipad 642, and two rectangular antipads 640. In some embodiments, the layer between the two elliptical antipads 642 may be formed of a low-speed material layer 654, which is different from the high-speed dielectric material layers 652 on the upper and lower layers.

[0126] 3.0. Performance Analysis

[0127] Figure 7 An example of a terminal time-domain reflectivity (TDR) impedance diagram 702 for an embodiment of electronic system 100 is illustrated. The terminal TDR impedance diagram 702 shows reflections along one of the vias 720.

[0128] In some embodiments, using ultra-low loss PCB dielectric materials such as core and prepreg can achieve the via impedance target 722 by removing all non-functional pads 454, which are typically limited in the BGA area due to physical constraints. Using additional non-functional pads 454 can help reduce the impedance of the via 720 to achieve the target value. The via impedance target 722 is the desired impedance level of the via 420. The via impedance target 722 can be represented by a single average value, a set of impedance values ​​over a period of time, a set of impedance values ​​over a distance from the end of the via, or a combination thereof.

[0129] Terminal TDR impedance diagram 702 shows impedance reflections with and without an additional pad, and with an additional non-functional pad 454. The addition of the additional pad reduces the impedance by approximately 5%, as shown at the 25 picosecond (ps) mark. In some embodiments, via impedance can be reduced by adding a pad at a location corresponding to a portion of the reflection time (e.g., the peak of the impedance) in the TDR impedance diagram. In some embodiments, the location of the peak or other point in the TDR impedance diagram may be an approximation of an offset distance.

[0130] Figure 8 An example of a terminal time-domain reflectivity impedance diagram 802 for another embodiment of electronic system 100 is illustrated. The terminal TDR impedance diagram 802 shows reflections along via 820.

[0131] In some embodiments, using ultra-low loss PCB dielectric materials such as core and prepreg can achieve the via impedance target 822 by removing all non-functional pads 454, which are typically limited in the BGA area due to physical constraints. Using additional non-functional pads 454 can help reduce the impedance of the via 820 to achieve the target value. The via impedance target 822 is the desired impedance level of the via 820.

[0132] Terminal TDR impedance diagram 802 shows impedance reflections with and without additional pads, and with two additional non-functional pads 454. The addition of the two additional pads reduces the impedance by approximately 10%, as shown at the 25 picosecond (ps) mark. This impedance reduction demonstrates that the addition of non-functional pads 454 can improve system performance. In some embodiments, via impedance can be reduced by adding one of the non-functional pads at a location corresponding to a reflection time (e.g., a peak in the impedance) of a portion of the TDR impedance diagram. In other embodiments, the location of a peak or other point in the TDR impedance diagram may be an approximation of an offset distance.

[0133] Figure 9 An example of a terminal time-domain reflectivity (TDR) impedance diagram 902 for another embodiment of electronic system 100 is illustrated. Terminal TDR impedance diagram 902 shows reflections along one of the vias 920, some of which are non-functional pads 454 with different anti-pad shape characteristics.

[0134] The impedance of via 918 can vary based on its location along the via structure and the shape of both antipad 524 and pad 522. In some embodiments, a uniform shape can be used across all layers, but this approach can result in impedance deviations from the desired target impedance at different locations along via 918. These deviations can manifest as impedance values ​​that are higher or lower than the expected target impedance. Consequently, these deviations can lead to increased return loss and reduced overall system margin in end-to-end high-speed signal transmission. Using an additional non-functional pad 454 can help reduce the impedance of via 918 to achieve the target value. The pad location can be selected based on initial measurements from the TDR impedance diagram 902.

[0135] Terminal TDR impedance diagram 902 shows impedance reflections with and without additional pads, and with two additional non-functional pads 454. The addition of the two additional pads reduces the impedance by approximately 10%, as shown at the 25 picosecond (ps) mark. The impedance reduction demonstrates that the addition of non-functional pads 454 can improve system performance. In some embodiments, via impedance 920 can be reduced by adding one of the pads with specific shape characteristics at a location corresponding to the reflection time of a portion of the TDR impedance diagram (such as a portion representing a peak in the impedance). In some embodiments, the location of a peak or other point in the TDR impedance diagram can be an approximation of an offset distance.

[0136] In other embodiments, the mounting substrate 102 can be formed using hybrid materials for stacked structures. These hybrid materials allow for the use of high-performance and low-performance materials as needed. This allows for fine-tuning of PCB manufacturing in high-speed signal transmission applications exceeding 50Gb / s by matching the properties of the materials to the desired performance characteristics. These stacks employ high-end materials in layers with ultra-high-speed routing, while using low-end materials in other areas, such as between power and GND layers and low-speed signal routing layers.

[0137] In some configurations, significant variations in via impedance 920 may exist due to the different dielectric constants of the high-end and low-end materials. Layer-by-layer pad stacking and anti-pad stacking methods can be configured to alter the via impedance distribution 924 and compensate for differences caused by variations in dielectric materials. The impedance distribution 924 can be the desired impedance measured at each layer within the via hierarchy. The impedance distribution 924 can be configured to reduce the overall via impedance and can be influenced by the trace and component layout of each layer. By configuring the pads 522 and anti-pads 524 of the pad structure 310, it becomes possible to customize the via impedance 920 in different regions with different dielectric constants to achieve the via impedance target 922. The via impedance target 922 can be various target values, such as the average impedance of the via or a specific impedance at a specific location along the via 520. The configuration of the shape and size of the pads 522 within the anti-pad 524 can alter the via impedance 920 along the via 520. The configuration of anti-pad shape and size can also change the via impedance 920 and accommodate multiple dielectric materials in different layers.

[0138] Configuring via pads and antipads, along with impedance control throughout these areas, can make the impedance characteristics on the hybrid stack more consistent and desirable, thereby mitigating signal integrity issues.

[0139] 4.0. Function Overview

[0140] Figure 10 An example of a manufacturing process flow 902 for an electronic system 100 is illustrated in the embodiment. The manufacturing process flow 902 can describe the steps and processes for manufacturing a mounting substrate 102.

[0141] Manufacturing process flow 902 may include various operations. In an illustrative embodiment, manufacturing process flow 902 may include a layer forming step 904, a pad structure forming step 906, a via forming step 908, and an attachment component step 910.

[0142] In layer formation step 904, an initial portion of the mounting substrate can be formed using one of the layers. The layer has at least two parts: a dielectric layer providing mechanical structural stability and a conductive layer in direct contact with the dielectric layer. The conductive layer can be formed of a metal or metal alloy (including copper, silver, gold, or other similar conductive materials). The dielectric layer can be formed of various materials such as glass fiber, resin, or other similar materials. The layers of the mounting substrate provide the basis for forming the functional traces supporting the electronic system 100.

[0143] In step 906 of forming the pad structure layer, the pad structure can be formed on one of the layers. The pad structure is formed from the conductive layer by removing a portion of the conductive layer. The pad structure and other conductive elements on the layer can be formed in a variety of ways, including etching, photolithography, drilling, milling, meshing, or other similar manufacturing techniques. For example, an etching mask can be placed on the conductive layer and photolithography can be performed using ultraviolet light.

[0144] A pad structure comprises pads formed within anti-pad openings. The electrical characteristics of a pad structure are controlled by its physical characteristics, including pad shape, pad size, anti-pad shape, and anti-pad size. The relative sizes of pads and anti-pads can expose varying amounts of dielectric layer. Similarly, combinations of pad and anti-pad shapes can alter the pad structure's ability to modify impedance.

[0145] In some embodiments, pads can be configured as non-functional pads. Non-functional pads can be pads that are not connected to other components on the same layer. Non-functional pads can affect the impedance of vias passing through them.

[0146] In the via formation step 908, vias, including vias connecting pads in a pad structure, can be formed. A via is a conductive element that can connect two or more pads on different layers of a mounting substrate.

[0147] Via formation can encompass a variety of techniques. Via formation can include drilling, laser drilling, etching, or other similar techniques. Vias are created by forming via holes and filling them with a conductive material. The conductive material can form a liner on the walls of the via hole or completely fill the via hole.

[0148] In some embodiments, the pads of the pad structure are formed in an aligned manner to allow interconnection between the pads and vias.

[0149] In other embodiments, a via can be formed between the top and bottom layers to form a through-hole through the board. In yet another embodiment, a via can be formed between two intermediate layers to form a buried via.

[0150] In some embodiments, the top and bottom layers may be etched to include mounting pads or other pads for interfacing with electronic components and systems outside the mounting substrate.

[0151] After a set of pad structures and via formation tasks have been completed, the control flow can return to the layer formation step 904 to add additional layers as needed. If no additional layers are needed, the control flow can proceed to the attachment step 910.

[0152] In the attachment step 910, electronic components 305 can be attached to vias using mounting pads. For example, electronic components such as ball grid array components can be attached to mounting pads on the outer layer. In some embodiments, electronic components can be attached to both the top and bottom layers of the mounting substrate simultaneously.

[0153] Other examples of these and other embodiments can be found throughout this disclosure.

[0154] 5.0. Example Implementation

[0155] Examples of some embodiments are presented in, but not limited to, the following terms and use cases:

[0156] According to an embodiment, a method of manufacturing an electronic system includes: forming a first pad structure on a first substrate layer of a mounting substrate, the first pad structure having a first pad located within a first anti-pad opening of a first conductive portion of the first substrate layer; forming a second pad structure on a second substrate layer of the mounting substrate, the second substrate layer being on the first substrate layer, the second pad structure having a second pad within a second anti-pad opening of a second conductive portion of the second substrate layer, and the second substrate layer being offset from the first substrate layer by a first offset distance; forming a via at least between the first pad and the second pad, the via having a conductive portion for electrically coupling the first pad and the second pad, and the first offset distance being configured to reduce the level of via impedance between the first pad and the second pad; and forming a top pad on a top substrate layer of the second substrate layer, the top pad being electrically coupled to one of the vias.

[0157] In an embodiment, the method includes forming a first pad structure by forming a first pad having a circular pad shape and a first anti-pad opening having a rectangular shape, wherein the first pad and the first anti-pad opening are offset by a pad gap offset distance on the nearest side.

[0158] In an embodiment, the method includes forming a first pad structure, which includes forming a first pad having a circular pad shape and a first anti-pad opening having a circular shape, wherein the first pad and the first anti-pad opening are offset by a pad gap offset distance on the nearest side.

[0159] In an embodiment, forming the first pad structure includes forming a second pad structure having a second antipad shape that is different from the shape of the first antipad.

[0160] In one embodiment, the method further includes forming a second via within the opening of the first antipad.

[0161] According to an embodiment, a method of manufacturing an electronic system includes: forming a first pad structure on a first substrate layer of a mounting substrate, the first pad structure having a first pad located within a first anti-pad opening of a first conductive portion of the first substrate layer; forming an intermediate substrate layer on the first substrate layer of the mounting substrate; forming a second pad structure on a second substrate layer of the mounting substrate, the second substrate layer being on the first substrate layer and the intermediate substrate layer, the second pad structure having a second pad within a second anti-pad opening of a second conductive portion of the second substrate layer, and the second substrate layer being offset from the first substrate layer by a first offset distance; forming a via at least between the first pad and the second pad, the via having a conductive portion for electrically coupling the first pad and the second pad, and the first offset distance being configured to reduce the via impedance level between the first pad and the second pad; forming a top pad on a top substrate layer on the second substrate layer, the top pad being electrically coupled to the via; and attaching an electronic component to the top pad.

[0162] In an embodiment, forming an intermediate substrate layer includes forming an intermediate substrate layer with non-functional pads directly between a first pad and a second pad.

[0163] In an embodiment, forming an intermediate substrate layer includes forming an intermediate substrate layer having a third pad structure having a third pad and a third anti-pad opening.

[0164] In an embodiment, the method includes forming an intermediate substrate layer, which includes forming an intermediate substrate layer having a third pad structure having a third pad and a third anti-pad opening, and the third anti-pad opening having a third anti-pad shape different from the first anti-pad opening.

[0165] In an embodiment, the method includes forming an intermediate substrate layer, which includes forming an intermediate substrate layer having a third pad structure with a third pad and a third anti-pad opening, and vias electrically coupled to the third pad.

[0166] According to an embodiment, an electronic system includes: a mounting substrate having at least a first layer and a second layer; a first pad structure having a first pad within a first anti-pad opening, the first pad structure being on the first layer; a second pad structure having a second pad within a second anti-pad opening, the second pad structure being on the second layer, and the second layer being on the first layer; and a via electrically coupled to the first pad and the second pad.

[0167] In an embodiment, the system includes a first pad structure having a circular pad shape and a first anti-pad opening having a rectangular shape, wherein the first pad and the first anti-pad opening are offset by a pad gap offset distance on the nearest side.

[0168] In an embodiment, the system includes a first pad structure having a circular pad shape and a first anti-pad opening having a circular shape, wherein the first pad and the first anti-pad opening are offset by a pad gap offset distance on the nearest side.

[0169] In an embodiment, the second pad structure in the system includes a second antipad shape that is different from the shape of the first antipad.

[0170] In one embodiment, the system further includes a second via within the opening of the first antipad.

[0171] In one embodiment, the system further includes an intermediate substrate layer between the first layer and the second layer.

[0172] In one embodiment, the intermediate substrate layer in the system includes non-functional pads directly between the first pad and the second pad.

[0173] In an embodiment, the intermediate substrate layer of the system is a third pad structure having a third pad and a third anti-pad opening.

[0174] In an embodiment, the intermediate substrate layer includes a third pad structure having a third pad and a third anti-pad opening, and the third anti-pad opening has a third anti-pad shape that is different from the shape of the first anti-pad.

[0175] In an embodiment, the intermediate substrate layer includes a third pad structure having a third pad and a third anti-pad opening, and vias are electrically coupled to the third pad and the first pad.

[0176] 6.0. Extensions and Alternatives

[0177] As used herein, the terms “first,” “second,” “certain,” and “specific” are used as a naming convention to distinguish queries, plans, representations, steps, objects, devices, or other items from one another so that these items can be referenced after they have been introduced. Unless otherwise stated herein, the use of these terms does not imply any order, timing, or other characteristics of the referenced items.

[0178] In the accompanying drawings, different components are depicted as coupled to different other components by arrows. These arrows only illustrate certain examples of current flow between or through these components. The direction of the arrows and the absence of arrow lines between some components should not be interpreted as indicating the presence or absence of flow within some components themselves.

[0179] Embodiments of the invention have been described in the specification with reference to numerous specific details, which may vary between implementations. Therefore, the sole and exclusive indication of the invention and the applicant's inventive intent is the set of claims published in specific form according to this application, wherein such claim publication includes any subsequent amendments. In this regard, although specific dependent attributes are set forth in the claims of this application, it should be noted that the features of the dependent claims of this application may be suitably combined with features of other dependent claims and features of the independent claims of this system, and not only with the specific dependent attributes set forth in the claim set forth. Moreover, although individual embodiments are discussed herein, any combination of the embodiments and / or portions of the embodiments discussed herein can be combined to form other embodiments.

[0180] Any definitions expressly set forth herein with respect to terms contained in such claims shall govern the meaning of such terms as used in the claims. Therefore, any limitations, elements, properties, characteristics, advantages, or attributes not expressly referenced in the claims shall not in any way limit the scope of such claims. Therefore, this specification and drawings should be viewed in an illustrative rather than restrictive sense.

[0181] It should be understood that system functionality can be described using terms such as modules, units, systems, subsystems, pads, and components that refer to devices that can be implemented using different combinations of mechanical and electronic components. Systems and devices may include electrical subsystems, mechanical subsystems, and other physical elements for operating and controlling the system. These elements may include computational elements that can execute the system's firmware and software to control the mechanical characteristics of the system. Furthermore, the mechanical elements of the system can operate in normal operation with or without control mechanisms.

Claims

1. An electronic system, characterized by The electronic system comprises: a mounting substrate having at least a first layer and a second layer; a first pad structure having a first pad within a first anti-pad opening, the first pad structure on the first layer; a second pad structure having a second pad within a second anti-pad opening, the second pad structure on the second layer, and the second layer on the first layer; a via electrically coupled to the first pad and the second pad.

2. The electronic system of claim 1, wherein, The first pad structure includes the first pad having a circular pad shape and the first anti-pad opening having a rectangular shape, wherein the first pad is offset from a nearest side of the first anti-pad opening by a pad gap offset distance.

3. The electronic system of claim 1, wherein, The first pad structure includes the first pad having a circular pad shape and the first anti-pad opening having a circular shape, wherein the first pad is offset from a nearest side of the first anti-pad opening by a pad gap offset distance.

4. The electronic system of claim 1, wherein, The second pad structure includes a second anti-pad shape different from a first anti-pad shape.

5. The electronic system of claim 1, wherein, Further comprising: a second via within the first anti-pad opening.

6. The electronic system of claim 1, wherein, Further comprising: an intermediate substrate layer between the first layer and the second layer.

7. The electronic system of claim 6, wherein, The intermediate substrate layer includes a non-functional pad directly between the first pad and the second pad.

8. The electronic system of claim 6, wherein, The intermediate substrate layer is a third pad structure having a third pad and a third anti-pad opening.

9. The electronic system of claim 6, wherein, The intermediate substrate layer includes a third pad structure having a third pad and a third anti-pad opening, and the third anti-pad opening has a third anti-pad shape different from the first anti-pad opening.

10. The electronic system of claim 6, wherein, The intermediate substrate layer includes a third pad structure having a third pad and a third anti-pad opening, and the via is electrically coupled to the third pad and the first pad.

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