Control circuit for suppressing overcurrent, switching power supply and power supply equipment
By setting up switching transistors, resistors, and capacitors in flyback or forward circuits, the duty cycle and frequency of the PWM signal can be precisely controlled, solving the problem of reduced current control accuracy caused by control signal delay errors, achieving precise overcurrent protection, and improving the safety and reliability of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2026-03-27
AI Technical Summary
In flyback or forward converters with peak current control, the current control accuracy decreases due to the delay error of the control signal. This is especially true when there is high input voltage, large capacitive load, or a small number of turns, which may lead to transformer saturation, circuit abnormalities, or even damage.
By setting the first switching transistor, the second switching transistor, resistors, and capacitors, the duty cycle and frequency of the PWM signal are precisely controlled. The overcurrent response module and adjustment module are used to achieve precise overcurrent protection and reduce the control of the start-up current.
It improves the safety and reliability of the circuit, prevents current runaway, protects the circuit from damage, and enhances the stability and reliability of the system.
Smart Images
Figure CN224054114U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of electronic circuit, and relates to but is not limited to a control circuit for inhibiting overcurrent, a switching power supply and a power supply device. BACKGROUND
[0002] In a flyback circuit or a forward circuit in a peak current control mode, due to the delay error of a control signal, when the switching frequency is high and the duty cycle of a pulse-width modulation (PWM) signal is low, the proportion of the delay error in the PWM signal will significantly increase, resulting in a decrease in current control accuracy. Especially when the input voltage is high and the output load is a large capacitive load or the primary-secondary winding ratio is low, the delay error can cause the start-up current to be out of control, and thus the transformer to be saturated, the circuit to work abnormally or even be damaged. SUMMARY
[0003] In view of this, the present disclosure provides a control circuit for inhibiting overcurrent, a switching power supply and a power supply device.
[0004] In a first aspect, the present disclosure provides a control circuit for inhibiting overcurrent, comprising a control chip, a first switch tube, a first capacitor, a first resistor, an overcurrent response module and an adjustment module, the adjustment module comprising a second switch tube, the second switch tube inputting an overcurrent protection signal to the control chip when in a first state, the second switch tube inputting an overcurrent exit signal to the control chip when in a second state, the first state being an on state or an off state; the overcurrent response module being configured to acquire an overcurrent signal; the first capacitor being connected between a first pole of the first switch tube and a third pole of the first switch tube, the second pole of the first switch tube being connected to the overcurrent response module, the first pole of the first switch tube further being connected to a reference voltage terminal pin of the control chip through the first resistor, the second switch tube being in the first state when the first switch tube receives the overcurrent signal, and the second switch tube being in the second state when the first switch tube does not receive the overcurrent signal and the voltage of the first capacitor reaches a preset voltage value.
[0005] In some embodiments, the overcurrent response module further comprises a third resistor, a fifth resistor and a first diode; the first switch tube is an N-type transistor; the second pole of the first switch tube is connected to a first end of the third resistor and then connected to a current sampling end through the first diode; the third pole of the first switch tube is connected to a second end of the third resistor, and the third pole of the first switch tube is connected to ground through the fifth resistor.
[0006] In some embodiments, the adjusting module further comprises a second resistor, a fourth resistor, a seventh resistor and a second capacitor, wherein the second switch tube is a P-type transistor; the first pole of the first switch tube is connected with the second pole of the second switch tube through the second resistor, the first end of the fourth resistor is connected with the second end of the third resistor, and the second end of the fourth resistor is connected with the current detection input pin of the control chip; the first end of the seventh resistor is connected with the first pole of the second switch tube, and the second end of the seventh resistor is connected with the second end of the fourth resistor and then grounded through the second capacitor.
[0007] In some embodiments, the cathode of the first diode is connected with the third pole of the first switch tube and the first end of the third resistor, and the anode of the first diode is connected with the current sampling end.
[0008] In some embodiments, the control circuit for inhibiting overcurrent further comprises a second diode and a sixth resistor, the cathode of the second diode is connected with the second pole of the first switch tube through the sixth resistor, and the anode of the second diode is connected with the cathode of the first diode.
[0009] In some embodiments, the first switch tube is an NPN-type triode, and the second switch tube is a PNP-type triode; wherein the first pole is a collector, the second pole is a base, and the third pole is an emitter; or, the first switch tube is an NMOS transistor, and the second switch tube is a PMOS transistor; wherein the first pole is a drain, the second pole is a gate, and the third pole is a source.
[0010] In some embodiments, the capacitance value of the first capacitor ranges from 10nF to 30nF; the resistance value of the first resistor ranges from 10kΩ to 20kΩ; and the resistance value of the second resistor ranges from 3kΩ to 5kΩ.
[0011] In other embodiments, the adjusting module further comprises an eighth resistor, a ninth resistor and a third capacitor; wherein the second switch tube and the first switch tube are both N-type transistors; the first end of the eighth resistor and the first end of the ninth resistor are connected and then connected with the reference voltage pin of the control chip; the second end of the eighth resistor, the first end of the third capacitor and the third pole of the second switch tube are connected and then connected with the oscillation timing pin of the control chip, and the second end of the third capacitor is grounded; the first pole of the second switch tube is connected with the second end of the ninth resistor, and the second pole of the second switch tube is connected with the first pole of the first switch tube.
[0012] In some embodiments, the overcurrent response module further comprises an eleventh resistor and a twelfth resistor; the first end and the second end of the eleventh resistor are respectively connected with the internal error amplifier output pin of the control chip and the second pole of the first switch tube; and the first end and the second end of the twelfth resistor are respectively connected with the second pole of the first switch tube and the third pole of the first switch tube.
[0013] In some embodiments, the second switch tube is an NMOS transistor, and the first switch tube is an NPN type triode; wherein the first pole of the second switch tube is a drain, the second pole of the second switch tube is a gate, and the third pole of the second switch tube is a source; the first pole of the first switch tube is a collector, the second pole of the first switch tube is a base, and the third pole of the first switch tube is an emitter.
[0014] In some embodiments, the capacitance value of the first capacitor ranges from 100 nF to 150 nF, and the resistance value of the first resistor ranges from 10 kΩ to 20 kΩ.
[0015] In the second aspect, the embodiments of the present disclosure provide a switching power supply, comprising a forward circuit or a flyback circuit and the control circuit for inhibiting overcurrent in any one of the first aspect.
[0016] In the third aspect, the embodiments of the present disclosure provide a power supply device, comprising the switching power supply in the second aspect.
[0017] The embodiments of the present disclosure realize accurate control of the turn-on and turn-off timing of the first switch tube and the second switch tube by setting the first switch tube, the second switch tube, the first resistor and the first capacitor, and further setting the parameters of the first resistor and the first capacitor, can adjust the duty ratio or frequency of the PWM signal, control the size of the starting current by effectively reducing the duty ratio or frequency of the PWM signal, realize accurate overcurrent protection, and significantly improve the safety of the circuit. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.
[0019] Figure 1 Fig. (a) in the above is a schematic diagram of the change of the sampling current with time, Figure 1 Fig. (b) in the above is a schematic diagram of the change of the voltage of the PWM signal with time;
[0020] Figure 2 Fig. (a) in the above is a schematic diagram of the change of the sampling current with time,
[0021] Figure 3 Fig. (a) in the above is a schematic diagram of the change of the sampling current with time, Figure 3 Fig. (b) in the above is a schematic diagram of the change of the voltage of the sampling current with time, Figure 3 Fig. (c) in the above is a schematic diagram of the change of the voltage of the PWM signal with time;
[0022] Figure 4 A specific configuration diagram of the isolation driving circuit provided for another embodiment of the present disclosure is shown in FIG. 6.
[0023] Figure 5 A specific configuration diagram of the isolation driving circuit provided for another embodiment of the present disclosure is shown in FIG. 6.
[0024] Figure 6 A specific configuration diagram of the isolation driving circuit provided for another embodiment of the present disclosure is shown in FIG. 6.
[0025] Figure 7 A specific configuration diagram of the isolation driving circuit provided for another embodiment of the present disclosure is shown in FIG. 6.
[0026] Figure 8 A specific configuration diagram of the isolation driving circuit provided for another embodiment of the present disclosure is shown in FIG. 6.
[0027] Figure 9 An optional structural schematic diagram of the switching power supply provided for an embodiment of the present disclosure is shown in FIG. 7. DETAILED DESCRIPTION
[0028] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will further describe the specific technical solutions of the application with reference to the drawings in the embodiments of the present disclosure. The following embodiments are used to illustrate the present disclosure, but not to limit the scope of the present disclosure.
[0029] In the following description, the term "some embodiments" describes a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.
[0030] In the following description, the term "first\second\third" is only used to distinguish different objects, and does not represent a specific order of the objects, and does not have a limitation of the order. It can be understood that "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.
[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure.
[0032] It should be noted that the technical solutions disclosed in the embodiments of the present disclosure can be combined arbitrarily without conflict.
[0033] In the related art, Figure 1 The delay problem that may occur in the current control process in a PWM (pulse width modulation) controlled switching power supply is shown. Figure 1 Figure (a) in the figure shows the relationship between the current and time, where Icontrol is the set current limit value. Figure 1 Figure (b) in the figure shows the corresponding PWM signal voltage change over time.
[0034] When the on time of the PWM signal is very short, as shown in Figure 1 Figure (a) in the figure, when the current sampling signal reaches the current limit value Icontrol at time t1, the PWM signal should be turned off at time t1 in the ideal case, and the actual PWM signal on time should be Δt1, that is, the time interval between time t1 and time t0. However, due to the delay in turning off the PWM signal, the actual PWM signal is turned off at time t2, so the actual PWM signal on time becomes Δt2, that is, the time interval between time t2 and time t0. After a time interval T1, the circuit continues to generate a wave at time t3, which causes the actual PWM signal duty cycle to be higher than the theoretical value. This delay effect can cause the current to continue to rise, which may exceed the set limit current value, causing abnormal current control, or even loss of control. Especially when the input voltage is high, the output load is a large capacitive load, or the turns ratio of the transformer primary and secondary is small, the effect of this delay error is more significant, which may cause the transformer to saturate, the circuit to work abnormally or be damaged.
[0035] Therefore, the present disclosure proposes the following embodiments.
[0036] In a first aspect, the present disclosure provides a control circuit for suppressing overcurrent, as shown in Figure 2 The control circuit for suppressing overcurrent includes a control chip IC1, a first switch tube Q1, a second switch tube Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, and a first diode D1. The first switch tube Q1 is an N-type transistor, and the second switch tube Q2 is a P-type transistor.
[0037] Referring to Figure 2 The first pole of the first switch tube Q1 is connected to the third pole of the second switch tube Q2 through the first resistor R1, and then connected to the reference voltage terminal pin (Vref) of the control chip IC1. Figure 2The eighth pin VREF shown in the figure is connected to the third pin FB of the control chip IC1, and the first pole of the first switch tube Q1 is connected to the second pole of the second switch tube Q2 through the second resistor R2; the second pole of the first switch tube Q1 is connected to the first end of the third resistor R3, and then connected to the current sampling end through the first diode D1; the third pole of the first switch tube Q1 is connected to the second end of the third resistor R3, and the third pole of the first switch tube Q1 is grounded through the fifth resistor R5; the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the current detection input end pin (CS) of the control chip IC1; the first end of the first capacitor C1 is connected to the first pole of the first switch tube Q1; the second end of the first capacitor C1 is connected to the first end of the fourth resistor R4; the first pole of the second switch tube Q2 is connected to the second end of the fourth resistor R4, and then grounded through the second capacitor C2. Figure 2
[0038] In some embodiments, the model of the control chip IC1 is UCC28C44. Illustratively, the control chip has 8 pins, which are the internal error amplifier output end pin (COMP pin), feedback pin (FB pin), current detection input end pin (CS pin), oscillation timing pin (RT / CT pin 4), ground pin (GND pin), output pin (OUT pin), power supply pin (VDD pin), and reference voltage end pin (VREF pin).
[0039] In some embodiments, the current transformer CT1 can be used for current sampling. Illustratively, as shown in Figure 2 , the current transformer CT1 is a transformer, the primary winding of the current transformer CT1 is connected to the circuit to be sampled, for sensing the current flowing through the circuit to be sampled, and the secondary winding of the current transformer CT1 outputs a current proportional to the primary current, which can be detected and processed by other parts (such as the control chip) in the circuit. Specifically, the same name end a of the secondary winding of the current transformer CT1 can be understood as the current sampling end, and the different name end b of the secondary winding of the current transformer CT1 is grounded, which helps to provide a stable reference point, reduce noise interference, and ensure the safe operation of the circuit.
[0040] In some embodiments, as shown in Figure 2 , the first end of the fifth resistor R5 is connected to the third pole of the first switch tube Q1, and the second end of the fifth resistor R5 is grounded.
[0041] In some embodiments, the second diode D2 is used to reduce the error of controlling the conduction timing of the first switch tube Q1.
[0042] In some embodiments, as shown in Figure 2 As shown, the overcurrent inhibiting control circuit further comprises a sixth resistor R6 and a seventh resistor R7; a first end of the sixth resistor R6 is connected to the second electrode of the first switch tube Q1, and a second end of the sixth resistor R6 is connected to the cathode of the second diode D2; a first end of the seventh resistor R7 is connected to the first electrode of the second switch tube Q2, and a second end of the seventh resistor R7 is connected to the second end of the fourth resistor R4.
[0043] In some embodiments, the sixth resistor R6 is used to limit the current value flowing through the second electrode of the first switch tube Q1. For example, when the first switch tube Q1 is an NPN type triode and the second switch tube Q2 is a PNP type triode, the sixth resistor R6 is used to limit the current flowing through the base of the first switch tube Q1.
[0044] In some embodiments, the sixth resistor R6 is also used to limit the current flowing through the first diode D1, thereby protecting the first diode D1 from excessive current.
[0045] In some embodiments, as shown, Figure 2 The overcurrent inhibiting control circuit further comprises a second diode D2, the cathode of the first diode D1 and the anode of the second diode D2 are connected to the first end of the third resistor R3, and the anode of the first diode D1 is connected to the current sampling end.
[0046] In some embodiments, the seventh resistor R7 acts as a voltage dividing resistor, which works with the fourth resistor R4 and the fifth resistor R5 to precisely control the voltage on the second capacitor C2, thereby ensuring that the current detection input end pin (CS pin) of the control chip IC1 will not be damaged by excessive voltage. This voltage dividing strategy can protect the circuit components from voltage surges, enhancing the stability and reliability of the entire system, not only improving the safety of the circuit, but also helping to prolong the service life of the control chip. In some embodiments, the first switch tube Q1 is an NPN type triode, and the second switch tube Q2 is a PNP type triode; wherein the first electrode is the collector, the second electrode is the base, and the third electrode is the emitter; or, the first switch tube is an NMOS transistor, and the second switch tube is a PMOS transistor; wherein the first electrode is the drain, the second electrode is the gate, and the third electrode is the source.
[0047] In the above embodiments, the third resistor R3, the fifth resistor R5, the sixth resistor R6, the first diode D1, and the second diode D2 belong to the overcurrent response module 1, which is used to obtain the overcurrent signal of the measured circuit. The second switch tube Q2, the second resistor R2, the fourth resistor R4, the seventh resistor R7, and the second capacitor C2 belong to the adjustment module 2; when the second switch tube Q2 is in the on state, the overcurrent protection signal is input to the control chip; when the second switch tube Q2 is in the off state, the control chip exits the overcurrent protection.
[0048] Next, reference will be made toFigure 2 and Figure 3 The working principle of the overcurrent suppression control circuit is described in detail.
[0049] Figure 3 Figure (a) in the above shows the relationship between the sampling current and time. Figure 3 Figure (b) in the above shows the relationship between the voltage converted from the sampling current and time, Figure 3 Figure (c) in the above shows the corresponding PWM signal voltage and time.
[0050] As shown in Figure 2 and Figure 3 In the overcurrent suppression control circuit, the current transformer CT1 detects the current signal ics of the circuit to be sampled, the current signal ics flows through the third resistor R3 and the fifth resistor R5 to generate a voltage signal Vcs, and the voltage signal Vcs is transmitted to the CS pin of the control chip IC1 through the fourth resistor R4 and the second capacitor C2. The third resistor R3 and the fifth resistor R5 are used for current detection, which converts the current signal into a voltage signal, and the low-pass filter constructed by the fourth resistor R4 and the second capacitor C2 can effectively filter out high-frequency interference signals to ensure the stability of the voltage signal. Through the filtering process of the fourth resistor R4 and the second capacitor C2, the signal received by the CS pin of the control chip IC1 is kept stable, thereby avoiding false operation caused by current fluctuation.
[0051] At time t1, the current signal ics reaches the current limit value Icontrol, and at time t4, the current signal ics reaches the set protection threshold (for example, Iset). The voltage Vset on the third resistor R3 will cause the first switch tube Q1 to turn on, at which time the first capacitor C1 is clamped to 0V, and the second switch tube Q2 is turned on, thereby pulling up the Vcs voltage and triggering the current limiting protection mechanism. This causes the PWM signal to be closed, and the starting current begins to decrease. At time t2, the first switch tube Q1 returns to the off state, but since the first capacitor C1 needs to be recharged through the first resistor R1 and the second resistor R2, the second switch tube Q2 continues to maintain the on state, the voltage signal Vcs is maintained in the high voltage state, and the circuit is still in the current limiting protection state. During this period, the PWM signal cannot be sent, and the circuit skips the current period. Only when the first capacitor C1 is fully charged, the second switch tube Q2 will be turned off at time t5, so that the circuit restores the normal PWM signal output at time t6.
[0052] In some embodiments, the set protection threshold (for example, Iset) is greater than the current limit value Icontrol.
[0053] As shown in Figure 3As shown, the time interval between two adjacent PWM signal pulses can be increased from T1 to T2 to reduce the duty cycle of the PWM signal.
[0054] In some embodiments, the capacitance value of the first capacitor ranges from 10nF to 30nF. More specifically, the capacitance value of the first capacitor can be 10nF, 15nF, 20nF, 25nF or 30nF.
[0055] In some embodiments, the resistance value of the first resistor ranges from 10kΩ to 20kΩ. More specifically, the resistance value of the first resistor can be 10kΩ, 15kΩ or 20kΩ.
[0056] In some embodiments, the resistance value of the second resistor ranges from 3kΩ to 5kΩ. More specifically, the resistance value of the second resistor can be 3kΩ, 4kΩ or 5kΩ. It should be noted that the above-mentioned capacitance value of the first capacitor, resistance value of the first resistor and resistance value of the second resistor are only an example, and in actual application, the capacitance value of the first capacitor, resistance value of the first resistor and resistance value of the second resistor can be reasonably selected in combination with specific circuits and application scenarios, as long as the charging and discharging time requirement of the first capacitor C1 is met.
[0057] The embodiments of the present disclosure achieve accurate control of the on and off timing of the first switch tube Q1 and the second switch tube Q2 by setting the first resistor R1, the second resistor R2 and the first capacitor C1 and further setting the parameters of the first resistor R1, the second resistor R2 and the first capacitor C1. On the one hand, the number of periods of the PWM signal can be controlled to adjust the duty cycle of the PWM signal, and the size of the starting current is controlled by effectively reducing the duty cycle of the PWM signal, so as to achieve accurate overcurrent protection and significantly improve the safety of the circuit. On the other hand, the settings of the first resistor R1, the second resistor R2 and the first capacitor C1 enable the circuit to quickly identify and respond to abnormal current, trigger the protection mechanism in time, and reduce the potential damage risk.
[0058] In a second aspect, the embodiments of the present disclosure provide a control circuit for suppressing overcurrent, which comprises Figure 4As shown, the control circuit for inhibiting overcurrent includes: a control chip IC1, a third switch Q3, a fourth switch Q4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a third capacitor C3, and a fourth capacitor C4; wherein the third switch Q3 and the fourth switch Q4 are both N-type transistors; a first end of the eighth resistor R8 and a first end of the ninth resistor R9 are connected and connected to a reference voltage pin (VREF pin) of the control chip IC1; a second end of the eighth resistor R8, a first end of the third capacitor C3, and a third pole of the third switch Q3 are connected and connected to an oscillation timing pin (RT / CT pin) of the control chip IC1, and a second end of the third capacitor C3 is grounded; a first pole of the third switch Q3 is connected to a second end of the ninth resistor R9; a second pole of the third switch Q3, a first end of the fourth capacitor C4, and a first pole of the fourth switch Q4 are connected and connected to the reference voltage pin (VREF pin) of the control chip IC1 through the tenth resistor R10; a second pole of the fourth switch Q4 is connected to an internal error amplifier output pin of the control chip IC1; a third pole of the fourth switch Q4 is connected to a second end of the fourth capacitor C4 and then grounded; a first end and a second end of the eleventh resistor R11 are respectively connected to the internal error amplifier output pin (COMP pin) of the control chip IC1 and the second pole of the fourth switch Q4; a first end and a second end of the twelfth resistor R12 are respectively connected to the second pole of the fourth switch Q4 and the third pole of the fourth switch Q4.
[0059] In the above embodiment, the eleventh resistor R11 and the twelfth resistor R12 belong to the overcurrent response module 1, cooperate with the Vcom pin of the control chip, and realize obtaining the overcurrent signal of the measured circuit. The third switch Q3, the eighth resistor R8, the ninth resistor R9, and the third capacitor C3 belong to the adjustment module 2. When the third switch Q3 is in the on state, the overcurrent protection signal is input to the control chip. When the third switch Q3 is in the off state, the control chip exits the overcurrent protection.
[0060] In some embodiments, the eleventh resistor R11 and the twelfth resistor R12 constitute a voltage dividing circuit for controlling the voltage Vcom, and then controlling the on or off of the fourth switch Q4 through the voltage Vcom.
[0061] For example, in the normal working state of the circuit, the voltage Vcom is usually designed to be less than a preset threshold (for example, 4V). However, when the circuit appears abnormal conditions, such as low output voltage or output short circuit, the voltage Vcom will rise to be greater than the preset threshold (for example, 4V). The above voltage change provides a protection mechanism for the circuit, which can change the working state (on or off) of the fourth switch Q4 in time based on the change of the voltage Vcom, so as to prevent the circuit from being damaged or performance degradation.
[0062] It should be noted that the preset threshold value of 4V is only an example, and in actual application, the preset threshold value can be reasonably set according to the specific circuit.
[0063] In some embodiments, the third switch tube is an NMOS transistor, and the fourth switch tube is an NPN type transistor; wherein the first pole of the third switch tube is the drain, the second pole of the third switch tube is the gate, and the third pole of the third switch tube is the source; the first pole of the fourth switch tube is the collector, the second pole of the fourth switch tube is the base, and the third pole of the fourth switch tube is the emitter.
[0064] In some embodiments, the capacitance value of the fourth capacitor is in the range of 100nF-150nF, and the resistance value of the tenth resistor is in the range of 10kΩ-20kΩ. More specifically, the capacitance value of the fourth capacitor can be 100nF, 125nF or 150nF, and the resistance value of the tenth resistor can be 10kΩ, 15kΩ or 20kΩ.
[0065] In some embodiments, Figure 4 The model of the control chip IC1 shown is UCC28C44. Next, with reference to Figure 4 、 Figure 5 、 Figure 6 and Figure 7 the working principle of the control circuit for suppressing overcurrent will be described in detail.
[0066] Figure 5 、 Figure 6 and Figure 7 respectively show different cases of the relationship between the gate-source voltage Vgs of the third switch tube Q3 and time, and the relationship between the voltage Vcom and time.
[0067] As shown in Figure 4 , the eighth resistor R8 and the third capacitor C3 constitute an oscillation circuit of the control chip IC1.
[0068] As shown in Figure 4 and Figure 6 , during the starting process of the circuit, when the supply voltage VDD reaches the working voltage threshold of the chip IC1, the reference voltage Vref will gradually rise from 0V to 5V at time s1. During this process, the reference voltage Vref charges the fourth capacitor C4 through the tenth resistor R10. With the rise of the gate-source voltage Vgs of the third switch tube Q3, when the gate-source voltage Vgs of the third switch tube Q3 reaches the turn-on voltage Vgs(on) of the third switch tube Q3 at time s2, the third switch tube Q3 starts to conduct, connecting the ninth resistor R9 to the oscillation circuit of the control chip IC1. In this way, the switching frequency of the PWM signal can be gradually increased (from frequency f1 to frequency f2), thereby dynamically adjusting the switching frequency of the PWM signal.
[0069] By reasonably setting the parameters of the tenth resistor R10 and the fourth capacitor C4, the duration of the frequency change required by the circuit (such as the duration of the frequency f2 or the duration of the frequency f1) can be accurately controlled, and thus the size of the starting current can be effectively controlled. Exemplarily, the duration of the frequency f1 is the time interval between the time s2 and the time s1, and the duration of the frequency f2 is the time interval between the time s3 and the time s2.
[0070] In the normal working state of the circuit, if an output short circuit occurs, as shown in Figure 5 and Figure 7 , at the time s3, the voltage Vcom will be rapidly pulled up from a lower voltage value to a high voltage level of 5V or above. This change triggers the fourth switch tube Q4 to turn on, and then the gate voltage Vg of the third switch tube Q3 is pulled down to 0V, at this time the gate-source voltage Vgs of the third switch tube Q3 becomes negative, and the third switch tube Q3 is turned off. With the turn-off of the third switch tube Q3, the ninth resistor R9 is removed from the oscillation circuit, resulting in a decrease in the switching frequency. This reduced switching frequency reduces the proportion of the minimum duty cycle in the entire working frequency, effectively reducing the maximum excitation current, thereby protecting the circuit from damage caused by short circuit.
[0071] Compared with Figure 6 , Figure 7 , the control circuit of the embodiment of the present disclosure for suppressing overcurrent when an output short circuit occurs reduces the switching frequency from f2 to f1. As shown in Figure 5 and Figure 7 , the working waveform when the output short circuit occurs shows the change of the frequency, in which the frequency f1 is lower than the normal working frequency f2. On the one hand, the safety of the circuit is improved, and on the other hand, the response ability of the circuit to abnormal conditions is enhanced, ensuring that the circuit can quickly respond when facing abnormal conditions such as output short circuit, maintaining the stability and reliability of the system. By adjusting the parameters of the tenth resistor R10 and the fourth capacitor C4, the turn-on time of the third switch tube Q3 can be flexibly controlled, and thus the starting current and the response time can be controlled to adapt to different application requirements.
[0072] In some embodiments, as shown in Figure 5 , the duration of the frequency f2 is the time interval between the time s3 and the time s2, and the duration of the frequency f1 is the time interval between the time s4 and the time s3.
[0073] In some embodiments, as shown in Figure 7As shown, in the first time period, the duration of frequency f1 is the time interval between time s2 and time s1; in the second time period, the duration of frequency f2 is the time interval between time s3 and time s2; in the third time period, the duration of frequency f1 is the time interval between time s4 and time s3; and in the fourth time period, the duration of frequency f2 is the time interval between time s5 and time s4.
[0074] It should be noted that, Figure 5 and Figure 7 In this context, time s2 represents the start time of frequency f2, or the time when the frequency changes from frequency f1 to frequency f2. Figure 5 and Figure 7 In the diagram, time s3 represents the moment when the frequency changes from frequency f2 to frequency f1. Figure 5 and Figure 7 The time s4 in the equation represents either the end of frequency f1 or the moment when frequency f1 begins to change to frequency f2.
[0075] In some embodiments, such as Figure 7 As shown, when the control chip IC1 receives the start signal and the supply voltage VDD reaches the start threshold, the reference voltage Vref will gradually rise from 0V to 5V at time s1. During this process, the gate-source voltage Vgs of the third switch Q3 also rises slowly. Because the output voltage is approaching or has already reached the preset value, or due to the effect of the soft-start circuit, the voltage Vcom signal will slowly increase until it reaches a stable state. At this time, the minimum duration of the PWM signal frequency f1 (the time interval between time s2 and time s1) is determined by the parameters of the tenth resistor R10 and the fourth capacitor C4. During the start-up phase, due to the large difference between the output voltage and the preset output voltage, the voltage Vcom will rise rapidly. Subsequently, as the output voltage gradually reaches the set value, the voltage Vcom begins to decrease and eventually stabilizes. Thus, the circuit operates at a lower frequency during startup, reducing the start-up current and protecting the circuit from overcurrent surges. As the output voltage stabilizes, the PWM frequency gradually increases to the normal operating frequency (e.g., frequency f2), at which point the circuit enters normal operation. By precisely controlling the parameters of the tenth resistor R10 and the fourth capacitor C4, the circuit can be ensured to operate stably and reliably under different load and input conditions, while reducing energy consumption and improving overall efficiency.
[0076] In some embodiments, the frequency f1 ranges from 30kHz to 40kHz, and the frequency f2 ranges from 60kHz to 70kHz. More specifically, the frequency f1 ranges from 30kHz, 35kHz, or 40kHz, and the frequency f2 ranges from 60kHz, 65kHz, or 70kHz.
[0077] In other embodiments, such as Figure 8 As shown, if the voltage Vcom reaches a high level before the third switch Q3 is turned on, that is, at time s6, the voltage Vcom reaches a high level, but the gate-source voltage Vgs of the third switch Q3 has not yet reached the turn-on voltage Vgs(on) of the third switch Q3, then the fourth switch Q4 is turned on, which pulls the gate voltage Vg of the third switch Q3 down to 0V. At this time, the gate-source voltage Vgs of the third switch Q3 becomes negative, and the third switch Q3 is still in the off state, and the switching frequency remains at f1.
[0078] Until time s7, as the voltage Vcom gradually decreases, the gate-source voltage Vgs of the third switch Q3 gradually increases. When the gate-source voltage Vgs of the third switch Q3 reaches its turn-on voltage Vgs(on) at time s7, the third switch Q3 begins to conduct, connecting the ninth resistor R9 to the oscillation circuit of the control chip IC1. This allows the switching frequency of the PWM signal to gradually increase (from frequency f1 to frequency f2). It is understandable that... Figure 8 In the example, even if the voltage Vcom reaches a high level before the third switch Q3 turns on, the duration of the frequency change required by the circuit (e.g., the duration of frequency f2 or the duration of frequency f1) can still be controlled, thereby effectively controlling the magnitude of the startup current. For example, Figure 8 The duration of the intermediate frequency f1 is the time interval between time s7 and time s6, and the duration of the frequency f2 is the time interval between time s8 and time s7.
[0079] Based on the above two embodiments and Figure 2 and Figure 5 As can be seen, both embodiments include a first switching transistor Q1 ( Figure 5 The fourth switch Q4), the second switch Q2 ( Figure 5 The third switch Q3), the first capacitor C1 Figure 5 The fourth capacitor C4) and the first resistor R1 Figure 5The tenth resistor R10 is used, and the first capacitor C1 (or the fourth capacitor C4) is connected across the first terminal of the first switch Q1 (or the fourth switch Q4) and the third terminal of the first switch Q1 (or the fourth switch Q4). The first terminal of the first switch Q1 (or the fourth switch Q4) is connected to the reference voltage pin of the control chip through the first resistor R1 (or the tenth resistor R10). When the circuit under test is overcurrent, the first switch Q1 (or the fourth switch Q4) is turned on, and the voltage of the first capacitor C1 (or the fourth capacitor C4) is clamped to 0V. At this time, the second switch Q2 (or the third switch Q3) is turned on. After the control chip receives the overcurrent protection signal, the equivalent frequency or equivalent duty cycle output is reduced, thereby realizing overcurrent protection for the circuit under test. When the overcurrent in the circuit under test disappears, the first switch Q1 (or the fourth switch Q4) turns off, and the first capacitor C1 (or the fourth capacitor C4) is charged. When the capacitor voltage meets the turn-off voltage of the second switch Q2 (or the third switch Q3), the second switch Q2 (or the third switch Q3) turns off, and the frequency or duty cycle output by the control chip returns to the normal level before protection, thereby causing the circuit under test to exit overcurrent protection.
[0080] The on and off states of the switching transistors correspond to the input of overcurrent protection signals and overcurrent exit signals to the control chip, respectively. In the above embodiment, when the circuit under test experiences overcurrent, the corresponding second switching transistor Q2 (or third switching transistor Q3) is in the on state. In other embodiments, when the circuit under test experiences overcurrent, the second switching transistor Q2 (or third switching transistor Q3) may be in the off state. Similarly, those skilled in the art can interchange the on and off states of the first switching transistor Q1 (or fourth switching transistor Q4), which is not limited here.
[0081] Thirdly, embodiments of this disclosure provide a switching power supply, including: a forward converter circuit or a flyback circuit, and any of the overcurrent suppression control circuits in the foregoing embodiments.
[0082] In some embodiments, such as Figure 9 As shown, the switching power supply 10 includes a flyback circuit 11 and any of the overcurrent suppression control circuits 12 in the aforementioned embodiments. The structure of the overcurrent suppression control circuit 12 can be referred to in the above embodiments, and will not be repeated here.
[0083] In other embodiments, the switching power supply includes a forward converter circuit and any of the overcurrent suppression control circuits in the foregoing embodiments.
[0084] It is understood that, since the switching power supply of this embodiment adopts the above-mentioned overcurrent suppression control circuit technical solution, the switching power supply has all the beneficial effects of the above-mentioned overcurrent suppression control circuit.
[0085] In a fourth aspect, the embodiments of the present disclosure provide a power supply device, which comprises the switching power supply provided by the above-mentioned embodiments.
[0086] It should be noted that the above description of the device embodiments is similar to the description of the control circuit embodiments for suppressing overcurrent, and has similar beneficial effects as the control circuit embodiments for suppressing overcurrent. For technical details not disclosed in the device embodiments of the present disclosure, please refer to the description of the control circuit embodiments for suppressing overcurrent of the present disclosure.
[0087] It should be understood that the "an embodiment" or "some embodiments" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification does not necessarily mean the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that the size of the sequence number of each process in various embodiments of the present disclosure does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above-mentioned embodiments of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiments.
[0088] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.
Claims
1. A control circuit for inhibiting overcurrent flow, characterized by, The control chip, the first switch tube, the first capacitor, the first resistor, the overcurrent response module and the adjustment module are included. The adjustment module includes a second switch tube, which inputs an overcurrent protection signal to the control chip when in a first state, and inputs an overcurrent exit signal to the control chip when in a second state, and the first state is an on state or an off state. The overcurrent response module is configured to obtain an overcurrent signal. The first pole of the first switch tube and the third pole of the first switch tube are connected across the first capacitor, the second pole of the first switch tube is connected to the overcurrent response module, the first pole of the first switch tube is also connected to the reference voltage end pin of the control chip through the first resistor, the second switch tube is in the first state when the first switch tube receives the overcurrent signal, and the second switch tube is in the second state when the first switch tube does not receive the overcurrent signal and the voltage of the first capacitor reaches a preset voltage value. The overcurrent response module further includes a third resistor, a fifth resistor and a first diode, and the first switch tube is an N-type transistor.
2. The control circuit to suppress overcurrent flow of claim 1, wherein, The second pole of the first switch tube is connected to the first end of the third resistor and then connected to the current sampling end through the first diode, and the third pole of the first switch tube is connected to the second end of the third resistor and grounded through the fifth resistor. The adjustment module further includes a second resistor, a fourth resistor, a seventh resistor and a second capacitor, and the second switch tube is a P-type transistor.
3. The control circuit to suppress overcurrent flow of claim 2, wherein, The first pole of the first switch tube is connected to the second pole of the second switch tube through the second resistor, the first end of the fourth resistor is connected to the second end of the third resistor, and the second end of the fourth resistor is connected to the current detection input end pin of the control chip. The first end of the seventh resistor is connected to the first pole of the second switch tube, and the second end of the seventh resistor is connected to the second end of the fourth resistor and then grounded through the second capacitor. The overcurrent control circuit further includes a second diode and a sixth resistor, the cathode of the second diode is connected to the second pole of the first switch tube through the sixth resistor, and the anode of the second diode is connected to the cathode of the first diode.
4. The control circuit to suppress overcurrent flow of claim 2, wherein, The capacitance value of the first capacitor ranges from 10nF to 30nF.
5. The control circuit to suppress overcurrent flow of claim 3, wherein, The resistance value of the first resistor ranges from 10kΩ to 20kΩ. The resistance value of the second resistor ranges from 3kΩ to 5kΩ. The adjustment module further includes an eighth resistor, a ninth resistor and a third capacitor, and the second switch tube and the first switch tube are both N-type transistors.
6. The control circuit to suppress overcurrent flow of claim 2, wherein, The first end of the eighth resistor and the first end of the ninth resistor are connected and then connected to the reference voltage pin of the control chip. The second end of the eighth resistor, the first end of the third capacitor and the third pole of the second switch tube are connected and then connected to the oscillation timing pin of the control chip, and the second end of the third capacitor is grounded. The first electrode of the second switch tube is connected with the second end of the ninth resistor, and the second electrode of the second switch tube is connected with the first electrode of the first switch tube.
7. The control circuit to suppress overcurrent flow of claim 6, wherein, The overcurrent response module further comprises an eleventh resistor and a twelfth resistor. The first end and the second end of the eleventh resistor are respectively connected with an internal error amplifier output end pin of the control chip and the second electrode of the first switch tube. The first end and the second end of the twelfth resistor are respectively connected with the second electrode of the first switch tube and the third electrode of the first switch tube.
8. The control circuit to suppress overcurrent flow of claim 7, wherein, The capacitance value of the first capacitor ranges from 100nF to 150nF, and the resistance value of the first resistor ranges from 10kΩ to 20kΩ.
9. A switching power supply, characterized by Comprise: A forward or flyback circuit and the control circuit for suppressing overcurrent according to any one of claims 1 to 8.
10. A power supply device characterized by comprising: A switching power supply according to claim 9.