Deposition mask

Abstract

A deposition mask is disclosed. The deposition mask includes: a substrate; a first inorganic layer disposed on the substrate; and a mask film disposed on the first inorganic layer, in which a cross-sectional structure of the mask film includes a second inorganic layer including a plurality of grooves filled with insulating layers.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0043052, filed on March 29, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This utility model application relates to a deposition mask, and more specifically, to a deposition mask and a method for manufacturing a deposition mask. Background Technology

[0004] Wearable devices that focus at a short distance from the user's eyes are being developed in the form of glasses or helmets. For example, wearable devices could be head-mounted displays (HMDs) or augmented reality (AR) glasses. These wearable devices provide users with AR or virtual reality (VR) visuals.

[0005] Wearable devices such as HMDs or AR glasses require display specifications of approximately 3000 PPI (pixels per inch) or greater, allowing users to use them for extended periods without experiencing dizziness. To this end, organic light-emitting diodes on silicon (OLEDoS) technology is being proposed for small, high-resolution organic light-emitting display devices. OLEDoS is a technology for placing organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) is disposed.

[0006] To manufacture high-resolution display panels with approximately 3000 PPI (pixels per inch) or greater, high-resolution deposition masks are required. As deposition masks for manufacturing OLEDoS display panels, a method is being investigated that involves depositing inorganic films on a silicon substrate and patterning the deposited inorganic films to form a mask film. However, due to the thinness of the mask film formed from the inorganic film, the mask has a high risk of breakage. Utility Model Content

[0007] This utility model application provides a deposition mask that can reduce mask damage by increasing the rigidity of the mask, and a method for manufacturing the deposition mask.

[0008] According to an embodiment, a method for manufacturing a deposition mask includes: depositing a first inorganic layer on a substrate; depositing a second inorganic layer on the first inorganic layer; forming a plurality of grooves in the second inorganic layer and filling the formed plurality of grooves with an insulating layer; forming a photoresist pattern including a plurality of first openings corresponding to cell openings on the second inorganic layer including the insulating layer; using the photoresist pattern as a mask to etch the second inorganic layer located at the periphery of the plurality of grooves; and forming cell openings by etching the substrate and the first inorganic layer in a downward direction from the rear surface facing the substrate.

[0009] In one embodiment, forming a cell opening includes exposing a mask membrane disposed in the cell opening.

[0010] In an embodiment, the cross-sectional structure of the mask film includes a second inorganic layer and an insulating layer. The second inorganic layer includes a plurality of grooves, and the insulating layer fills the plurality of grooves.

[0011] In this embodiment, the material of the second inorganic layer is the same as the material of the insulating layer.

[0012] In this embodiment, the material of the second inorganic layer is different from the material of the insulating layer.

[0013] In this embodiment, the substrate comprises silicon (Si).

[0014] In an embodiment, the first inorganic layer comprises silicon oxide (SiO2). x ).

[0015] In an embodiment, the second inorganic layer comprises silicon nitride (SiN). x ).

[0016] In this embodiment, the insulating layer comprises silicon oxide (SiO2). x ) or silicon nitride (SiN) x ).

[0017] In an embodiment, when the deposition mask is viewed on a plane, the width of each of the plurality of grooves filled with the insulating layer is uniform.

[0018] In one embodiment, when the deposition mask is viewed on a plane, the widths of the multiple grooves filled with the insulating layer are uneven and formed differentially.

[0019] In an embodiment, when the deposition mask is viewed on a plane, a first groove disposed near the center of the substrate has a first width, and when the deposition mask is viewed on a plane, a second groove disposed further away from the center of the substrate than the first groove has a second width less than the first width.

[0020] In an embodiment, the method of manufacturing a deposition mask further includes forming a coating covering the entire surface of the substrate and the entire surface of the mask film using an atomic layer deposition (ALD) method.

[0021] According to an embodiment, the deposition mask includes: a substrate; a first inorganic layer disposed on the substrate; and a mask film disposed on the first inorganic layer, wherein the cross-sectional structure of the mask film includes a second inorganic layer, the second inorganic layer including a plurality of grooves and an insulating layer filling the plurality of grooves.

[0022] In this embodiment, the second inorganic layer and the insulating layer are made of the same material.

[0023] In this embodiment, the second inorganic layer and the insulating layer are layers made of different materials.

[0024] In this embodiment, the substrate is a silicon (Si) substrate.

[0025] In this embodiment, the first inorganic layer is silicon oxide (SiO2). x The first inorganic layer is silicon nitride (SiN), and the second inorganic layer is silicon nitride (SiN). x )layer.

[0026] In an embodiment, when the deposition mask is viewed on a plane, the width of each of the plurality of grooves filled with an insulating layer is formed uniformly or differentially.

[0027] In an embodiment, when the deposition mask is viewed on a plane, a first groove disposed near the center of the substrate has a first width, and when the deposition mask is viewed on a plane, a second groove disposed further away from the center of the substrate than the first groove has a second width less than the first width.

[0028] According to an embodiment, a deposition mask and a method for manufacturing the deposition mask are provided, and more specifically, a deposition mask capable of reducing mask damage by increasing the rigidity of the mask and a method for manufacturing the deposition mask are provided.

[0029] The effects of this utility model application are not limited to those described above, and other effects not described herein will become apparent to those skilled in the art based on the following description. Attached Figure Description

[0030] The above and other aspects and features of this utility model application will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 This is an exploded perspective view of the display device according to an embodiment;

[0032] Figure 2 This is a schematic block diagram illustrating a display device according to an embodiment;

[0033] Figure 3 This is a schematic equivalent circuit diagram of the first sub-pixel according to an embodiment;

[0034] Figure 4 This is a layout diagram showing an example of a display panel according to an embodiment;

[0035] Figure 5 This illustrates an embodiment. Figure 4 Layout diagram of the display area;

[0036] Figure 6 This illustrates an embodiment. Figure 4 Layout diagram of the display area;

[0037] Figure 7 It is shown along the embodiment Figure 5 A cross-sectional view of the display panel taken by line I1-I1';

[0038] Figure 8 This is a perspective view of a head-mounted display according to an embodiment;

[0039] Figure 9 This illustrates an embodiment. Figure 8 Exploded perspective view of a head-mounted display;

[0040] Figure 10 This is a perspective view showing another example of a head-mounted display according to an embodiment;

[0041] Figure 11 This is a perspective view of the mask according to an embodiment;

[0042] Figure 12 This is a schematic plan view of the mask according to an embodiment;

[0043] Figure 13 It is a cross-sectional view used to illustrate the process steps of a method for manufacturing a mask according to an embodiment;

[0044] Figure 14 It is a cross-sectional view used to illustrate the process steps of a method for manufacturing a mask according to an embodiment;

[0045] Figure 15 It is a cross-sectional view used to illustrate the process steps of a method for manufacturing a mask according to an embodiment;

[0046] Figure 16 It is a cross-sectional view used to illustrate the process steps of a method for manufacturing a mask according to an embodiment;

[0047] Figure 17 This is a plan view of the mask according to an embodiment;

[0048] Figure 18 It is a plan view of the mask according to the embodiment; and

[0049] Figure 19This is a cross-sectional view of a mask used to illustrate the process steps of depositing a protective film on a mask according to an embodiment. Detailed Implementation

[0050] The present invention will now be described more fully below with reference to the accompanying drawings, in which embodiments of the present invention are illustrated. However, the present invention may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0051] It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, that layer or substrate may be directly on said other layer or substrate, or an intervening layer may be present. Throughout the specification, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0052] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Therefore, a first element discussed below may be referred to as a second element without departing from the teachings of one or more embodiments. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0053] It will also be understood that when an element, layer, or substrate is referred to as being "connected to" or "bonded to" another element, layer, or substrate, the element, layer, or substrate may be directly on the other element, layer, or substrate, or an intervening element, layer, or substrate may be present. Similarly, those referred to as "below," "left," and "right" include cases where they are directly adjacent to other elements or where another layer or other material is involved. For this purpose, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without an intervening element.

[0054] Unless otherwise stated, the illustrated embodiments are to be understood as providing features that provide variations in some ways in which this disclosure may be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, areas and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the scope of this utility model application.

[0055] The use of crosshairs and / or shading in the accompanying drawings is generally provided to make the boundaries between adjacent elements clear. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, scale, commonalities and / or any other characteristics, properties, etc., of the elements.

[0056] Furthermore, the dimensions and relative dimensions of elements may be exaggerated in the accompanying drawings for clarity and / or descriptive purposes. When embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or two consecutively described processes may be performed in the reverse order of their description. Additionally, the same reference numerals denote the same elements.

[0057] Furthermore, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of a Cartesian coordinate system, and therefore the first direction DR1, the second direction DR2, and the third direction DR3 can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0058] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, or XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0059] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element to another (or more elements) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the term “below” can cover both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and in such cases, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0060] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. Furthermore, when the terms “comprising,” “including,” “having,” and / or “possessing” are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are thus used to interpret inherent deviations in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0061] Various embodiments may be described herein with reference to cross-sectional and / or exploded views as schematic diagrams of examples and / or intermediate structures. Thus, variations in the shapes illustrated will be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the areas specifically shown, but should include deviations in shape caused, for example, by manufacturing. In this way, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and are thus not intended to be limiting.

[0062] In accordance with the conventions of the art, some embodiments are described and illustrated in the accompanying drawings in the form of functional blocks, units, components, and / or modules. Those skilled in the art will understand that these blocks, units, components, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, components, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, component, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of this utility model application, each block, unit, component, and / or module of some embodiments may be physically divided into two or more interactively discrete blocks, units, components, and / or modules. Furthermore, without departing from the scope of this utility model application, some embodiments of blocks, units, components and / or modules can be physically combined into more complex blocks, units, components and / or modules.

[0063] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and should not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0064] Features of the various embodiments of this utility model application can be combined in part or in whole. As will be clearly understood by those skilled in the art, various technical interactions and operations are possible. Various embodiments can be practiced individually or in combination.

[0065] In the following description, embodiments of the present invention will be described with reference to the accompanying drawings.

[0066] Figure 1 This is an exploded perspective view of a display device according to an embodiment. Figure 2 This is a schematic block diagram illustrating a display device according to an embodiment.

[0067] In the embodiments and reference Figure 1 and Figure 2 The display device 10 is a device for displaying moving or still images. According to the embodiments, the display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied as a display unit in a television set, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. In another embodiment, the display device 10 can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0068] According to an embodiment, the display device 10 includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (timing controller) 400, and a power supply circuit (power supply unit) 500.

[0069] In embodiments, the display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but this invention is not limited thereto.

[0070] In an embodiment, such as Figure 2 As shown, the display panel 100 includes a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0071] In this embodiment, the display area DAA includes multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, and multiple data lines DL.

[0072] In this embodiment, multiple pixels PX can be arranged in a matrix on the first direction DR1 and the second direction DR2. Multiple scan lines SL and multiple emission control lines EL can extend on the first direction DR1 and are simultaneously arranged on the second direction DR2. Multiple data lines DL can extend on the second direction DR2 and are simultaneously arranged on the first direction DR1.

[0073] In this embodiment, the multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple transmit control lines EL include multiple first transmit control lines EL1 and multiple second transmit control lines EL2.

[0074] In this embodiment, the plurality of pixels PX includes a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include, for example: Figure 3 The multiple pixel transistors shown can be formed by semiconductor processes and disposed on a semiconductor substrate SSUB (see Figure 7 For example, the multiple data transistors of the data driver 700 can be formed of complementary metal-oxide-semiconductor (CMOS).

[0075] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a corresponding write scan line GWL among multiple write scan lines GWL, a corresponding control scan line GCL among multiple control scan lines GCL, a corresponding bias scan line GBL among multiple bias scan lines GBL, a corresponding first emission control line EL1 among multiple first emission control lines EL1, a corresponding second emission control line EL2 among multiple second emission control lines EL2, and a corresponding data line DL among multiple data lines DL. Furthermore, each of the multiple sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0076] In an embodiment, the non-display area NDA includes a scan driver 610, a transmit driver 620, and a data driver 700.

[0077] In one embodiment, the scan driver 610 includes a plurality of scan transistors, and the emitter driver 620 includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors can be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 7 In CMOS, for example, multiple scanning transistors and multiple light-emitting transistors can be formed. Although in Figure 2 The diagram shows a scan driver 610 positioned on the left side of the display area DAA and a transmit driver 620 positioned on the right side of the display area DAA, but this application is not limited thereto. For example, in another embodiment, the scan driver 610 and the transmit driver 620 may be positioned on the left and right sides of the display area DAA, respectively.

[0078] In an embodiment, the scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of these units may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0079] In one embodiment, the transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622, wherein each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and outputs it sequentially to a first transmit control line EL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and outputs it sequentially to a second transmit control line EL2.

[0080] In one embodiment, the data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 7 In, for example, multiple data transistors can be formed using CMOS.

[0081] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0082] In an embodiment, the heat dissipation layer 200 may overlap the display panel 100 on a third-direction DR3, where DR3 is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100 (e.g., on the rear surface of the display panel 100) and may be used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite with high thermal conductivity or a metal layer containing materials such as silver (Ag), copper (Cu), or aluminum (Al).

[0083] In one embodiment, the circuit board 300 can be electrically connected to the first pad portion PDA1 of the display panel 100 (see [link to embodiment]) using a conductive adhesive component such as an anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible material. Although circuit board 300 is in Figure 1The circuit board 300 is shown unfolded, but it can be bent. In this embodiment, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. This one end of the circuit board 300 may be a first pad portion of the circuit board 300 connected to the display panel 100 using a conductive adhesive component (see [link to circuit board 300]). Figure 4 Multiple first pads PD1 (see) Figure 4 The opposite end of the other end of the ).

[0084] In this embodiment, the timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. The timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signals. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0085] In this embodiment, the power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0086] In this embodiment, each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this embodiment, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 via the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0087] In another embodiment, similar to scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be disposed in the non-display area NDA of display panel 100. In this embodiment, timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors may be formed on a semiconductor substrate SSUB (see [link to semiconductor diagram]) using semiconductor processes. Figure 7 In, for example, multiple timing transistors and multiple power transistors can be formed by CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the data driver 700 and the first pad portion of PDA1 (see...). Figure 4 )between.

[0088] Figure 3 This is a schematic equivalent circuit diagram of the first sub-pixel according to an embodiment.

[0089] In the embodiments and reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to a first drive voltage VSS corresponding to a low potential voltage (see...). Figure 2 The first driving voltage line VSL applied, and the second driving voltage VDD corresponding to the high potential voltage (see...) Figure 2 The second drive voltage line VDL and the third drive voltage VINT corresponding to the initialization voltage (see...) are applied. Figure 2 The third driving voltage line VIL is applied. That is, the first driving voltage line VSL can be a low-potential voltage line, the second driving voltage line VDL can be a high-potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. In this embodiment, the first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0090] In an embodiment, the first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0091] In an embodiment, the light-emitting element LE emits light in response to a drive current Ids flowing through the channel of the first transistor T1, wherein the emission amount of the light-emitting element LE is proportional to the drive current Ids. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this invention is not limited thereto. For example, in another embodiment, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0092] In an embodiment, the first transistor T1 may be a drive transistor that controls the source-drain current Ids (also referred to herein as “drive current Ids”) flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0093] In one embodiment, a second transistor T2 may be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor CP1.

[0094] In one embodiment, a third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal controlling the scan line GCL to connect the first node N1 to the second node N2. For this purpose, since the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0095] In this embodiment, a fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emission control signal on the first emission control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current Ids of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0096] In one embodiment, a fifth transistor T5 may be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0097] In one embodiment, a sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal via the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Therefore, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0098] In one embodiment, a first capacitor CP1 is formed between the drain electrodes of the first node N1 and the second transistor T2, and includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0099] In one embodiment, the second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL, and includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0100] In this embodiment, the first node N1 is the node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0101] In one embodiment, each of transistors T1 to T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of transistors T1 to T6 may be a p-type MOSFET; however, this application is not limited thereto. In another embodiment, each of transistors T1 to T6 may be an n-type MOSFET. In yet another embodiment, some of transistors T1 to T6 may be p-type MOSFETs, and each of the remaining transistors may be an n-type MOSFET.

[0102] Despite Figure 3 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 As shown in the illustration. For example, in another embodiment, the number of transistors and capacitors of the first sub-pixel SP1 is not limited to... Figure 3 The number of transistors and capacitors in the first sub-pixel SP1 shown.

[0103] In addition, the second sub-pixel SP2 (see Figure 2 The equivalent circuit diagram of ) and the third sub-pixel SP3 (see Figure 2 The equivalent circuit diagram of ) can be combined with Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 is omitted in this specification.

[0104] Figure 4 This is a layout diagram showing an example of a display panel according to an embodiment.

[0105] In the embodiments and reference Figure 4 The display area DAA of the display panel 100 includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0106] In one embodiment, the scan driver 610 may be disposed on a first side of the display area DAA, and the transmit driver 620 may be disposed on a second side of the display area DAA. For example, the scan driver 610 may be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 may be disposed on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 may be disposed on the left side of the display area DAA, and the transmit driver 620 may be disposed on the right side of the display area DAA. However, this invention is not limited thereto, and in another embodiment, the scan driver 610 and the transmit driver 620 may be disposed on both sides of the first and second sides of the display area DAA.

[0107] In an embodiment, the first pad portion of PDA1 may include a connection to the circuit board 300 via a conductive adhesive component (see...). Figure 1 Multiple first pads PD1 of the pads or bumps of the display area DAA. The first pad portion PDA1 can be located on the third side of the display area DAA. For example, the first pad portion PDA1 can be located on one side of the display area DAA in the second direction DR2.

[0108] In this embodiment, the first pad portion of PDA1 can be disposed outside the data driver 700 on the second direction DR2. That is, the first pad portion of PDA1 can be disposed closer to the edge of the display panel 100 than the data driver 700.

[0109] In an embodiment, the second pad portion PDA2 may include a plurality of second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The plurality of second pads PD2 may be connected to a fixture or probe pins during the inspection process, or may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0110] In an embodiment, the first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL (see...). Figure 3 This reduces the number of first pads PD1. The first distribution circuit 710 can be disposed on the third side of the display area DDA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DDA in the second direction DR2. That is, the first distribution circuit 710 can be disposed on the lower side of the display area DDA.

[0111] In this embodiment, the second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610 and the transmit driver 620. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0112] Figure 5 and Figure 6 This illustrates an embodiment. Figure 4 A layout diagram of an embodiment of the display area.

[0113] In the embodiments and referenced Figure 5 and Figure 6 Multiple pixel PX (see Figure 4 Each of the sub-pixels includes a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0114] Each of the first launch area EA1, the second launch area EA2, and the third launch area EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape in the plan view.

[0115] In an embodiment, the maximum length of the third transmission region EA3 in the first direction DR1 may be less than the maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1. The maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1 may be substantially the same.

[0116] In this embodiment, the maximum length of the third transmission region EA3 in the second direction DR2 may be longer than the maximum length of the first transmission region EA1 in the second direction DR2 and the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 may be longer than the maximum length of the second transmission region EA2 in the second direction DR2.

[0117] In an embodiment, such as Figure 5 and Figure 6As shown, the first emission region EA1, the second emission region EA2, and the third emission region EA3 can have a hexagonal shape formed by six straight lines in the plan view, but this utility model application is not limited to this. The first emission region EA1, the second emission region EA2, and the third emission region EA3 can have polygonal shapes, circular shapes, elliptical shapes, or irregular shapes other than hexagonal shapes in the plan view.

[0118] In the embodiments and as Figure 5 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 can be arranged adjacent to each other in the second direction DR2. Furthermore, the first emission region EA1 and the third emission region EA3 can be arranged adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 can be arranged adjacent to each other in the first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be different.

[0119] In another embodiment, such as Figure 6 As shown, the first transmission region EA1 and the second transmission region EA2 can be arranged adjacent to each other in the first direction DR1, but the second transmission region EA2 and the third transmission region EA3 can be arranged adjacent to each other in the first diagonal direction DD1, and the first transmission region EA1 and the third transmission region EA3 can be arranged adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction perpendicular to the direction pointed to by the first diagonal direction DD1.

[0120] In an embodiment, the first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. The first color light can be light in the blue wavelength band, the second color light can be light in the green wavelength band, and the third color light can be light in the red wavelength band. For example, in an embodiment, the blue wavelength band can be a wavelength band with the main peak wavelength of light in the range of about 370 nm to about 460 nm, the green wavelength band can be a wavelength band with the main peak wavelength of light in the range of about 480 nm to about 560 nm, and the red wavelength band can be a wavelength band with the main peak wavelength of light in the range of about 600 nm to about 750 nm.

[0121] exist Figure 5 and Figure 6The diagram shows that each of the plurality of pixels PX includes three emission regions EA1, EA2, and EA3, but this invention is not limited thereto. That is, each of the plurality of pixels PX may include four emission regions.

[0122] Furthermore, the layout of the emission regions of multiple pixel PXs is not limited to Figure 5 and Figure 6 The layout is shown in the figure. For example, in another embodiment, the emission regions of the plurality of pixels PX can be configured as a strip structure in which the emission regions are arranged in a first direction DR1, wherein the emission regions are arranged in a diamond shape. Structure or such Figure 6 The diagram shows a hexagonal structure with hexagonal emission regions arranged side by side in a plan view.

[0123] Figure 7 It is shown along the embodiment Figure 5 A cross-sectional view of an example display panel taken by line I1'-I1.

[0124] In the embodiments and reference Figure 7 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), and an optical layer (OPL). The optical layer (OPL) includes an organic layer (APL), a cover layer (CVL), and a polarizer (POL).

[0125] In an embodiment, the semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating layers (SINS1 to SINS3) covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) may be a reference. Figure 3 The transistors T1 to T6 are described.

[0126] In this embodiment, the semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, in this embodiment, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. In another embodiment, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0127] In an embodiment, each of the plurality of well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0128] The lower insulating layer (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating layer (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating layer (SINS) can be disposed on the lower insulating layer (BINS).

[0129] In this embodiment, each of the source region SA and the drain region DA can be a region doped with a second type of impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third-direction DR3. The channel region CH can overlap with the gate electrode GE on the third-direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA can be disposed on the other side of the gate electrode GE.

[0130] In an embodiment, each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA due to the lower insulating layer BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTRs can be increased, thereby preventing breakdown and hot carrier phenomena that may be caused by short channels.

[0131] In this embodiment, the first semiconductor insulating layer SINS1 can be disposed on the semiconductor substrate SSUB and can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2) based materials. x The inorganic layer is formed, but this utility model application is not limited thereto.

[0132] In this embodiment, the second semiconductor insulating layer SINS2 can be disposed on the first semiconductor insulating layer SINS1, and can be made of silicon oxide (SiO2). x The inorganic layer is formed, but this utility model application is not limited thereto.

[0133] In this embodiment, a plurality of contact terminals CTEs may be disposed on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTEs may be connected to any one of the gate electrode GE, source region SA, and drain region DA of each of the plurality of pixel transistors PTRs through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTEs may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them.

[0134] In an embodiment, a third semiconductor insulating layer (SINS3) may be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) may be exposed and not covered by the third semiconductor insulating layer (SINS3). The third semiconductor insulating layer (SINS3) may be made of silicon oxide (SiO2). x The inorganic layer is formed, but this utility model application is not limited thereto.

[0135] In this embodiment, the semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate containing polyimide, etc. In this case, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, and the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0136] In this embodiment, the backplane EBP of the light-emitting element includes multiple conductive layers ML1 to ML8 and multiple vias VA1 to VA9. Additionally, the backplane EBP also includes multiple insulating layers INS1 to INS9.

[0137] In an embodiment, conductive layers ML1 to ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The circuitry for the first sub-pixel SP1 shown. For example, combined with... Figure 3Transistors T1 to T6 are formed only in the semiconductor backplane SBP, and the connection between transistors T1 to T6 and capacitors CP1 and CP2 is achieved through conductive layers ML1 to ML8. Additionally, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through conductive layers ML1 to ML8. A first insulating layer INS1 may be disposed on the semiconductor backplane SBP. Each of the plurality of first vias VA1 may penetrate the first insulating layer INS1 to connect to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the plurality of first conductive layers ML1 may be disposed on the first insulating layer INS1 and may be connected to the first via VA1.

[0138] In one embodiment, a second insulating layer INS2 may be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of the plurality of second vias VA2 may penetrate the second insulating layer INS2 and connect to the exposed first conductive layer ML1. Each of the plurality of second conductive layers ML2 may be disposed on the second insulating layer INS2 and may connect to the second via VA2.

[0139] In one embodiment, a third insulating layer INS3 may be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of the plurality of third vias VA3 may penetrate the third insulating layer INS3 and connect to the exposed second conductive layer ML2. Each of the plurality of third conductive layers ML3 may be disposed on the third insulating layer INS3 and may connect to the third via VA3.

[0140] In one embodiment, a fourth insulating layer INS4 may be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of the plurality of fourth vias VA4 may penetrate the fourth insulating layer INS4 and connect to the exposed third conductive layer ML3. Each of the plurality of fourth conductive layers ML4 may be disposed on the fourth insulating layer INS4 and may connect to the fourth via VA4.

[0141] In one embodiment, a fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the plurality of fifth vias VA5 may penetrate the fifth insulating layer INS5 and connect to the exposed fourth conductive layer ML4. Each of the plurality of fifth conductive layers ML5 may be disposed on the fifth insulating layer INS5 and may connect to the fifth via VA5.

[0142] In one embodiment, a sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the plurality of sixth vias VA6 may penetrate the sixth insulating layer INS6 and connect to the exposed fifth conductive layer ML5. Each of the plurality of sixth conductive layers ML6 may be disposed on the sixth insulating layer INS6 and may connect to the sixth via VA6.

[0143] In one embodiment, a seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the plurality of seventh vias VA7 may penetrate the seventh insulating layer INS7 and connect to the exposed sixth conductive layer ML6. Each of the plurality of seventh conductive layers ML7 may be disposed on the seventh insulating layer INS7 and may connect to the seventh via VA7.

[0144] In one embodiment, an eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the plurality of eighth vias VA8 may penetrate the eighth insulating layer INS8 and connect to the exposed seventh conductive layer ML7. Each of the plurality of eighth conductive layers ML8 may be disposed on the eighth insulating layer INS8 and may connect to the eighth via VA8.

[0145] In this embodiment, the conductive layers ML1 to ML8 and the vias VA1 to VA8 can be formed of substantially the same material. The conductive layers ML1 to ML8 and the vias VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The insulating layers INS1 to INS8 can be made of substantially the same material, and the insulating layers INS1 to INS8 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but this utility model application is not limited thereto.

[0146] In an embodiment, the thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, in an embodiment, the thickness of the first conductive layer ML1 can be approximately... The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately Furthermore, the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be approximately [missing information].

[0147] In an embodiment, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, in an embodiment, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately... Furthermore, the thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately

[0148] In this embodiment, the ninth insulating layer INS9 can be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but this utility model application is not limited thereto.

[0149] In an embodiment, each of the plurality of ninth vias VA9 can penetrate the ninth insulating layer INS9 and connect to the exposed eighth conductive layer ML8. The ninth vias VA9 can be formed of any one or an alloy comprising copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the ninth via VA9 can be approximately...

[0150] In an embodiment, the display element layer EML can be disposed on the light-emitting element backplane EBP, and can include a light-emitting element LE comprising a first electrode AND, a light-emitting stack IL, and a second electrode CAT, a reflective electrode layer RL, a tenth insulating layer INS10 and an eleventh insulating layer INS11, a tenth via VA10, a pixel defining layer PDL, and a plurality of trench TRCs. Each of the plurality of trench TRCs can pass through the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. Additionally, each of the plurality of trench TRCs can pass through the eleventh insulating layer INS11. Due to the trench TRCs, the first stack IL1 and the second stack IL2 can be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or an empty space can be disposed in the trench TRCs.

[0151] In an embodiment, the reflective electrode layer RL may be disposed on the ninth insulating layer INS9, and may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as... Figure 7 As shown, the reflective electrode layer RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0152] In an embodiment, each of the plurality of first reflective electrodes RL1 may be disposed on the ninth insulating layer INS9 and may be connected to the ninth via VA9. The first reflective electrodes RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride comprising any of them. For example, the first reflective electrode RL1 may comprise titanium nitride (TiN).

[0153] In an embodiment, each of the plurality of second reflective electrodes RL2 may be disposed on the first reflective electrode RL1 and may be formed of any one or an alloy comprising copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the second reflective electrode RL2 may comprise aluminum (Al).

[0154] In an embodiment, each of the plurality of third reflective electrodes RL3 may be disposed on the second reflective electrode RL2 and may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride comprising any one of them. For example, the third reflective electrode RL3 may comprise titanium nitride (TiN).

[0155] In an embodiment, the fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3, and may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0156] In an embodiment, since the second reflective electrode RL2 is the electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, in an embodiment, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately Furthermore, the thickness of the second reflective electrode RL2 can be approximately

[0157] In an embodiment, the tenth insulating layer INS10 may be disposed on the ninth insulating layer INS9, wherein the tenth insulating layer INS10 may be disposed between horizontally adjacent reflective electrode layers RL. The tenth insulating layer INS10 may be made of silicon oxide (SiO2). x The inorganic layer is formed, but this utility model application is not limited thereto.

[0158] In this embodiment, the eleventh insulating layer INS11 can be disposed on the tenth insulating layer INS10 and the reflective electrode layer RL, and can be made of silicon oxide (SiO2). x The inorganic layer is formed, but this utility model application is not limited thereto. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be optical auxiliary layers through which light emitted from the light-emitting element LE is reflected by the reflective electrode layer RL.

[0159] In an embodiment, and in order to adjust the resonant distance of the light emitted by the light-emitting element LE from at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the tenth insulating layer INS10 or the eleventh insulating layer INS11 may not be disposed below the first electrode AND. For example, the first electrode AND of the first sub-pixel SP1 may be directly disposed on the reflective electrode layer RL. The eleventh insulating layer INS11 may be disposed below the first electrode AND of the second sub-pixel SP2. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be disposed below the first electrode AND of the third sub-pixel SP3. In an embodiment, for example, as Figure 7As shown, in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the eleventh insulating layer INS11 may be disposed below the first electrode AND, and the tenth insulating layer INS10 may not be disposed below the first electrode AND.

[0160] In summary, in the embodiments, the distance between the first electrode AND and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the dominant wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating layer INS10 and the eleventh insulating layer INS11 can be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. However, this invention is not limited thereto.

[0161] Additionally, although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are shown in the embodiments of this specification, a twelfth insulating layer (not shown) may be additionally disposed below the first electrode AND of the first sub-pixel SP1. In this embodiment, the eleventh insulating layer INS11 and the twelfth insulating layer (not shown) may be disposed below the first electrode AND of the second sub-pixel SP2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer (not shown) may be disposed below the first electrode AND of the third sub-pixel SP3.

[0162] In this embodiment, each of the plurality of tenth vias VA10 can penetrate the eleventh insulating layer INS11 in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and can be connected to the exposed reflective electrode layer RL. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0163] In an embodiment, the first electrode AND of each of the plurality of light-emitting elements LE can be disposed on the eleventh insulating layer INS11 and connected to the tenth via VA10. The first electrode AND of each of the plurality of light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, reflective electrodes RL1 to RL4, vias VA1 to VA9, conductive layers ML1 to ML8, and contact terminal CTE. The first electrode AND of each of the plurality of light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride comprising any one of them. For example, the first electrode AND of each of the plurality of light-emitting elements LE can be titanium nitride (TiN).

[0164] In an embodiment, a pixel defining layer (PDL) may be disposed on a portion of the first electrode AND of each of the plurality of light-emitting elements (LEs). The pixel defining layer (PDL) may cover the edge of the first electrode AND of each of the plurality of light-emitting elements (LEs). The pixel defining layer (PDL) may be used to separate a first emission region EA1, a second emission region EA2, and a third emission region EA3.

[0165] In an embodiment, the first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0166] In an embodiment, the pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be disposed on the edge of the first electrode AND of each of the plurality of light-emitting elements LE, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO2). x The inorganic layer is formed, but this utility model application is not limited thereto. The first pixel limiting layer PDL1, the second pixel limiting layer PDL2, and the third pixel limiting layer PDL3 may each have approximately The thickness.

[0167] In an embodiment, when the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 form a single pixel defining layer, the height of this single pixel defining layer increases, making it possible for the first encapsulation inorganic layer TFE1 to be cut due to step coverage. Step coverage refers to the ratio of the degree to which the film is coated on the inclined portion to the degree to which the film is coated on the flat portion. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0168] Therefore, to prevent the first encapsulated inorganic layer TFE1 from being cut off due to step coverage, the first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 can have a cross-sectional structure with stepped portions. For example, the width of the first pixel-defining layer PDL1 can be greater than the width of the second pixel-defining layer PDL2 and the width of the third pixel-defining layer PDL3, and the width of the second pixel-defining layer PDL2 can be greater than the width of the third pixel-defining layer PDL3. The width of the first pixel-defining layer PDL1 refers to the horizontal length of the first pixel-defining layer PDL1 defined in the first direction DR1 and the second direction DR2.

[0169] In an embodiment, the light-emitting stack IL may include multiple intermediate layers, wherein the light-emitting stack IL may include a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3 that emit light of different colors. The first stack layer IL1 and the second stack layer IL2 are not connected discontinuously and are disconnected between adjacent sub-pixels.

[0170] In an embodiment, the first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The first stacked layer IL1 may be disposed on the first electrode AND and the pixel defining layer PDL in the first emission region EA1 of the first sub-pixel SP1.

[0171] In an embodiment, the second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The second stacked layer IL2 may be disposed on the first electrode AND and the pixel defining layer PDL in the second emission region EA2 of the second sub-pixel SP2.

[0172] In an embodiment, the third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of the second color, and a third electron transport layer are sequentially stacked. The third stacked layer IL3 may be disposed on the first electrode AND and the pixel defining layer PDL in the first emission region EA1 of the third sub-pixel SP3.

[0173] In an embodiment, the second electrode CAT can be disposed on the third stacked layer IL3 and the pixel defining layer PDL, and can be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency can be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 due to the microcavity effect.

[0174] In this embodiment, the encapsulation layer TFE may be disposed on the display element layer EML, and may include at least one inorganic layer TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0175] In an embodiment, the first encapsulation inorganic layer TFE1 can be disposed on the second electrode CAT, and can be formed wherein the first encapsulation inorganic layer TFE1 is selected from silicon nitride (SiN). x ) layer, silicon oxynitride (SiON) layer and silicon oxide (SiO) layer x A multilayer structure consisting of one or more inorganic layers stacked alternately. The first encapsulation inorganic layer TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0176] In this embodiment, the second encapsulation inorganic layer TFE2 can be disposed on the first encapsulation inorganic layer TFE1, and can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO x The second encapsulation inorganic layer TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic layer TFE2 can be less than the thickness of the first encapsulation inorganic layer TFE1.

[0177] In the embodiments, the organic layer APL may be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the cover layer CVL, and may be an organic layer including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0178] In this embodiment, the CVL cover layer can be disposed on the organic layer APL, and can be a glass substrate or a polymer resin substrate.

[0179] In an embodiment, a polarizing plate (POL) may be disposed on one surface of the CVL cover layer, wherein the polarizing plate POL may be a structure for preventing visibility degradation caused by reflection of external light. The polarizing plate POL may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter-wave plate), but exemplary embodiments of this disclosure are not limited thereto.

[0180] Figure 8 This is a perspective view showing a head-mounted display according to an embodiment. Figure 9 This illustrates an embodiment. Figure 8 An exploded perspective view of an example of a head-mounted display.

[0181] In the embodiments and reference Figure 8 and Figure 9 The head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0182] In this embodiment, the first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. This is because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 1 and Figure 2 The display devices 10 described are substantially the same, so the description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0183] In one embodiment, the first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0184] In this embodiment, the intermediate frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0185] In this embodiment, the control circuit board 1600 may be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data (DATA). Figure 2 The digital video data DATA is transmitted to the first display device 10_1 and the second display device 10_2 via a connector.

[0186] In one embodiment, the control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. In another embodiment, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0187] In this embodiment, the display device housing 1100 is used to house a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 are shown to be separately configured, but this utility model application is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0188] In this embodiment, the first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, a user can view the image on the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image on the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0189] In one embodiment, the headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are kept aligned with the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display 1000 can provide, for example, a lightweight and compact design. Figure 10 The eyeglasses frame shown is not the headband 1300.

[0190] Additionally, the head-mounted display 1000 may include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0191] Figure 10 This is a perspective view showing another example of a head-mounted display according to an embodiment.

[0192] In the embodiments and reference Figure 10 The head-mounted display 1000_1 can be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. According to an embodiment, the head-mounted display 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path alteration component 1070, and a display device housing 1200_1.

[0193] In this embodiment, the display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye via the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines the virtual image displayed on the display device 10_3 with the real image seen through the right eye lens 1020.

[0194] Figure 10 The illustration shows the display device housing 1200_1 positioned at the right end of the support frame 1030, but this application is not limited thereto. For example, in another embodiment, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and in this case, the image displayed on the display device 10_3 can be provided to the user's left eye. In another embodiment, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, and in this case, the user can view the image displayed on the display device 10_3 through both their left and right eyes.

[0195] Figure 11 This is a perspective view of the mask according to an embodiment. Figure 12This is a schematic plan view of the mask according to an embodiment. Figure 11 This is a perspective view showing the state in which a single unit mask UM is separated from multiple unit masks UM. According to Figure 11 and Figure 12 The mask MK shown in the embodiment can be used in the deposition reference. Figure 7 In at least a portion of the process of the described light-emitting stack IL. For example, the light-emitting stack IL can be configured to emit light of different colors in sub-pixels SP1, SP2, and SP3.

[0196] In the embodiments and reference Figure 11 and Figure 12 The mask MK can be a shadow mask in which a mask film MM is disposed on a silicon substrate 1700. According to embodiments, the mask MK can be referred to as a "silicon mask". The mask MK may include a unit mask UM and a mask frame MF.

[0197] According to an embodiment, the mask MK may include a silicon substrate 1700, and a mask film MM may be disposed on the silicon substrate 1700. The mask films MM may be disposed in cell regions 1710 in a matrix arrangement, and each cell region 1710 may be surrounded by a mask rib region 1721. A portion of the silicon substrate 1700 may be disposed in the mask rib region 1721. The mask rib region 1721 may support the mask films MM.

[0198] The mask MM can be a portion of the unit mask UM set in each of multiple unit regions 1710.

[0199] In an embodiment, the silicon substrate 1700 may include a plurality of cell regions 1710 and a mask frame region 1720 in addition to the cell regions 1710. The mask frame region 1720 may include a mask rib region 1721 surrounding each cell region 1710 and an outer frame region 1722 disposed at the outermost periphery of the silicon substrate 1700. A mask frame MF may be disposed in the mask frame region 1720, wherein the mask frame MF may include mask ribs surrounding the cell regions 1710.

[0200] The mask rib region 1721 can be a region that separates the cell regions 1710. For example, the cell regions 1710 can be arranged in a matrix, and the mask ribs provided in the mask rib region 1721 can surround the outer side of the mask film MM provided in each of the plurality of cell regions 1710.

[0201] In an embodiment, a unit mask UM that masks at least a portion of the cell opening COP can be disposed in each of the plurality of cell regions 1710 of the silicon substrate 1700.

[0202] Multiple cell openings (COPs) can penetrate the mask frame MF along the thickness direction of the mask MK (e.g., third-direction DR3), wherein the cell openings (COPs) can be formed by partially etching the silicon substrate 1700 from the back side.

[0203] In an embodiment, each unit mask UM may include a mask film MM, and the mask film MM may include a mask opening OP.

[0204] The mask opening OP of each mask film MM can be referred to as a "hole" or "mask hole". The mask opening OP can penetrate the unit mask UM along the thickness direction of the mask MK (e.g., third direction DR3).

[0205] One unit mask UM can be used in a display panel 100 (see Figure 2 In the deposition process of ), the term "unit mask UM" may be replaced by a term such as "mask unit UM".

[0206] Figures 13 to 16 This is a cross-sectional view illustrating the process steps of a method for manufacturing a mask (deposition mask) according to an embodiment. For example, Figure 16 It could be a cross-sectional view of a portion of the mask that has been cut out, and Figures 13 to 16 Manufacturing can be shown in sequence. Figure 16 A diagram showing the process of the mask is shown.

[0207] In the following text, reference will be made to Figures 13 to 16 A method for manufacturing a mask according to an embodiment is described.

[0208] In the embodiments and referenced Figure 13 A substrate 1810 can be prepared, wherein the substrate 1810 may include silicon (Si). The substrate 1810 may be referred to as a film substrate 1810 or a host substrate 1810, but this disclosure is not limited thereto.

[0209] When preparing the substrate 1810, inorganic layers 1820 and 1830 can be deposited on the substrate 1810. Inorganic layers 1820 and 1830 can be deposited on the entire surface of the substrate 1810. For example, inorganic layers 1820 and 1830 can be deposited on the front surface, side surface, and rear surface.

[0210] According to an embodiment, the inorganic layer 1820 may comprise a single layer. For example, the inorganic layer 1820 may comprise a first inorganic layer 1820, and the material of the first inorganic layer 1820 may comprise silicon (Si) or silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of them.

[0211] According to another embodiment, inorganic layers 1820 and 1830 may include multiple layers. For example, the inorganic layers may include a first inorganic layer 1820 and a second inorganic layer 1830 disposed on the first inorganic layer 1820. The first inorganic layer 1820 may include silicon oxide (SiO2). x The second inorganic layer 1830 may include silicon nitride (SiN). x However, the material of each of the first inorganic layer 1820 and the second inorganic layer 1830 is not limited thereto. For example, in embodiments, the material of each of the first inorganic layer 1820 and the second inorganic layer 1830 may include silicon (Si), silicon nitride (SiN), etc. x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of them.

[0212] In the following, an embodiment of depositing a first inorganic layer 1820 and a second inorganic layer 1830 on a substrate 1810 will be described.

[0213] In the embodiments and referenced Figure 14 Multiple grooves H1 can be formed in the second inorganic layer 1830, and an insulating layer 1840 can be deposited to fill the multiple grooves H1. For example, the material of the insulating layer 1840 may include silicon (Si) or silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of them.

[0214] In an embodiment, the process of forming the groove H1 in the second inorganic layer 1830 may include the steps described below. First, in conjunction with the plurality of cell regions 1710 (see... Figure 12 (or unit opening COP (see)) Figure 11A photoresist pattern (not shown) with multiple openings (not shown) is formed in the corresponding second inorganic layer 1830. Subsequently, the second inorganic layer 1830 corresponding to the multiple unit regions 1710 is etched to a predetermined thickness using the photoresist pattern as a mask to form multiple grooves H1 in the second inorganic layer 1830. Therefore, the second inorganic layer 1830 has multiple grooves H1 in the multiple unit regions 1710. In another embodiment, the second inorganic layer 1830 may have a surface with an irregular shape in the multiple unit regions 1710.

[0215] In this embodiment, after forming the groove H1 in the second inorganic layer 1830, a process for filling the groove H1 with an insulating layer 1840 can be performed. First, the insulating layer 1840 is deposited onto the second inorganic layer 1830. The material of the insulating layer 1840 may include silicon (Si) or silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following. Subsequently, a photoresist pattern (not shown) may be formed on the insulating layer 1840, and the insulating layer 1840 deposited on the upper surface of the second inorganic layer 1830, excluding the groove H1, may be etched by using the photoresist pattern as a mask.

[0216] According to an embodiment, the patterning process of the insulating layer 1840 may not use a photolithography process utilizing photoresist patterns. For example, after depositing the insulating layer 1840 onto the second inorganic layer 1830, a chemical mechanical polishing (CMP) process can be performed on the upper surface of the polishing substrate 1810. Therefore, the insulating layer 1840 deposited on the upper surface of the second inorganic layer 1830, except for the groove H1, can be removed, and the insulating layer 1840 filling the groove H1 can be retained.

[0217] In the embodiments and reference Figure 15 A COP (see cell opening) can be formed on the second inorganic layer 1830, which includes the insulating layer 1840. Figure 11 The photoresist pattern 1910 corresponds to a plurality of first openings OP1. As shown in the figures, the photoresist pattern 1910 can be configured to overlap with the groove H1 filled with the insulating layer 1840 and formed to have a width larger than the width of the groove H1. Therefore, the photoresist pattern 1910 can be formed to completely cover the groove H1 filled with the insulating layer 1840.

[0218] In the embodiments and referenced Figure 16The second inorganic layer 1830, located around the periphery of the plurality of grooves H1, can be etched using a photoresist pattern 1910 as a mask, and the cell opening COP of the exposed mask film MM can be formed by etching the substrate 1810 and the first inorganic layer 1820 in a downward direction from the rear surface of the substrate 1810.

[0219] According to an embodiment, the process for etching the second inorganic layer 1830 can be described as follows. A photoresist pattern 1910 is used as a mask to etch the second inorganic layer 1830 positioned between adjacent recesses H1. Therefore, the second inorganic layer 1830 overlapping with the photoresist pattern 1910 and the insulating layer 1840 filling the recesses H1 of the second inorganic layer 1830 are not etched and are retained, thus completing the cross-sectional structure of the mask film MM. The cross-sectional structure of the mask film MM includes a second inorganic layer 1830 containing a plurality of recesses H1 and an insulating layer 1840 filling the recesses H1.

[0220] The photoresist pattern 1910 can be removed after etching the second inorganic layer 1830.

[0221] According to an embodiment, the step of forming the unit opening COP may include etching the first inorganic layer 1820 deposited on the rear surface of the substrate 1810 and etching the substrate 1810 and the first inorganic layer 1820 deposited on the front surface of the substrate 1810. Here, the first inorganic layer 1820 deposited on the rear surface of the substrate 1810, the substrate 1810, and the first inorganic layer 1820 deposited on the front surface of the substrate 1810 may be etched sequentially. In addition, the etching of the first inorganic layer 1820 deposited on the rear surface of the substrate 1810, the substrate 1810, and the first inorganic layer 1820 deposited on the front surface of the substrate 1810 may be performed in a downward direction facing the rear surface of the substrate 1810.

[0222] According to an embodiment, the material of the second inorganic layer 1830 may be the same as the material of the insulating layer 1840 filled inside the groove H1.

[0223] According to an embodiment, the material of the second inorganic layer 1830 may be different from the material of the insulating layer 1840 filled inside the groove H1.

[0224] As described above, the method for manufacturing a mask according to the embodiment allows the cross-sectional structure of the mask film MM to include a second inorganic layer 1830 and an insulating layer 1840, wherein the second inorganic layer 1830 includes a plurality of grooves H1, and the insulating layer 1840 fills the interior of the plurality of grooves H1. Therefore, the risk of damage due to the thinness of the mask film MM formed by the inorganic layer can be reduced. Furthermore, this invention can reduce sagging of the mask film MM and reduce bending defects in the mask film MM caused by its thinness.

[0225] Figure 17 and Figure 18 This is a plan view of the mask according to an embodiment.

[0226] In the embodiments and referenced Figure 17 and Figure 18 When viewed on a plane, the width of the second inorganic layer 1830 (or the width of the insulating layer 1840) in which the mask MK is filled can be designed into various shapes.

[0227] According to the embodiments, such as Figure 17 As shown, when the mask MK is viewed in a plane, the width of each of the plurality of grooves H1 filled with insulating layer 1840 can be uniform. For example, the grooves H1 filled with insulating layer 1840 can be configured to surround the mask film MM (see Figure 1) when the mask MK is viewed in a plane. Figure 16 The periphery of the opening of the second inorganic layer 1830 (i.e., the mask opening OP of the mask film MM), and the width A1 of the groove H1 can be uniform overall.

[0228] According to the embodiments, such as Figure 18 As shown, when the mask MK is viewed in a plane, the widths of the plurality of grooves H1 filled with the insulating layer 1840 can be non-uniform and can be designed to be different for each partial area. For example, when the mask MK is viewed in a plane, the grooves H1 filled with the insulating layer 1840 can be arranged to surround the mask film MM (see Figure 1). Figure 16 The periphery of the opening (i.e., the mask opening OP of the mask film MM) of the second inorganic layer 1830, and the widths A2 and A3 of the grooves H1 can be non-uniform and can be designed to be different for each partial area. For example, when viewing the mask MK in a plane, the widths A2 and A3 of the multiple grooves H1 filled with the insulating layer 1840 are formed to be different. Adjacent to the substrate 1810 (see Figure 16 The first groove H1, which is set at the center 2011 of the substrate 1810, has a first width A3, and when the mask MK is viewed on a plane, the second groove H1, which is set further away from the center 2011 of the substrate 1810 than the first groove H1, has a second width A2 that is smaller than the first width A3.

[0229] Figure 19 This is a cross-sectional view of a mask used to illustrate the process steps of depositing a protective film on a mask according to an embodiment.

[0230] In the embodiments and reference Figure 19 Considering the reusability of masks, the method of manufacturing a mask may also include forming a coating on the entire surface of the mask. For example, the method of manufacturing a mask also includes forming a mask film MM covering the entire surface of the substrate 1810 and the mask film MM using an atomic layer deposition (ALD) method (see Figure 16 The steps of coating the entire surface of )2111.

[0231] Those skilled in the art to which this application pertains will understand that this application can be implemented in other specific forms without altering its technical spirit or essential features. Therefore, it will be understood that the exemplary embodiments described above are illustrative in all respects and not restrictive. The disclosed embodiments of this application are for general and descriptive purposes only and are not intended to be limiting. Each component specifically shown in the embodiments of this application can be implemented by modification, and such modifications and differences relevant to the application should be interpreted as being included within the scope of this application. Furthermore, embodiments or portions of embodiments can be combined, in whole or in part, without departing from the scope of this application.

Claims

1. A deposition mask, characterized in that, The deposition mask includes: Base; A first inorganic layer is disposed on the substrate; and A mask film is disposed on the first inorganic layer. The cross-sectional structure of the mask film includes a second inorganic layer, which includes a plurality of grooves filled with an insulating layer.

2. The deposition mask as described in claim 1, characterized in that, The second inorganic layer is made of the same material as the insulating layer.

3. The deposition mask as described in claim 1, characterized in that, The second inorganic layer and the insulating layer are layers made of different materials.

4. The deposition mask as described in claim 1, characterized in that, The substrate is a silicon substrate.

5. The deposition mask as described in claim 1, characterized in that, The first inorganic layer is a silicon oxide layer, and The second inorganic layer is a silicon nitride layer.

6. The deposition mask as claimed in claim 1, characterized in that, When the deposition mask is viewed on a plane, the width of each of the plurality of grooves filling the insulating layer is formed uniformly or differentially.

7. The deposition mask as claimed in claim 1, characterized in that, When the deposition mask is viewed on a plane, A first groove, located near the center of the base, has a first width, and The second groove, which is positioned further away from the center of the substrate than the first groove, has a second width that is smaller than the first width.

Images