Program-controlled variable optical attenuator

Abstract

The utility model discloses a program-controlled variable optical attenuator. The program-controlled variable optical attenuator comprises an optical splitter, a variable optical attenuation unit, an optical detector and a control unit, the optical branching device comprises a first optical branching device and a second optical branching device which are responsible for branching input optical signals, so that the flexibility and the expansibility of the system are improved. The adjustable light attenuation unit can change light transmission loss so as to adjust the light attenuation amount. The optical detector detects the attenuated optical power and transmits information to the control unit. The control unit is connected with the light detector and the adjustable light attenuation unit, and adjusts the adjustable light attenuation unit according to the light power information feedback to form a closed loop feedback system. The system can accurately control the light attenuation, track the change of the light signal in real time, ensure the stability of the output light power, improve the reliability and stability of the system, and meet the accurate requirements of different optical communication systems on the light signal power.

Description

Technical Field

[0001] This utility model belongs to the field of optical communication technology, specifically a programmable adjustable optical attenuator. Background Technology

[0002] In optical communication systems, power control of optical signals is crucial. With the rapid development of optical communication technology, the demand for devices capable of precisely and flexibly adjusting the attenuation of optical signals is increasing. Furthermore, during the testing, maintenance, and upgrading of optical networks, it is necessary to flexibly adjust the attenuation of optical signals to simulate different link conditions or to troubleshoot faults. In addition, in the integrated application of optical communication systems with other optical devices (such as optical amplifiers and optical sensors), precise programming control of optical attenuation helps to optimize the performance and coordinate the functions of the entire system.

[0003] Existing technology: Traditional fixed optical attenuators cannot dynamically change the attenuation amount according to actual needs, making it difficult to adapt to complex and ever-changing optical network environments. For example, in optical transmission lines, due to factors such as different transmission distances, fiber loss characteristics, signal source power fluctuations, and different network topologies, it is necessary to dynamically optimize the power of the optical signal to ensure that the signal has an appropriate strength at the receiving end, avoiding receiver saturation due to excessive power or bit errors due to insufficient power. Utility Model Content

[0004] The purpose of this invention is to provide a programmable adjustable optical attenuator to solve the problems mentioned in the background art, where adjustable optical attenuators cannot dynamically change the attenuation amount according to actual needs, making them difficult to adapt to complex and ever-changing optical network environments. This results in high testing costs and low testing efficiency.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0006] A programmable adjustable optical attenuator includes an optical splitter, an adjustable optical attenuation unit, a photodetector, and a control unit; wherein the optical splitter is used to split the input optical signal, and includes a first optical splitter and a second optical splitter.

[0007] The adjustable optical attenuation unit is used to change the loss of light transmission therein, thereby adjusting the amount of optical attenuation; the photodetector is used to detect the attenuated optical power.

[0008] The control unit is connected to the photodetector and the adjustable light attenuation unit respectively. The control unit is used to receive the light power information transmitted from the photodetector.

[0009] According to the above technical solution, the first optical splitter is used in the main optical path. The first optical splitter includes chip U2, capacitor C1, resistor R2, resistor R3 and resistor R4.

[0010] Pins 1 to 5 of chip U2 are connected to a switching circuit;

[0011] Pins 6 to 8 of chip U2 are all grounded; pin 9 of chip U2 is connected to one end of resistor R4; pin 10 of U2 is connected to one end of resistor R3; pin 11 of U2 is connected to one end of resistor R2; the other ends of resistors R2, R3, and R4 are all connected to the power supply.

[0012] Pins 12 to 15 of chip U2 are connected to a switching circuit;

[0013] Pin 16 of chip U2 is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded.

[0014] Pin 16 of chip U2 and capacitor C1 are both connected to the power supply.

[0015] According to the above technical solution, the second optical splitter is used as a reference optical path. The second optical splitter includes chip U3, chip U4, capacitor C2, capacitor C3, capacitor C4, capacitor C7, capacitor C8, resistor R5, resistor R6, and resistor R7.

[0016] Pins 1, 2, 4, and 6 of chip U3 are connected to a switching circuit;

[0017] Pin 3 of chip U3 is connected to pin 3 of chip U4; pins 6, 7, and 8 of chip U3 are all grounded; pins 9, 10, and 11 of chip U3 are connected to the control unit respectively.

[0018] Pins 12, 13, 14, 15, and 16 of chip U3 are connected to a switching circuit;

[0019] Pin 1 of chip U4 is connected to one end of resistors R6 and R5 respectively. The other end of resistor R5 is connected to pin 4 of chip U4 and one end of resistor R7 respectively. The other end of resistor R7 is grounded. The other end of resistor R6 is connected to capacitors C7 and C8 and pin 1 of chip U12 respectively. The other ends of capacitors C7 and C8 are both grounded.

[0020] Pin 5 of chip U4 is connected to one end of capacitor C3 and capacitor C4 respectively; the other end of capacitor C3 and capacitor C4 is grounded.

[0021] According to the above technical solution, chip U4's No. 5, capacitor C3, and capacitor C4 are also connected to the power supply.

[0022] According to the above technical solution, the control unit includes chip U1, capacitor C5 and capacitor C6;

[0023] Pins 32 to 30 of chip U1 are connected to pins 11 to 9 of chip U3, respectively; pins 18 to 14 of chip U1 are connected to the optical output port and the adjustable optical attenuation unit.

[0024] Pin 6 of chip U1 is connected to one end of capacitor C5 and capacitor C6 respectively; the other ends of capacitor C5 and capacitor C6 are grounded; pins 24 and 23 of chip U1 are connected to the photodetector.

[0025] Pin 3 of chip U1 is grounded.

[0026] According to the above technical solution, pin 6 of chip U1, capacitor C5, and capacitor C6 are all still connected to the power supply.

[0027] According to the above technical solution, the photodetector includes chip U9, capacitor C32, capacitor C33, and capacitor C34;

[0028] Pin 1 of chip U9 is connected to pins 2 and 3 of chip U9, one end of capacitor C32, and one end of capacitor C33, respectively.

[0029] Pin 4 of chip U9 is connected to pin 5 of chip U9, capacitor C32, and the other end of capacitor C33, respectively.

[0030] Pins 1, 2, and 3 of chip U9, capacitor C32, and capacitor C33 are all connected to the power supply.

[0031] Pins 4 and 5 of chip U9, the other end of capacitor C32 and capacitor C33 are all grounded;

[0032] Pin 10 of chip U9 is connected to the adjustable light attenuation unit; pin 8 of chip U9 is connected to pin 24 of chip U1; pin 7 of chip U9 is connected to pin 23 of chip U1.

[0033] Pin 9 of chip U9 is connected to one end of capacitor C32; the other end of capacitor C32 is grounded.

[0034] Pin 6 of chip U9 is grounded.

[0035] According to the above technical solution, the tunable attenuation unit includes chip U7, resistor R20, resistor R23, resistor R25, resistor R26 and capacitor C22.

[0036] Pin 2 of chip U7 is connected to one end of resistors R23 and R20 respectively, and the other end of resistor R23 is grounded; the other end of resistor R20 is connected to pin 6 of chip U7 and one end of resistor R26 respectively; the other end of resistor R26 is used to connect to an external output interface.

[0037] Pin 3 of chip U7 is connected to one end of resistor R25, and the other end of resistor R25 is connected to pin 10 of U9.

[0038] Pin 4 of chip U7 is grounded; pin 7 of chip U7 is connected to one end of capacitor C22, and the other end of capacitor C22 is grounded.

[0039] Pin 7 of chip U7 and capacitor C22 are both connected to the power supply.

[0040] According to the above technical solution, the tunable attenuation unit includes chip U10, chip U11, chip U12, chip X1, capacitor C31, capacitor C35, capacitor C36, capacitor C37, capacitor C38, capacitor C39, capacitor C40, capacitor C41, capacitor C42, capacitor C43, capacitor C44, capacitor C45, capacitor C46, ​​resistor R33, resistor R34, resistor R35, resistor R36, resistor R37, resistor R38, resistor R39, resistor R40, resistor R42, resistor R43, and resistor R45;

[0041] Pin 1 of chip U12 is connected to capacitors R6, C7, and C8 respectively; pins 2 and 3 of chip U12 are grounded; pin 4 of chip U12 is connected to capacitors C35 and C42 and the power supply respectively; the other ends of capacitors C35 and C42 are grounded; pins 5 and 6 of chip U12 are both grounded.

[0042] Pin 7 of chip U12 is connected to one end of resistor R37; the other end of resistor R37 is connected to pin 14 of chip U1; pin 8 of chip U12 is connected to one end of resistor R39, and the other end of resistor R39 is connected to pin 17 of chip U1.

[0043] Pin 9 of chip U12 is connected to one end of resistor R40, and the other end of resistor R40 is connected to pin 16 of chip U1; pin 10 of chip U12 is connected to one end of resistor R38, and the other end of resistor R38 is connected to pin 15 of chip U1; pin 11 of chip U12 is connected to one end of resistor R36, and the other end of resistor R36 is connected to pin 18 of chip U1.

[0044] Pin 12 of chip U12 is connected to one end of resistor R42, the other end of resistor R42 is connected to pin 3 of chip X1, pin 4 of chip X1 is connected to one end of capacitor C45 and capacitor C46 respectively, and the other ends of capacitor C45 and capacitor C46 are grounded; pin 4 of chip X1, capacitor C45 and capacitor C46 are all connected to the power supply.

[0045] Pin 1 of chip U12 is connected to one end of resistors R43 and R45 respectively; the other end of resistor R43 is connected to the power supply, and the other end of resistor R45 is grounded; pin 2 of chip U12 is grounded.

[0046] Pin 13 of chip U12 is connected to one end of capacitor C43 and capacitor C44, as well as the power supply; pin 14 of chip U13 is connected to the other end of capacitor C43 and capacitor C44.

[0047] Pin 15 of chip U12 is connected to one end of capacitor C36 and capacitor C37 respectively. Pin 16 of chip U12 is connected to one end of capacitor C36 and capacitor C37, pin 6 and pin 2 of chip U10, and one end of resistor R33 respectively.

[0048] Pin 7 of chip U10 is connected to one end of capacitor C31 and the power supply; the other end of capacitor C31 is grounded.

[0049] Pin 3 of chip U10 is connected to one end of resistor R34. The other end of resistor R34 is connected to the other end of resistor R33, one end of capacitor C38 and capacitor C39, and pin 2 of chip U11. Pin 4 of chip U10 is grounded.

[0050] The other ends of capacitors C38 and C39, as well as pin 3 of chip U11, are all grounded;

[0051] Pin 1 of chip U11 is connected to one end of capacitor C40 and capacitor C41, as well as the power supply. The other ends of capacitors C40 and C41 are grounded.

[0052] According to the above technical solution, pin 12 of chip U13, capacitor C43, and capacitor C44 are all grounded.

[0053] Compared with the prior art, the present invention has the following beneficial effects:

[0054] In this invention, the optical attenuation is adjusted by changing the optical transmission loss through an adjustable optical attenuation unit, and the control unit performs feedback adjustment based on the optical power information detected by the photodetector. This enables precise control of the optical attenuation to meet the precise power requirements of different optical communication systems. The photodetector detects the attenuated optical power in real time and transmits the information to the control unit. The control unit then adjusts the adjustable optical attenuation unit in real time, forming a closed-loop feedback system. This system can track changes in the optical signal in real time, ensuring the stability of the output optical power and improving the reliability and stability of the system.

[0055] Optical splitters split the input optical signal and can simultaneously perform optical attenuation processing on multiple optical paths, increasing the system's flexibility and scalability. They facilitate independent or coordinated control of optical signals from different optical paths to adapt to complex optical communication network architectures and diverse service requirements. Attached Figure Description

[0056] Figure 1 This is the circuit diagram of the first optical splitter of this utility model;

[0057] Figure 2 This is the circuit diagram of the second optical splitter of this utility model;

[0058] Figure 3 This is the circuit diagram of the control unit of this utility model;

[0059] Figure 4 This is the circuit diagram of the photodetector of this utility model;

[0060] Figure 5 This is the circuit diagram of the adjustable light attenuation unit of this utility model;

[0061] Figure 6 This is a circuit diagram of the switching circuit of this utility model. Detailed Implementation

[0062] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0063] Example 1

[0064] A programmable adjustable optical attenuator, specifically relating to a programmable adjustable optical attenuator circuit; including an optical splitter, an adjustable optical attenuation unit, a photodetector, and a control unit; wherein, the optical splitter is used to split the input optical signal, including a first optical splitter and a second optical splitter.

[0065] The adjustable optical attenuation unit is used to change the loss of light transmission therein, thereby adjusting the amount of optical attenuation; the photodetector is used to detect the attenuated optical power.

[0066] The control unit is connected to the photodetector and the adjustable light attenuation unit respectively. The control unit is used to receive the light power information transmitted from the photodetector.

[0067] In this invention, the optical attenuation is adjusted by changing the optical transmission loss through an adjustable optical attenuation unit, and the control unit performs feedback adjustment based on the optical power information detected by the photodetector. This enables precise control of the optical attenuation to meet the precise power requirements of different optical communication systems. The photodetector detects the attenuated optical power in real time and transmits the information to the control unit. The control unit then adjusts the adjustable optical attenuation unit in real time, forming a closed-loop feedback system. This system can track changes in the optical signal in real time, ensuring the stability of the output optical power and improving the reliability and stability of the system.

[0068] Optical splitters split the input optical signal and can simultaneously perform optical attenuation processing on multiple optical paths, increasing the system's flexibility and scalability. They facilitate independent or coordinated control of optical signals from different optical paths to adapt to complex optical communication network architectures and diverse service requirements.

[0069] Example 2

[0070] This embodiment is a further refinement of Embodiment 1.

[0071] like Figure 1 As shown, the first optical splitter is used for the main optical path. The first optical splitter includes chip U2, capacitor C1, resistor R2, resistor R3 and resistor R4.

[0072] Pins 1 to 5 of chip U2 are connected to a switching circuit;

[0073] Pins 6 to 8 of chip U2 are all grounded; pin 9 of chip U2 is connected to one end of resistor R4; pin 10 of U2 is connected to one end of resistor R3; pin 11 of U2 is connected to one end of resistor R2; the other ends of resistors R2, R3, and R4 are all connected to the power supply.

[0074] Pins 12 to 15 of chip U2 are connected to a switching circuit;

[0075] Pin 16 of chip U2 is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded.

[0076] Pin 16 of chip U2 and capacitor C1 are both connected to the power supply.

[0077] The second optical splitter is used for the reference optical path. The second optical splitter includes chip U3, chip U4, capacitors C2, C3, C4, C7, C8, resistors R5, R6, and R7.

[0078] Pins 1, 2, 4, and 6 of chip U3 are connected to a switching circuit;

[0079] Pin 3 of chip U3 is connected to pin 3 of chip U4; pins 6, 7, and 8 of chip U3 are all grounded; pins 9, 10, and 11 of chip U3 are connected to the control unit respectively.

[0080] Pins 12, 13, 14, 15, and 16 of chip U3 are connected to a switching circuit;

[0081] Pin 1 of chip U4 is connected to one end of resistors R6 and R5 respectively. The other end of resistor R5 is connected to pin 4 of chip U4 and one end of resistor R7 respectively. The other end of resistor R7 is grounded. The other end of resistor R6 is connected to capacitors C7 and C8 and pin 1 of chip U12 respectively. The other ends of capacitors C7 and C8 are both grounded.

[0082] Pin 5 of chip U4 is connected to one end of capacitor C3 and capacitor C4 respectively; the other end of capacitor C3 and capacitor C4 is grounded.

[0083] Chip U4's No. 5 capacitor, capacitor C3, and capacitor C4 are all connected to the power supply.

[0084] The control unit includes chip U1, capacitor C5, and capacitor C6;

[0085] Pins 32 to 30 of chip U1 are connected to pins 11 to 9 of chip U3, respectively; pins 18 to 14 of chip U1 are connected to the optical output port and the adjustable optical attenuation unit.

[0086] Pin 6 of chip U1 is connected to one end of capacitor C5 and capacitor C6 respectively; the other ends of capacitor C5 and capacitor C6 are grounded; pins 24 and 23 of chip U1 are connected to the photodetector.

[0087] Pin 3 of chip U1 is grounded.

[0088] Pin 6 of chip U1, capacitor C5, and capacitor C6 are still connected to the power supply.

[0089] The photodetector includes chip U9, capacitor C32, capacitor C33, and capacitor C34;

[0090] Pin 1 of chip U9 is connected to pins 2 and 3 of chip U9, one end of capacitor C32, and one end of capacitor C33, respectively.

[0091] Pin 4 of chip U9 is connected to pin 5 of chip U9, capacitor C32, and the other end of capacitor C33, respectively.

[0092] Pins 1, 2, and 3 of chip U9, capacitor C32, and capacitor C33 are all connected to the power supply.

[0093] Pins 4 and 5 of chip U9, the other end of capacitor C32 and capacitor C33 are all grounded;

[0094] Pin 10 of chip U9 is connected to the adjustable light attenuation unit; pin 8 of chip U9 is connected to pin 24 of chip U1; pin 7 of chip U9 is connected to pin 23 of chip U1.

[0095] Pin 9 of chip U9 is connected to one end of capacitor C32; the other end of capacitor C32 is grounded.

[0096] Pin 6 of chip U9 is grounded.

[0097] The adjustable light attenuation unit includes chip U7, resistors R20, R23, R25, R26, and capacitor C22;

[0098] Pin 2 of chip U7 is connected to one end of resistors R23 and R20 respectively, and the other end of resistor R23 is grounded; the other end of resistor R20 is connected to pin 6 of chip U7 and one end of resistor R26 respectively; the other end of resistor R26 is used to connect to an external output interface.

[0099] Pin 3 of chip U7 is connected to one end of resistor R25, and the other end of resistor R25 is connected to pin 10 of U9.

[0100] Pin 4 of chip U7 is grounded; pin 7 of chip U7 is connected to one end of capacitor C22, and the other end of capacitor C22 is grounded.

[0101] Pin 7 of chip U7 and capacitor C22 are both connected to the power supply.

[0102] The adjustable light attenuation unit includes chips U10, U11, U12, X1, capacitors C31, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, ​​resistors R33, R34, R35, R36, R37, R38, R39, R40, R42, R43, and R45.

[0103] Pin 1 of chip U12 is connected to capacitors R6, C7, and C8 respectively; pins 2 and 3 of chip U12 are grounded; pin 4 of chip U12 is connected to capacitors C35 and C42 and the power supply respectively; the other ends of capacitors C35 and C42 are grounded; pins 5 and 6 of chip U12 are both grounded.

[0104] Pin 7 of chip U12 is connected to one end of resistor R37; the other end of resistor R37 is connected to pin 14 of chip U1; pin 8 of chip U12 is connected to one end of resistor R39, and the other end of resistor R39 is connected to pin 17 of chip U1.

[0105] Pin 9 of chip U12 is connected to one end of resistor R40, and the other end of resistor R40 is connected to pin 16 of chip U1; pin 10 of chip U12 is connected to one end of resistor R38, and the other end of resistor R38 is connected to pin 15 of chip U1; pin 11 of chip U12 is connected to one end of resistor R36, and the other end of resistor R36 is connected to pin 18 of chip U1.

[0106] Pin 12 of chip U12 is connected to one end of resistor R42, the other end of resistor R42 is connected to pin 3 of chip X1, pin 4 of chip X1 is connected to one end of capacitor C45 and capacitor C46 respectively, and the other ends of capacitor C45 and capacitor C46 are grounded; pin 4 of chip X1, capacitor C45 and capacitor C46 are all connected to the power supply.

[0107] Pin 1 of chip U12 is connected to one end of resistors R43 and R45 respectively; the other end of resistor R43 is connected to the power supply, and the other end of resistor R45 is grounded; pin 2 of chip U12 is grounded.

[0108] Pin 13 of chip U12 is connected to one end of capacitor C43 and capacitor C44, as well as the power supply; pin 14 of chip U13 is connected to the other end of capacitor C43 and capacitor C44.

[0109] Pin 15 of chip U12 is connected to one end of capacitor C36 and capacitor C37 respectively. Pin 16 of chip U12 is connected to one end of capacitor C36 and capacitor C37, pin 6 and pin 2 of chip U10, and one end of resistor R33 respectively.

[0110] Pin 7 of chip U10 is connected to one end of capacitor C31 and the power supply; the other end of capacitor C31 is grounded.

[0111] Pin 3 of chip U10 is connected to one end of resistor R34. The other end of resistor R34 is connected to the other end of resistor R33, one end of capacitor C38 and capacitor C39, and pin 2 of chip U11. Pin 4 of chip U10 is grounded.

[0112] The other ends of capacitors C38 and C39, as well as pin 3 of chip U11, are all grounded;

[0113] Pin 1 of chip U11 is connected to one end of capacitor C40 and capacitor C41, as well as the power supply. The other ends of capacitors C40 and C41 are grounded.

[0114] Pin 12 of chip U13, capacitor C43, and capacitor C44 are all grounded.

[0115] This embodiment provides a specific implementation method for a switching circuit.

[0116] like Figure 6 As shown, the switching circuit includes: chip U6, capacitors C9, C12, C14, C15, C16, C21, C23, C27, C30, resistors R8, R17, R19, R21, R24, R30, R31, and R32.

[0117] Pin 1 of chip U6 is connected to pin 3 of chip U2; pins 2 and 3 of chip U6 are both grounded; pin 5 of chip U6 is connected to the power supply, one end of capacitor C14, and one end of capacitor C15; the other ends of capacitor C14 and capacitor C15 are both grounded.

[0118] Pin 4 of chip U6 is connected to one end of capacitors C9, C12, C16, C21, C23, C27, C30, resistors R8, R17, R19, R21, R24, and R32 respectively.

[0119] The other end of capacitor C9 is connected to the other end of resistor R8, pin 13 of chip U2, and pin 13 of chip U3, respectively.

[0120] The other end of capacitor C12 is connected to the other end of resistor R17, pin 14 of chip U2, and pin 14 of chip U3, respectively.

[0121] The other end of capacitor C16 is connected to the other end of resistor R19, pin 15 of chip U2, and pin 15 of chip U3, respectively.

[0122] The other end of capacitor C21 is connected to the other end of resistor R21, pin 12 of chip U2, and pin 12 of chip U3, respectively.

[0123] The other end of capacitor C23 is connected to the other end of resistor R24, pin 1 of chip U2, and pin 1 of chip U3, respectively.

[0124] The other end of capacitor C27 is connected to the other end of resistor R28, pin 5 of chip U2, and pin 5 of chip U3, respectively.

[0125] The other end of capacitor C30 is connected to the other end of resistor R32, one end of resistor R31, one end of resistor R30, pin 2 of chip U2, and pin 2 of chip U3, respectively.

[0126] The other end of resistor R31 is grounded; one end of resistor R30 is connected to pin 4 of chip U2 and pin 4 of chip U3 respectively.

[0127] Furthermore, all electronic components involved in this utility model adopt existing technologies. For example, chip U1 adopts the C8051F342-G1 type chip, chip U4 adopts the AD5625WARTZ type chip, and chip U7 adopts the ADA4841-1YRZ type chip.

[0128] The working principle of this invention is as follows: The input optical signal enters the optical splitter, where the first and second optical splitters divide it into different optical paths. The split optical signal then enters the adjustable optical attenuation unit. The adjustable optical attenuation unit adjusts the optical attenuation by changing the light transmission loss. The attenuated optical signal then reaches the photodetector. The photodetector converts the optical signal into an electrical signal and generates a corresponding electrical signal output based on the optical power, thereby enabling the detection of optical power.

[0129] The control unit is connected to both the photodetector and the adjustable optical attenuation unit. The control unit receives an electrical signal representing optical power information from the photodetector and compares it to a preset optical power value. If the detected optical power deviates from the preset value, the control unit sends a corresponding control signal to the adjustable optical attenuation unit to adjust its attenuation, causing the optical power to change towards the preset value until it is reached. This achieves precise control and stable output of the optical attenuation.

[0130] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0131] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A program-controlled adjustable optical attenuator, characterized by: The application relates to an optical power attenuation device, which comprises an optical splitter, an adjustable optical attenuation unit, an optical detector and a control unit. The optical splitter is used for splitting input optical signals and comprises a first optical splitter and a second optical splitter. The adjustable optical attenuation unit is used for changing the loss of optical transmission, so as to realize the adjustment of optical attenuation.

2. A programmable optical attenuator as claimed in claim 1, characterized in that: The control unit is connected with the optical detector and the adjustable optical attenuation unit and is used for receiving optical power information transmitted by the optical detector. The first optical splitter is used for a main optical path and comprises a chip U2, a capacitor C1, resistors R2, R3 and R4. The 1-5 pins of the chip U2 are connected with a switch circuit. The 6-8 pins of the chip U2 are grounded. The 9 pin of the chip U2 is connected with one end of the resistor R4, the 10 pin of the chip U2 is connected with one end of the resistor R3, and the 11 pin of the chip U2 is connected with one end of the resistor R2. The 12-15 pins of the chip U2 are connected with a switch circuit.

3. A programmable optical attenuator as claimed in claim 2, characterized in that: The 16 pin of the chip U2 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is grounded. The 16 pin of the chip U2 and the capacitor C1 are connected with a power supply. The second optical splitter is used for a reference optical path and comprises a chip U3, a chip U4, capacitors C2, C3, C4, C7, C8, resistors R5, R6 and R7. The 1, 2, 4 and 6 pins of the chip U3 are connected with a switch circuit. The 3 pin of the chip U3 is connected with the 3 pin of the chip U4. The 6, 7 and 8 pins of the chip U3 are grounded.

4. A programmable optical attenuator as claimed in claim 3, characterized in that: The 9, 10 and 11 pins of the chip U3 are connected with the control unit.

5. A program controlled adjustable optical attenuator as claimed in claim 1, characterized in that: The 12, 13, 14, 15 and 16 pins of the chip U3 are connected with a switch circuit. The 1 pin of the chip U4 is connected with one end of the resistor R6 and the resistor R5. The other end of the resistor R5 is connected with the 4 pin of the chip U4 and one end of the resistor R7. The other end of the resistor R7 is grounded.

6. A programmable optical attenuator as claimed in claim 5, characterized in that: The other end of the resistor R6 is connected with the 1 pin of the chip U12, the capacitors C7 and C8.

7. A programmable optical attenuator as claimed in claim 6, characterized in that: The 5 pin of the chip U4 is connected with one end of the capacitors C3 and C4. The 5 pin of the chip U4, the capacitors C3 and C4 are connected with a power supply. The control unit comprises a chip U1, capacitors C5 and C6. The 32-30 pins of the chip U1 are connected with the 11-9 pins of the chip U3. The 18-14 pins of the chip U1 are connected with an optical output port and an adjustable optical attenuation unit. The 6 pin of the chip U1 is connected with one end of the capacitors C5 and C6. The other end of the capacitors C5 and C6 is grounded. The 3 pin of the chip U1 is grounded. The 6 pin of the chip U1, the capacitors C5 and C6 are connected with a power supply. The optical detector comprises a chip U9, capacitors C32, C33 and C34. The pin 1 of the chip U9 is connected with the pin 2, the pin 3, one end of the capacitor C32 and one end of the capacitor C33 of the chip U9 respectively; The pin 4 of the chip U9 is connected with the pin 5, the other end of the capacitor C32 and the other end of the capacitor C33 of the chip U9 respectively; The pin 1, the pin 2, the pin 3, the capacitor C32 and the capacitor C33 of the chip U9 are connected with the power supply respectively; The pin 4, the pin 5, the capacitor C32 and the other end of the capacitor C33 of the chip U9 are grounded respectively; The pin 10 of the chip U9 is connected with the adjustable optical attenuation unit; the pin 8 of the chip U9 is connected with the pin 24 of the chip U1; the pin 7 of the chip U9 is connected with the pin 23 of the chip U1; The pin 9 of the chip U9 is connected with one end of the capacitor C32; the other end of the capacitor C32 is grounded; The pin 6 of the chip U9 is grounded.

8. A program controlled adjustable optical attenuator according to claim 1, wherein: The adjustable optical attenuation unit comprises the chip U7, the resistor R20, the resistor R23, the resistor R25, the resistor R26 and the capacitor C22; The pin 2 of the chip U7 is connected with one end of the resistor R23 and one end of the resistor R20 respectively; the other end of the resistor R23 is grounded; the other end of the resistor R20 is connected with the pin 6 of the chip U7 and one end of the resistor R26 respectively; the other end of the resistor R26 is connected with the external output interface; The pin 3 of the chip U7 is connected with one end of the resistor R25; the other end of the resistor R25 is connected with the pin 10 of the chip U9; The pin 4 of the chip U7 is grounded; the pin 7 of the chip U7 is connected with one end of the capacitor C22; the other end of the capacitor C22 is grounded; The pin 7 of the chip U7 and the capacitor C22 are connected with the power supply respectively.

9. A programmable optical attenuator as claimed in claim 8, characterized in that: The adjustable optical attenuation unit comprises the chip U10, the chip U11, the chip U12, the chip X1, the capacitor C31, the capacitor C35, the capacitor C36, the capacitor C37, the capacitor C38, the capacitor C39, the capacitor C40, the capacitor C41, the capacitor C42, the capacitor C43, the capacitor C44, the capacitor C45, the capacitor C46, the resistor R33, the resistor R34, the resistor R35, the resistor R36, the resistor R37, the resistor R38, the resistor R39, the resistor R40, the resistor R42, the resistor R43 and the resistor R45; The pin 1 of the chip U12 is connected with the capacitor R6, the capacitor C7 and the capacitor C8 respectively; the pin 2 and the pin 3 of the chip U12 are grounded; the pin 4 of the chip U12 is connected with the capacitor C35, the capacitor C42 and the power supply respectively; the other end of the capacitor C35 and the capacitor C42 is grounded; the pin 5 and the pin 6 of the chip U12 are grounded; The pin 7 of the chip U12 is connected with one end of the resistor R37; the other end of the resistor R37 is connected with the pin 14 of the chip U1; the pin 8 of the chip U12 is connected with one end of the resistor R39; the other end of the resistor R39 is connected with the pin 17 of the chip U1; The pin 9 of the chip U12 is connected with one end of the resistor R40; the other end of the resistor R40 is connected with the pin 16 of the chip U1; the pin 10 of the chip U12 is connected with one end of the resistor R38; the other end of the resistor R38 is connected with the pin 15 of the chip U1; The pin 11 of the chip U12 is connected with one end of the resistor R36, and the other end of the resistor R36 is connected with the pin 18 of the chip U1; The pin 12 of the chip U12 is connected with one end of the resistor R42, and the other end of the resistor R42 is connected with the pin 3 of the chip X1, the pin 4 of the chip X1 is connected with one end of the capacitor C45 and the capacitor C46 respectively, and the other ends of the capacitor C45 and the capacitor C46 are grounded; the pin 4 of the chip X1, the capacitor C45 and the capacitor C46 are connected with the power supply; The pin 1 of the chip U12 is connected with one end of the resistor R43 and the resistor R45 respectively; the other end of the resistor R43 is connected with the power supply, and the other end of the resistor R45 is grounded; the pin 2 of the chip U12 is grounded; The pin 13 of the chip U12 is connected with one end of the capacitor C43 and the capacitor C44 and the power supply respectively; the pin 14 of the chip U13 is connected with the other ends of the capacitor C43 and the capacitor C44 respectively; The pin 15 of the chip U12 is connected with one end of the capacitor C36 and the capacitor C37 respectively, and the pin 16 of the chip U12 is connected with one end of the capacitor C36, the capacitor C37, the pin 6 and the pin 2 of the chip U10 and one end of the resistor R33 respectively; The pin 7 of the chip U10 is connected with one end of the capacitor C31 and the power supply respectively; the other end of the capacitor C31 is grounded; The pin 3 of the chip U10 is connected with one end of the resistor R34, and the other end of the resistor R34 is connected with the other end of the resistor R33, one end of the capacitor C38 and the capacitor C39 and the pin 2 of the chip U11 respectively; the pin 4 of the chip U10 is grounded; The other ends of the capacitor C38 and the capacitor C39 and the pin 3 of the chip U11 are grounded; The pin 1 of the chip U11 is connected with one end of the capacitor C40 and the capacitor C41 and the power supply respectively, and the other ends of the capacitor C40 and the capacitor C41 are grounded.

10. A programmable optical attenuator as claimed in claim 1, wherein: The pin 12 of the chip U13, the capacitor C43 and the capacitor C44 are grounded.

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