High-voltage detection and timing H-bridge driving circuit

Abstract

The utility model discloses a high-voltage detection and timing H-bridge driving circuit, and belongs to the technical field of motor driving. The high-voltage detection and timing H-bridge driving circuit comprises a high-voltage detection unit, a gate driving unit and an H-bridge circuit, the high-voltage detection unit is connected with the four comparators through voltage division output, and the two groups of comparators are respectively used for comparing different voltage sources to realize accurate high-voltage detection. The grid driving unit comprises a first trigger, a second trigger, a first grid driver and a second grid driver, and effective control over the grid of the H-bridge circuit is achieved through cooperative work of the triggers and the grid drivers. And the grid electrode of the H-bridge circuit is connected to the output end of the grid electrode driver and is used for being connected with an external load driver. According to the utility model, the problem that the motor driving circuit in the prior art is difficult to realize the accurate management of the steering of the motor under the condition that long-time accurate timing control is required is effectively solved.

Description

TECHNICAL FIELD

[0001] The utility model embodiment belongs to motor drive technical field, especially relate to a high pressure detection and can fixed time H bridge drive circuit. BACKGROUND

[0002] With the continuous growth of industrial automation and intelligentization demand, the performance requirements of motor drive circuit are also constantly improving. In some special fields, such as military equipment and aerospace, the requirements for motor drive technology are particularly stringent. These scenarios not only require high-performance driving capability, but also must meet specific environmental adaptability, high reliability and safety standards.

[0003] Especially in high-voltage working environment, the circuit may cause device breakdown or system failure risk due to transient overvoltage, voltage fluctuation or abnormal working condition. Traditional H bridge drive circuit relies on external detection module or discrete device to realize voltage monitoring, but this way has the problems of slow response speed, insufficient precision and high circuit complexity, which is difficult to provide real-time and reliable system protection function. UTILITY MODEL CONTENT

[0004] The utility model embodiment provides a high pressure detection and can fixed time H bridge drive circuit, to solve the problem that the motor drive circuit in prior art is difficult to realize accurate management of motor steering under the condition of long-time accurate timing control.

[0005] The technical scheme adopted by the utility model embodiment is a high pressure detection and can fixed time H bridge drive circuit, which comprises a high voltage detection unit, the high voltage detection unit comprising a first comparator, a second comparator, a third comparator, a fourth comparator and a voltage dividing circuit; the voltage dividing circuit comprises a plurality of voltage dividing output ends, the plurality of voltage dividing output ends being connected to the non-inverting input terminal of the first comparator, the inverting input terminal of the second comparator, the non-inverting input terminal of the third comparator and the inverting input terminal of the fourth comparator respectively; the inverting input terminal of the first comparator and the non-inverting input terminal of the second comparator are commonly connected to a first voltage source for outputting a first threshold voltage, and the inverting input terminal of the third comparator and the non-inverting input terminal of the fourth comparator are commonly connected to a second voltage source for outputting a second threshold voltage;

[0006] The gate drive unit comprises a first flip-flop, a second flip-flop, a first gate driver and a second gate driver; the first flip-flop is connected between the common output terminals of the first comparator and the second comparator and the first gate driver, and the second flip-flop is connected between the common output terminals of the third comparator and the fourth comparator and the second gate driver;

[0007] The H-bridge circuit comprises an upper half-bridge and a lower half-bridge, the gates of the upper half-bridge and the lower half-bridge are connected to the output of the first gate driver and the output of the second gate driver respectively, and the output of the upper half-bridge and the output of the lower half-bridge are configured to be connected to the external motor.

[0008] Further, the upper half-bridge comprises a first MOS tube and a second MOS tube, and the lower half-bridge comprises a third MOS tube and a fourth MOS tube.

[0009] The first gate driver comprises two outputs, and the two outputs of the first gate driver are connected to the gates of the first MOS tube and the second MOS tube respectively, the sources of the first MOS tube and the second MOS tube are connected to a voltage source, and the drains of the first MOS tube and the second MOS tube are connected to the load respectively.

[0010] The second gate driver comprises two outputs, and the two outputs of the second gate driver are connected to the gates of the third MOS tube and the fourth MOS tube respectively, the sources of the third MOS tube and the fourth MOS tube are connected to a current detection resistor, and the drains of the third MOS tube and the fourth MOS tube are connected to the load respectively.

[0011] Further, the first MOS tube and the second MOS tube are PMOS, and the third MOS tube and the fourth MOS tube are NMOS.

[0012] Further, the voltage dividing circuit comprises a DC power supply, a first resistor, a second resistor, a third resistor and a fourth resistor, and the first resistor, the second resistor, the third resistor and the fourth resistor are connected in series between the DC power supply and the ground.

[0013] The DC power supply is connected to the positive input of the first comparator after being divided by the first resistor, connected to the inverting input of the second comparator after being divided by the second resistor, connected to the positive input of the third comparator after being divided by the third resistor, and connected to the inverting input of the fourth comparator after being divided by the fourth resistor.

[0014] Further, the high-voltage detection and timing H-bridge driving circuit further comprises a clock, the clock comprises a clock output port, the first flip-flop comprises a first clock input, and the second flip-flop comprises a second clock input; the clock output port is connected to the first clock input of the first flip-flop and the second clock input of the second flip-flop respectively.

[0015] Further, the high-voltage detection and timing H-bridge driving circuit further comprises a counter, the receiving end of the counter is connected to the clock output port, and the output end is connected to the first clock input of the first flip-flop and the second clock input of the second flip-flop respectively.

[0016] Further, the high-voltage detection and timing H-bridge driving circuit further comprises an overcurrent detection unit, the overcurrent detection unit is connected with a current detection resistor, and output ends of the overcurrent detection unit are connected with the first gate driver and a protection circuit input end of the second gate driver.

[0017] Further, the first flip-flop and the second flip-flop are D flip-flops.

[0018] The utility model discloses beneficial effect is:

[0019] The utility model discloses beneficial effect is: BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 It is the circuit structure diagram provided by the utility model embodiment. DETAILED DESCRIPTION

[0021] The utility model will be explained in detail below in combination with the drawings and specific embodiment, but this should not be understood as the range of the above-mentioned theme of the utility model is limited to the following examples, and it should be understood that these examples are only used for explaining the utility model and are not used for limiting the range of the utility model.

[0022] The utility model embodiment provides a kind of high-voltage detection and timing H-bridge driving circuit, as shown in figure Figure 1 The high-voltage detection and timing H-bridge driving circuit includes high-voltage detection unit, gate drive unit and H-bridge circuit.

[0023] Specifically, the high-voltage detection unit includes a first comparator U1, a second comparator U2, a third comparator U3, a fourth comparator U4 and a voltage dividing circuit. Among them, the voltage dividing circuit includes a plurality of voltage dividing output ends, and the plurality of voltage dividing output ends are respectively connected with the non-inverting input end of the first comparator U1, the inverting input end of the second comparator U2, the non-inverting input end of the third comparator U3 and the inverting input end of the fourth comparator U4. In addition, the inverting input end of the first comparator U1 and the non-inverting input end of the second comparator U2 are commonly connected with a first voltage source Vref1 for providing a first threshold voltage. The inverting input end of the third comparator U3 and the non-inverting input end of the fourth comparator U4 are commonly connected with a second voltage source Vref2 for providing a second threshold voltage.

[0024] The gate drive unit includes a first flip-flop Q1, a second flip-flop Q2, a first gate driver Q5 and a second gate driver Q7. Among them, the first flip-flop Q1 is connected between the common output end of the first comparator U1 and the second comparator U2 and the first gate driver Q5; the second flip-flop Q2 is connected between the common output end of the third comparator U3 and the fourth comparator U4 and the second gate driver Q7. Specifically, the input end of the first flip-flop Q1 is connected with the common output end of the first comparator U1 and the second comparator U2, the output end of the first flip-flop Q1 is connected with the input end of the first gate driver Q5, the input end of the second flip-flop Q2 is connected with the common output end of the third comparator U3 and the fourth comparator U4, and the output end of the second flip-flop Q2 is connected with the input end of the second gate driver Q7.

[0025] The H-bridge circuit includes an upper half-bridge and a lower half-bridge, wherein the gate of the upper half-bridge is connected with the output end of the first gate driver Q5, the gate of the lower half-bridge is connected with the output end of the second gate driver Q7, and the output end of the upper half-bridge and the output end of the lower half-bridge are configured to be connected with an external motor.

[0026] The high-voltage detection unit of the utility model can monitor the change of high-voltage signal in real time through the combination of voltage dividing circuit and four comparators. The voltage dividing circuit reduces the high-voltage signal by a certain proportion and inputs it into the comparator for comparison with the preset threshold voltage. The comparator monitors whether the high-voltage signal exceeds or is lower than the preset overvoltage threshold value. If the high-voltage signal exceeds the threshold value, the comparator will output an overvoltage fault signal to trigger the control logic to cut off the output of the H-bridge or turn off the driving signal, thereby preventing the device from being damaged due to high voltage. In the embodiment, independent high and low side protection threshold values Vref1 and Vref2 are provided to realize asymmetric voltage monitoring.

[0027] The gate drive unit latches the output state of the comparator through a flip-flop, the flip-flop can latch and process the signal output by the comparator, ensures that the gate drive receives stable and reliable driving signals, thereby accurately controlling the conduction and cutoff of the upper and lower half-bridge arms in the H-bridge circuit, and improving the stability and reliability of the driving circuit. Therefore, the forward and reverse rotation of the motor in the H-bridge circuit can be accurately managed.

[0028] In the embodiment, the upper half-bridge arm includes a first MOS tube Q8 and a second MOS tube Q9, and the lower half-bridge arm includes a third MOS tube Q10 and a fourth MOS tube Q11.

[0029] The first gate drive Q5 includes two outputs, the two outputs of the first gate drive Q5 are connected to the gates of the first MOS tube Q8 and the second MOS tube Q9 respectively, the sources of the first MOS tube Q8 and the second MOS tube are connected to a voltage source, and the drain terminals of the first MOS tube Q8 and the second MOS tube Q9 are connected to both ends of the motor.

[0030] The second gate drive Q7 includes two outputs, the two outputs of the second gate drive Q7 are connected to the gates of the third MOS tube Q10 and the fourth MOS tube Q11 respectively, the sources of the third MOS tube Q10 and the fourth MOS tube Q11 are connected to a current detection resistor RSENSE, and the drain terminals of the third MOS tube Q10 and the fourth MOS tube Q11 are connected to both ends of the motor.

[0031] The H-bridge circuit includes an upper half-bridge arm composed of the first MOS tube Q8 and the second MOS tube Q9, and a lower half-bridge arm composed of the third MOS tube Q10 and the fourth MOS tube Q11, which constitutes a classical structure. The first gate drive Q5 and the second gate drive Q7 control the conduction and cutoff of the MOS tubes in the upper and lower half-bridge arms respectively. When the first gate drive Q5 drives the first MOS tube Q8 to conduct, and at the same time the second gate drive Q7 drives the fourth MOS tube Q11 to conduct, and the second MOS tube Q9 and the third MOS tube Q10 are cut off, the motor realizes forward rotation. Conversely, when the second MOS tube Q9 and the third MOS tube Q10 are turned on, and the first MOS tube Q8 and the fourth MOS tube Q11 are cut off, the motor realizes reverse rotation.

[0032] The current detection resistor RSENSE is connected in series at the source of the lower half-bridge arm, which can monitor the motor loop current in real time, and provide direct feedback for overcurrent protection, dynamic current limiting and efficiency optimization.

[0033] In the embodiment, the first MOS Q8 and the second MOS Q9 are PMOS, the third MOS Q10 and the fourth MOS Q11 are NMOS. The upper half bridge arm adopts PMOS as a switch, because the gate voltage only needs to be lower than the source voltage to turn on, without using a boost circuit. The NMOS needs the gate voltage to be higher than the source voltage to turn on. This design can significantly simplify the drive circuit and improve the overall efficiency.

[0034] The voltage dividing circuit comprises a direct current power supply, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are connected in series between the direct current power supply and the ground, and sequentially divide the voltage of the direct current power supply.

[0035] The direct current power supply is connected to the positive input terminal of the first comparator U1 after being divided by the first resistor R1, is connected to the inverting input terminal of the second comparator U2 after being divided by the second resistor R2, is connected to the positive input terminal of the third comparator U3 after being divided by the third resistor R3, and is connected to the inverting input terminal of the fourth comparator U4 after being divided by the fourth resistor R4.

[0036] In the embodiment, a fifth resistor R5 is further included, the input terminal of the fifth resistor R5 is connected to the output terminal of the fourth resistor R4, the output terminal of the fifth resistor R5 is grounded, and the direct current power supply is further divided by the fifth resistor R5.

[0037] A clock Q4 is further included, and the clock Q4 has a clock output port. The first flip-flop Q1 includes a first clock input terminal, and the second flip-flop Q2 includes a second clock input terminal. The output port of the clock module Q4 is connected to the first clock input terminal of the first flip-flop Q1 and the second clock input terminal of the second flip-flop Q2 respectively. The first flip-flop Q1 and the second flip-flop Q2 share the same clock signal and realize completely synchronous operation.

[0038] The design does not need additional clock frequency division or phase adjustment circuit, thereby simplifying the circuit structure. If the first flip-flop Q1 and the second flip-flop Q2 are driven by different clocks, the clock deviation may cause a race condition problem, and the shared clock design effectively avoids this risk. In addition, the first flip-flop Q1 and the second flip-flop Q2 are triggered synchronously at the clock edge, ensuring the consistency of the H-bridge upper and lower tube switching and avoiding the occurrence of short circuit.

[0039] In addition, a counter Q3 is provided, which has a receiving end and an output end. The receiving end of the counter Q3 is connected to the output port of the clock Q4, and the output end of the counter Q3 is connected to the first clock input end of the first flip-flop Q1 and the second clock input end of the second flip-flop Q2, respectively. The counter Q3 is responsible for receiving the clock signal and counting according to the clock pulse, so that through the counter Q3, the timing of triggering the first flip-flop Q1 and the second flip-flop Q2 is accurately controlled.

[0040] In the embodiment, an overcurrent detection unit Q6 is also provided. The overcurrent detection unit Q6 is externally connected to a current detection resistor RSENSE, and the output end of the overcurrent detection unit Q6 is connected to the protection circuit input end of the first gate driver Q5 and the second gate driver Q7, respectively. The overcurrent detection unit Q6 monitors the output current of the H-bridge circuit through the external resistor RSENSE. When the detected current exceeds the preset threshold, the overcurrent detection unit Q6 sends a signal to the protection circuit input end of the first gate driver Q5 and the second gate driver Q7, thereby triggering the protection mechanism. Through the real-time monitoring function of the external resistor RSENSE, it can be ensured that the H-bridge circuit always operates within a safe range. The introduction of the overcurrent detection unit Q6 significantly improves the reliability of the H-bridge circuit and effectively reduces the risk of failure caused by overcurrent.

[0041] The first flip-flop Q1 and the second flip-flop Q2 are D flip-flops. The D flip-flop can update the output state at the edge of the clock signal (such as the rising edge or the falling edge), thereby ensuring the synchronization of the upper and lower bridge arm switching signals in the H-bridge circuit and avoiding the occurrence of short circuit. At the same time, the D flip-flop has good compatibility and is easy to integrate with other digital circuit elements, which is convenient for realizing more complex control logic. In other embodiments, JK flip-flops, RS flip-flops, etc. can also be used according to needs.

Claims

1. A high-voltage detection and timed H-bridge drive circuit, characterized in that, include: A high-voltage detection unit includes a first comparator, a second comparator, a third comparator, a fourth comparator, and a voltage divider circuit. The voltage divider circuit includes multiple voltage divider output terminals, which are respectively connected to the non-inverting input terminal of the first comparator, the inverting input terminal of the second comparator, the non-inverting input terminal of the third comparator, and the inverting input terminal of the fourth comparator. The inverting input terminal of the first comparator and the non-inverting input terminal of the second comparator are jointly connected to a first voltage source for outputting a first threshold voltage, and the inverting input terminal of the third comparator and the non-inverting input terminal of the fourth comparator are jointly connected to a second voltage source for outputting a second threshold voltage. A gate driving unit, the gate driving unit including a first flip-flop, a second flip-flop, a first gate driver and a second gate driver; the first flip-flop is connected between the common output terminal of the first comparator and the second comparator and the first gate driver, and the second flip-flop is connected between the common output terminal of the third comparator and the fourth comparator and the second gate driver; The H-bridge circuit includes an upper half-arm bridge and a lower half-arm bridge. The gates of the upper half-arm bridge and the lower half-arm bridge are respectively connected to the output terminals of the first gate driver and the second gate driver. The output terminals of the upper half-arm bridge and the lower half-arm bridge are configured to connect to an external motor.

2. The high-voltage detection and timed H-bridge drive circuit according to claim 1, characterized in that, The upper half-arm bridge includes a first MOSFET and a second MOSFET, and the lower half-arm bridge includes a third MOSFET and a fourth MOSFET. The first gate driver has two outputs, which are respectively connected to the gate of the first MOSFET and the gate of the second MOSFET. The source of the first MOSFET and the source of the second MOSFET are connected to a voltage source, and the drain of the first MOSFET and the drain of the second MOSFET are respectively connected to a load. The second gate driver includes two outputs, which are respectively connected to the gate of the third MOS transistor and the gate of the fourth MOS transistor. The source of the third MOS transistor and the source of the fourth MOS transistor are connected to current sensing resistors, and the drain of the third MOS transistor and the drain of the fourth MOS transistor are respectively connected to loads.

3. The high-voltage detection and timed H-bridge drive circuit according to claim 2, characterized in that, The first and second MOS transistors are PMOS transistors, and the third and fourth MOS transistors are NMOS transistors.

4. The high-voltage detection and timed H-bridge drive circuit according to claim 1, characterized in that, The voltage divider circuit includes a DC power supply, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein the first resistor, the second resistor, the third resistor, and the fourth resistor are connected in series between the DC power supply and ground. The DC power supply is connected to the positive input terminal of the first comparator after being divided by the first resistor; it is connected to the inverting input terminal of the second comparator after being divided by the second resistor; it is connected to the positive input terminal of the third comparator after being divided by the third resistor; and it is connected to the inverting input terminal of the fourth comparator after being divided by the fourth resistor.

5. The high-voltage detection and timed H-bridge drive circuit according to claim 1, characterized in that, It also includes a clock; the clock has a clock output port, the first flip-flop has a first clock input terminal, and the second flip-flop has a second clock input terminal; the clock output port is respectively connected to the first clock input terminal of the first flip-flop and the second clock input terminal of the second flip-flop.

6. The high-voltage detection and timed H-bridge drive circuit according to claim 5, characterized in that, It also includes a counter, which has a receiving end and an output end. The receiving end is connected to the clock output port, and the output end is connected to the first clock input end of the first flip-flop and the second clock input end of the second flip-flop, respectively.

7. The high-voltage detection and timed H-bridge drive circuit according to claim 2, characterized in that, It also includes an overcurrent detection unit, which is externally connected to the current detection resistor. The output terminal of the overcurrent detection unit is connected to the protection circuit input terminal of the first gate driver and the second gate driver, respectively.

8. The high-voltage detection and timed H-bridge drive circuit according to claim 1, characterized in that, The first flip-flop and the second flip-flop are D flip-flops.

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