Simple latch circuit based on NAND gate

Abstract

The utility model discloses a simple latch circuit based on NAND gates. The simple latch circuit comprises resistors R1 and R2, a capacitor C1, a diode D1 and two NAND gate chips U1, one end of the resistor R1 and one end of the resistor R2 are loaded with 3.3 V voltage, the other end of the resistor R1 is connected with an excitation input 1A pin of the NOT gate chip U1 and is connected with an anode of the diode D1, and a cathode of the diode D1 is connected with an excitation input signal end; one end of the resistor R2 is connected with an excitation input 2A pin of the NOT gate chip U1 and is connected with one end of the capacitor C1, and the other end of the capacitor C1 is grounded; an excitation output 1Y pin of the NOT gate chip U1 outputs first response output, and an excitation output 2Y pin of the NOT gate chip U1 outputs second response output; according to the utility model, response output is triggered through one excitation input, the effect of two opposite latch outputs is realized, and the latch circuit is suitable for more latch application scenes.

Description

Technical Field

[0001] This utility model relates to the technical field of latching circuits, specifically a simple latching circuit based on NAND gates. Background Technology

[0002] In the field of latches, latching circuits are required for maintaining the output level of signals, such as for implementing step-by-step control. Existing latching circuits use two inputs to correspond to two outputs, which results in poor synchronization between the two outputs. Furthermore, existing latching circuits require complex hardware designs to output two highly synchronized and complementary levels, leading to high costs. Therefore, designing a simple latching circuit with high output synchronization has become an urgent problem to be solved. Utility Model Content

[0003] To address the shortcomings of existing technologies, this invention provides a simple latching circuit based on NAND gates.

[0004] To solve the above-mentioned technical problems, this utility model provides the following technical solution:

[0005] This utility model discloses a simple latching circuit based on NAND gates, including resistors R1 and R2, capacitor C1, diode D1, and a 2-channel NAND gate chip U1.

[0006] One end of resistor R1 and one end of resistor R2 are both loaded with a voltage of 3.3V. The other end of resistor R1 is connected to the excitation input pin 1A of the NOT gate chip U1, and is also connected to the anode of diode D1. The cathode of diode D1 is connected to the excitation input signal terminal.

[0007] One end of the resistor R2 is connected to the excitation input pin 2A of the NOT gate chip U1, and is also connected to one end of the capacitor C1, while the other end of the capacitor C1 is grounded.

[0008] The excitation output pin 1Y of the NOT gate chip U1 outputs the first response output, and the excitation output pin 2Y of the NOT gate chip U1 outputs the second response output.

[0009] The excitation output pin 2Y is connected to the excitation input pin 1B of the NOT gate chip U1, and the excitation output pin 1Y is connected to the excitation input pin 2B of the NOT gate chip U1.

[0010] As a preferred embodiment of this invention, diode D1 is an isolation diode used to isolate the high level of the excitation input signal, and only the 0 level input is valid.

[0011] In a preferred embodiment of this invention, the resistance values ​​of resistors R1 and R2 are 3.3kΩ.

[0012] In a preferred embodiment of this invention, the capacitance value of capacitor C1 is 1uF.

[0013] As a preferred embodiment of this invention, the output levels of the first response output and the second response output are complementary.

[0014] The beneficial effects of this utility model are:

[0015] This simplified latching circuit based on NAND gates uses NAND gates to construct a simple latching circuit. A single stimulus input triggers the response output, achieving the effect of two opposite latching outputs, thus adapting to a wider range of latching applications. This invention requires only one stimulus input to obtain the effect of two complementary latching outputs, with high synchronization. If n simplified latching circuits of this invention are triggered by a single stimulus input, n sets of complementary latching effects can be achieved with one stimulus input. It is implemented in hardware; after one stimulus input, n sets of complementary triggers respond immediately. Compared to methods that use multiple stimulus inputs to serially control different latching devices or to control different latching devices in parallel, this simplifies hardware design and saves latching time. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation thereof. In the drawings:

[0017] Figure 1 This is a schematic diagram of a simple latching circuit based on NAND gates according to this utility model. Detailed Implementation

[0018] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0019] Example: Figure 1 As shown, this utility model discloses a simple latching circuit based on NAND gates, including resistors R1 and R2, capacitor C1, diode D1, and a 2-channel NAND gate chip U1.

[0020] Among them, the 2-channel NAND gate chip U1, model reference: SN74LVC2G132DCUR, contains 2 sets of NAND gate resources. In the first set, pins 1A and 1B are used as excitation inputs and pin 1Y is used as the response output; in the second set, pins 2A and 2B are used as excitation inputs and pin 1Y is used as the response output. It is powered by 3.3V.

[0021] Diode D1, model reference: SDM20U30-7, isolates the high-level input of the excitation input, ensuring only a 0-level input is active and guaranteeing a stable high-level default state for pin 1A of U1. Resistors R1 and R2, reference value 3.3kΩ, provide a stable high-level input to pins 1A and 2A of U1 as the default state.

[0022] Capacitor C1, with a reference capacitance of 1uF, serves to gradually raise the voltage level of pin 2A of U1 from low level 0 to high level 1 during power-on. This causes the high level 1 of pin 2A to lag behind the high level 1 of pin 1A. This can be summarized as the voltage level changes of pins 1A and 2A of U1 from the moment of power-on to the stable power-on process, changing from the initial 1 and 0 to the stable 1 and 1, thus ensuring the correctness of the initial state timing of the latch circuit.

[0023] The connection relationship of the latch circuit is as follows: one end of resistor R1 and one end of resistor R2 are both loaded with 3.3V voltage. The other end of resistor R1 is connected to the excitation input 1A pin of NOT gate chip U1, and is also connected to the anode of diode D1. The cathode of diode D1 is connected to the excitation input signal terminal.

[0024] One end of resistor R2 is connected to the excitation input pin 2A of NOT gate chip U1, and also to one end of capacitor C1, with the other end of capacitor C1 grounded; the excitation output pin 1Y of NOT gate chip U1 outputs a first response output, and the excitation output pin 2Y of NOT gate chip U1 outputs a second response output; the excitation output pin 2Y is connected to the excitation input pin 1B of NOT gate chip U1, and the excitation output pin 1Y is connected to the excitation input pin 2B of NOT gate chip U1.

[0025] This invention requires only one stimulus input to achieve the effect of two complementary latch outputs, with high synchronization. If n simplified latch circuits of this invention are triggered by a single stimulus input, n sets of complementary latching effects can be achieved with just one stimulus input. It is implemented in hardware; after one stimulus input, the n sets of complementary triggers respond immediately. Compared to methods that use multiple stimulus inputs to serially control different latching devices or to control different latching devices in parallel, this simplifies hardware design and saves latching time.

[0026] In practical applications, a low-level 0 stimulus input triggers either a high-level 1 or a low-level 0 output (with complementary outputs, selectable according to the actual application). The high-level 1 or low-level 0 output will not change with the stimulus input and will remain unchanged thereafter. (For example, after the stimulus input is 0, if the stimulus input is changed to 1, the two complementary level outputs will remain unchanged.)

[0027] The working principle of the latch circuit of this utility model is described in detail.

[0028] Step 1: At the instant of power-on at 3.3V, the first group of excitation input pins 1A of U1 is at a high level (1). Due to the charging effect of capacitor C1, the second group of excitation input pins 2A of U1 is at a low level (0). According to the properties of NAND gates, regardless of whether the second group of excitation input pins 2B of U1 is at a high level (1) or a low level (0), the second group of response output pins 2Y is at a high level (1). Since the second group of response output pins 2Y of U1 is at a high level (1), the first group of excitation input pins 1B is also at a high level (1). Furthermore, since the level of the first group of excitation input pins 1A of U1 is 1, the first group of response output pins 1Y is at a low level (0).

[0029] Step 2: After the 3.3V power-on stabilizes, the first group of excitation input pins 1A and 2A of U1 are both at a high level (1). As we know from Step 1, the first group of response output pins 1Y and 2B of U1 are at a low level (0). Although the level of the second group of excitation input pins 2A changes from low to high, the level of the second group of response output pins 2Y remains high (1), and the output levels of 1Y and 2Y are maintained. Based on the above analysis, Steps 1 and 2 are completed from the moment the 3.3V power-on stabilizes. The first group of excitation input pins 1A and 2A of U1 stabilize at a high level (1), and the output levels of responses 1Y and 2Y remain low (0) and high (1) respectively, preparing for the arrival of excitation input 1.

[0030] Step 3: When excitation input 1 arrives, i.e., excitation input pin 1 is at a low level (0), which is equivalent to being pulled to GND, the state of the first group of excitation input pins 1A of U1 changes from 1 to 0. Since the first group of excitation input pins 1B is at a high level (1), the first group of response output pins 1Y is at 1. The state of the second group of excitation input pins 2B is at a high level (1). Since the second group of excitation input pins 2A outputs a high level (1), the second group of response output pins 2Y outputs a low level (0), and the state of the first group of excitation input pins 1B is also at a low level (0). Through step 3, excitation input 1 is given a low level (0), and the output levels of responses 1Y and 2Y are flipped from the original low level (0) and high level (1) to high level (1) and low level (0), respectively.

[0031] Step 4: When the excitation input 1 changes from low level 0 to high level 1 again, the state of the first group of excitation input pins 1A of U1 is high level 1, and the output of the second group of response pins 2Y is low level 0. The state of the first group of excitation input pins 1B is also low level 0. Then the state of the first group of response pins 1Y remains high level 1. The state of the second group of excitation input pins 2B is high level 1, and the state of the second group of excitation input pins 2A is high level 1. The output of the second group of response pins 2Y is low level 0; the state of 2Y is also maintained.

[0032] In step 4, in response to the output level states of 1Y and 2Y, the high level 1 and low level 0 of step 3 are maintained respectively.

[0033] Similarly, in each subsequent step, regardless of how the level state of the excitation input 1 changes, the output level states of responses 1Y and 2Y will always maintain the high level 1 and low level 0 of step 3, respectively; 1Y and 2Y correspond to response output 1 and response output 2, respectively, thereby achieving a level latching effect where the levels of response output 1 and response output 2 are complementary, adapting to more latching application scenarios.

[0034] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A simple latching circuit based on NAND gates, characterized in that, Includes resistors R1 and R2, capacitor C1, diode D1, and a 2-way NAND gate chip U1; One end of resistor R1 and one end of resistor R2 are both loaded with a voltage of 3.3V. The other end of resistor R1 is connected to the excitation input pin 1A of the NOT gate chip U1, and is also connected to the anode of diode D1. The cathode of diode D1 is connected to the excitation input signal terminal. One end of the resistor R2 is connected to the excitation input pin 2A of the NOT gate chip U1, and is also connected to one end of the capacitor C1, while the other end of the capacitor C1 is grounded. The excitation output pin 1Y of the NOT gate chip U1 outputs the first response output, and the excitation output pin 2Y of the NOT gate chip U1 outputs the second response output. The excitation output pin 2Y is connected to the excitation input pin 1B of the NOT gate chip U1, and the excitation output pin 1Y is connected to the excitation input pin 2B of the NOT gate chip U1.

2. The simplified latch circuit based on NAND gates according to claim 1, characterized in that, The diode D1 is an isolation diode used to isolate the high level of the excitation input signal; only a 0 level input is valid.

3. A simple latching circuit based on NAND gates according to claim 1, characterized in that, The resistance values ​​of resistors R1 and R2 are 3.3kΩ.

4. A simple latching circuit based on NAND gates according to claim 1, characterized in that, The capacitance of capacitor C1 is 1uF.

5. A simplified latch circuit based on NAND gates according to claim 1, characterized in that, The output levels of the first response output and the second response output are complementary.

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