TBC solar cell and cell assembly

Abstract

The utility model relates to a TBC solar cell and a cell assembly. The TBC solar cell comprises a silicon substrate. The first region and the second region are alternately arranged on the back surface of the silicon substrate; the first metal electrode and the second metal electrode are respectively positioned in the first region and the second region; the first metal electrode and the second metal electrode respectively comprise a plurality of first fine grids and second fine grids which extend along the first direction and are arranged along the second direction; the ratio X of two times of the distance between the adjacent first fine grid and second fine grid and Y of the width of the first area / second area along the second direction to two times of the distance between the adjacent first fine grid and second fine grid satisfies 0.00007 X + 0.0767 < Y <-0.00023 X + 0.9267. According to the solar cell, the partial region, which is not in contact with the metal electrode, of the back surface is thinned, and meanwhile, the proportion of the width of the first region / the second region to the distance between the first fine grid and the second fine grid is limited, so that the light absorption problem caused by the too thick poly layer can be reduced, and the excellent electrical performance of the cell can be ensured.

Description

Technical Field

[0001] This utility model relates to the field of solar cell technology, specifically to a TBC solar cell and battery module with good electrical performance. Background Technology

[0002] TBC (Tunnel Back Contact) solar cells are a type of solar cell formed by stacking IBC (Interdigitated Back Contact) cells and TOPcon (Tunneling Oxide Passivated Contact) cells. As a novel photovoltaic cell technology, it boasts numerous advantages due to its unique structural design, which places the positive and negative grid lines on the back of the cell and draws current through a tunnel structure. Its absence of grid lines on the front not only makes it aesthetically pleasing but also avoids the shading of light by the grid lines. Compared to other traditional photovoltaic cells, it has greater potential for efficiency improvement and is highly competitive in the future solar energy market.

[0003] However, current mainstream TBC solar cell fabrication technologies, in pursuit of high efficiency, generally employ methods that construct tunneling oxide layers and relatively thick poly layers in both the P- and N-regions. While the thicker poly layer contributes to improved cell performance to some extent, it also introduces problems such as excessively high optical parasitic absorption and current loss. Although existing technologies have provided processes for partially thinning the poly layer, the size of the thinning area on the solar panel plane, the grid line arrangement, and other structural elements still significantly impact cell performance. Utility Model Content

[0004] To address the aforementioned technical problems, this utility model provides a TBC solar cell and battery module.

[0005] The present invention adopts the following technical solution:

[0006] A TBC solar cell, comprising:

[0007] A silicon substrate having a front and a back side that are positioned opposite to each other;

[0008] A front passivation layer is disposed on the front side of the silicon substrate;

[0009] A first region and a second region are alternately disposed on the back side of the silicon substrate;

[0010] The first region includes, in sequence along the direction away from the silicon substrate, a tunneling oxide layer, a first conductive passivation layer, a back passivation layer, and a first metal electrode, wherein the first metal electrode is in ohmic contact with the first conductive passivation layer;

[0011] The second region includes, in sequence along the direction away from the silicon substrate, a tunneling oxide layer, a second conductive passivation layer, a back passivation layer, and a second metal electrode, wherein the second metal electrode is in ohmic contact with the second conductive passivation layer;

[0012] The first conductive passivation layer and the second conductive passivation layer have opposite conductive media;

[0013] An isolation region located between adjacent first and second regions, the isolation region being recessed inward and closer to the silicon substrate than the first and second regions;

[0014] The first metal electrode includes a plurality of first fine grids extending along a first direction and arranged along a second direction;

[0015] The second metal electrode includes a plurality of second fine grids extending along a first direction and arranged along a second direction;

[0016] The TBC solar cell satisfies:

[0017] 0.00007X+0.0767<Y<-0.00023X+0.9267;

[0018] Where X is the distance between two adjacent first fine gates or two adjacent second fine gates, in μm;

[0019] Y is the ratio of the width of the first / second region along the second direction to the distance between two adjacent first grids or two adjacent second grids.

[0020] Furthermore, the distance X between two adjacent first fine gates or two adjacent second fine gates and the ratio Y of the width of the first region / second region along the second direction to the distance between two adjacent first fine gates or two adjacent second fine gates satisfy the following condition: 0.00001X+0.2433<Y<-0.00016X+0.7600.

[0021] Furthermore, the distance X between two adjacent first fine gates or two adjacent second fine gates is 700μm~1500μm, the ratio Y of the width of the first region / second region along the second direction to the distance between two adjacent first fine gates or two adjacent second fine gates is 15.0%~65.0%, and the width Z of the first region / second region along the second direction is 150~830μm.

[0022] Furthermore, the width of the first / second region along the second direction is 28.3% to 60.0% of the distance between two adjacent first or second fine gates, and the width Z of the first / second region along the second direction is 300 to 780 μm.

[0023] Furthermore, the width difference between the first region and the second region along the second direction is 50μm to 450μm; the width of the isolation region between adjacent first regions and second regions along the second direction is 50μm to 300μm.

[0024] Furthermore, the first conductive passivation layer and / or the second conductive passivation layer are doped polycrystalline silicon layers or doped stacked polycrystalline silicon layers containing silicon oxide layers; the stacked polycrystalline silicon layers containing silicon oxide layers can be a polycrystalline silicon layer + silicon oxide layer + polycrystalline silicon layer structure.

[0025] On the other hand, the present invention also provides a battery assembly including the above-mentioned TBC solar cell.

[0026] Furthermore, the first metal electrode also includes a plurality of first main gates spaced apart along the second direction and arranged along the first direction, and the intersection of the first fine gate and the first main gate is connected along the second direction by a first interconnecting strip;

[0027] The second metal electrode further includes a plurality of second main gates spaced apart along the second direction and arranged along the first direction, wherein the intersection of the second fine gate and the second main gate is connected along the second direction by a second interconnecting strip.

[0028] The TBC solar cell of this invention removes the poly layer by thinning the area on the back side that is not in contact with the metal electrode, while limiting the ratio of the width of the first / second area in contact with the metal electrode to the distance between the first and second grids. This not only improves the light transmittance of the solar cell and reduces the light absorption problem caused by the excessive thickness of the poly layer, but also ensures that the cell has excellent electrical performance. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the TBC solar cell structure of this utility model;

[0031] Figure 2 This is a partial structural diagram of the back of the TBC solar cell of this utility model (without interconnecting strips).

[0032] Figure 3 This is a partial structural diagram of the back of the battery module of this utility model (connecting interconnect strips);

[0033] In the figure: 1-Silicon substrate, 2-Front-side passivation layer, 3-First region, 4-Second region, 5-First metal electrode, 6-Second metal electrode, 7-Isolation region, 8-First fine gate, 9-Second fine gate, 10-First main gate, 11-First interconnect strip, 12-Second main gate, 13-Second interconnect strip, 14-Tunneling oxide layer, 15-First conductive passivation layer, 16-Back passivation layer, 17-Second conductive passivation layer. Detailed Implementation

[0034] The technical solutions of this utility model will be clearly and completely described below with reference to the embodiments thereof. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0035] A type of TBC solar cell, such as Figure 1-2 As shown, it includes:

[0036] Silicon substrate 1 has a front side and a back side that are positioned opposite to each other;

[0037] A front passivation layer 2 is disposed on the front side of the silicon substrate 1;

[0038] A first region 3 and a second region 4 are alternately disposed on the back side of the silicon substrate 1;

[0039] The first region 4 includes, in sequence along the direction away from the silicon substrate 1, a tunneling oxide layer 14, a first conductive passivation layer 15, a back passivation layer 16, and a first metal electrode 5;

[0040] The second region 4 includes, in sequence along the direction away from the silicon substrate, a tunneling oxide layer 14, a second conductive passivation layer 17, a back passivation layer 16, and a second metal electrode 6;

[0041] The first conductive passivation layer 15 and the second conductive passivation layer 17 have opposite conductive media.

[0042] An isolation region 7 is located between adjacent first region 3 and second region 4, and the isolation region 7 is recessed inward and closer to the silicon substrate 1 than the first region 3 and second region 4;

[0043] The first metal electrode 5 includes a plurality of first fine grids 8 extending along a first direction and arranged along a second direction;

[0044] The second metal electrode 6 includes a plurality of second fine grids 9 extending along a first direction and arranged along a second direction;

[0045] The TBC solar cell satisfies:

[0046] 0.00007X+0.0767<Y<-0.00023X+0.9267;

[0047] Where X is the distance between two adjacent first fine gates or two adjacent second fine gates, in μm;

[0048] Y is the ratio of the width of the first / second region along the second direction to the distance between two adjacent first grids or two adjacent second grids.

[0049] This invention relates to a TBC solar cell. By thinning and removing the poly layer in the isolation area on the back side that is not in contact with the metal electrode, and by limiting the ratio of the width of the first / second region in contact with the metal electrode to the distance between the first and second fine grids, the light transmittance of the solar cell can be improved, reducing light absorption problems caused by excessive poly layer thickness. This also ensures excellent electrical performance and improves the cell's Jsc (Joint Selective Capacity). Thinning and removing the poly layer in a portion of the back side can improve the cell's Voc (Volume of Capacity), but to form a good PN junction, the first and second regions cannot be too narrow, otherwise it will reduce electrical performance such as FF (Fast Forward). Excessively narrowing the width of the first and second regions can also make the fine grid area easier to misalign, making the cell more prone to leakage and increasing the defect rate in mass production. This invention, by limiting the width of the first / second region, can optimize cell performance while ensuring a high yield rate.

[0050] In this invention, the first region 2, the isolation region 7, and the second region 4 are arranged sequentially along the second direction. The width of the first region 2 / second region 4 along the second direction refers to... Figure 2 Z represents the width.

[0051] Specifically, in some embodiments of this utility model, the distance X between adjacent first fine grids 8 or two adjacent second fine grids 9 and the ratio Y (Y=Z / X) of the width of the first region 2 / second region 4 along the second direction to the distance between two adjacent first fine grids 8 or two adjacent second fine grids 9 satisfy the following: 0.00001X+0.2433<Y<-0.00016X+0.7600.

[0052] Specifically, in some embodiments of this utility model, the distance X between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 700μm~1500μm, the ratio Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 15.0%~65.0%, and the width Z of the first region 3 / second region 4 along the second direction is 150~830μm. Preferably, the ratio Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 28.3%~60.0%, and the width of the first region 3 / second region 4 along the second direction is 300~780μm.

[0053] Preferably, the distance X between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 1000μm, 1200μm, or 1500μm.

[0054] When the distance X between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 1000 μm, the ratio Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 15.0% to 65.0%; the ratio Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 15.0%, 20.0%, 25.0%, 30.0%, 35.0%, 40.0%, 45.0%, 50.0%, 55.0%, 60.0%, 65.0%, or any combination thereof; preferably, the ratio Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 30.0% to 60.0%.

[0055] When the distance X between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 1200 μm, the proportion Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 20% to 61.7%; specifically, the proportion Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 20.0%, 24.2%, 28.3%, 32.5%, 36.7%, 40.8%, 45.0%, 49.2%, 53.3%, 57.5%, 61.7%, or any combination of both; preferably, the proportion Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 28.3% to 53.3%.

[0056] When the distance X between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 1500 μm, the proportion Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 18.7% to 55.3%; specifically, the proportion Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 18.7%, 22.0%, 25.3%, 28.7%, 32.0%, 35.3%, 38.7%, 42.0%, 45.3%, 48.7%, 52.0%, 55.3%, or any combination of both; preferably, the proportion Y of the width of the first region 3 / second region 4 along the second direction to the distance between two adjacent first fine gates 8 or two adjacent second fine gates 9 is 28.7% to 52.0%.

[0057] Specifically, in some embodiments of this invention, the width difference between the first region and the second region along the second direction is 50μm to 200μm; the width of the isolation region between adjacent first and second regions along the second direction is 50μm to 300μm. Although there is a width difference between the first region and the second region along the second direction, the width of the first region or the second region along the second direction relative to the distance between two adjacent first grids or two adjacent second grids satisfies the relationship of this invention.

[0058] More specifically, in some embodiments of this utility model, the first conductive passivation layer 15 is a phosphorus-doped conductive passivation layer, and the second conductive passivation layer 17 is a boron-doped conductive passivation layer.

[0059] Specifically, in some embodiments of this utility model, the first conductive passivation layer 15 and / or the second conductive passivation layer 17 are doped polycrystalline silicon layers or doped stacked polycrystalline silicon layers containing silicon oxide layers; preferably, the first conductive passivation layer 15 is a phosphorus-doped polycrystalline silicon layer and the second conductive passivation layer 17 is a boron-doped polycrystalline silicon layer.

[0060] This invention also provides a battery assembly, including the aforementioned TBC solar cell.

[0061] Specifically, in some embodiments of this utility model, such as Figure 2-3 As shown, the first metal electrode 5 further includes a plurality of first main gates 10 that are spaced apart along the second direction and arranged along the first direction, and the first fine gate 8 and the first main gate 10 are connected along the second direction by a first interconnecting strip 11 at their intersection positions.

[0062] The second metal electrode 6 further includes a plurality of second main gates 12 spaced apart along the second direction and arranged along the first direction, wherein the second fine gate 9 and the second main gate 12 are connected along the second direction by a second interconnecting strip 13 at their intersection positions.

[0063] The present invention will be further described below with reference to specific embodiments.

[0064] Depend on Figure 1 It can be seen that the distance between two adjacent first fine gates along the second direction is equal to the distance between two adjacent second fine gates, both being the width of one first region + the width of one second region + the width of two isolation regions; therefore, in this embodiment, only the distance X between two adjacent first fine gates is used as an example for explanation. The first region and the second region have a width difference, but both are within the range of the above relationship; in this embodiment, only the width Z of the first region along the second direction is used as an example for explanation.

[0065] Example 1

[0066] This embodiment provides a TBC solar cell and a battery module, such as Figure 1-2 As shown, it includes:

[0067] Silicon substrate 1 has a front side and a back side that are positioned opposite to each other;

[0068] A front passivation layer 2 is disposed on the front side of the silicon substrate 1;

[0069] A first region 3 and a second region 4 are alternately disposed on the back side of the silicon substrate 1;

[0070] The first region 3 includes, in sequence along the direction away from the silicon substrate 1, a tunneling oxide layer 14, a phosphorus-doped polysilicon layer, a back passivation layer 16, and a metal positive electrode; the metal positive electrode is in ohmic contact with the phosphorus-doped polysilicon layer.

[0071] The second region 4, along the direction away from the silicon substrate 1, sequentially includes a tunneling oxide layer 14, a boron-doped polysilicon layer, a back passivation layer 16, and a metal negative electrode; the metal negative electrode is in ohmic contact with the boron-doped polysilicon layer.

[0072] An isolation region 7 is located between adjacent first region 3 and second region 4, and the isolation region 7 is recessed inward and closer to the silicon substrate 1 than the first region 3 and second region 4;

[0073] The metal positive electrode includes a plurality of first fine grids 8 extending along a first direction and arranged along a second direction, and a plurality of first main grids 12 spaced along the second direction and arranged along the first direction. The first fine grids 8 and the first main grids 12 are connected along the second direction by a first interconnecting strip 11 at their intersection positions.

[0074] The metal negative electrode includes a plurality of second fine grids 9 extending along a first direction and arranged along a second direction, and a plurality of second main grids 12 spaced along the second direction and arranged along the first direction. The intersection of the second fine grids 9 and the second main grids 12 is connected along the second direction by a second interconnecting strip 13.

[0075] The distance X between two adjacent first fine gates 8 is 1200 μm, the width Z of the first region 3 along the second direction is 740 μm, and the ratio Y of the width of the first region 3 along the second direction to the distance between two adjacent first fine gates 8 is 61.7%.

[0076] Examples 2-34, Comparative Examples 1-13

[0077] Examples 2-34 and Comparative Examples 1-13 differ from Example 1 only in the distance X between two adjacent first fine gates and the ratio Y of the width of the first region along the second direction to the distance between two adjacent first fine gates, as shown in Table 1. The rest are the same as in Example 1, and the test results are shown in Table 1.

[0078] Table 1

[0079]

[0080] As can be seen from the test results in Table 1, the TBC solar cell of this invention can improve the light transmittance of the solar cell, reduce the light absorption problem caused by excessive poly layer thickness, and ensure the excellent electrical performance of the cell by thinning and removing the area on the back of the silicon substrate that is not in contact with the metal electrode, and controlling the spacing between adjacent first grids and the width of the first / second region along the second direction.

[0081] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the substance and scope of the present invention. Various modifications made by those skilled in the art to the above embodiments after reading this specification are all within the scope of protection of the present invention.

Claims

1. A TBC solar cell, characterized in that, include: A silicon substrate having a front and a back side that are positioned opposite to each other; A front passivation layer is disposed on the front side of the silicon substrate; A first region and a second region are alternately disposed on the back side of the silicon substrate; The first region includes, in sequence along the direction away from the silicon substrate, a tunneling oxide layer, a first conductive passivation layer, a back passivation layer, and a first metal electrode, wherein the first metal electrode is in ohmic contact with the first conductive passivation layer; The second region includes, in sequence along the direction away from the silicon substrate, a tunneling oxide layer, a second conductive passivation layer, a back passivation layer, and a second metal electrode, wherein the second metal electrode is in ohmic contact with the second conductive passivation layer; The first conductive passivation layer and the second conductive passivation layer have opposite conductive media; An isolation region located between adjacent first and second regions, the isolation region being recessed inward and closer to the silicon substrate than the first and second regions; The first metal electrode includes a plurality of first fine grids extending along a first direction and arranged along a second direction; The second metal electrode includes a plurality of second fine grids extending along a first direction and arranged along a second direction; The TBC solar cell satisfies: 0.00007X+0.0767<Y<-0.00023X+0.9267; Where X is the distance between two adjacent first fine gates or two adjacent second fine gates, in μm; Y is the ratio of the width of the first / second region along the second direction to the distance between two adjacent first grids or two adjacent second grids.

2. The TBC solar cell according to claim 1, characterized in that, The distance X between two adjacent first fine grids or two adjacent second fine grids and the ratio Y of the width of the first region / second region along the second direction to the distance between two adjacent first fine grids or two adjacent second fine grids satisfy the following condition: 0.00001X+0.2433<Y<-0.00016X+0.7600.

3. The TBC solar cell according to claim 1, characterized in that, The distance X between two adjacent first fine gates or two adjacent second fine gates is 700μm~1500μm, the ratio Y of the width of the first region / second region along the second direction to the distance between two adjacent first fine gates or two adjacent second fine gates is 15.0%~65.0%, and the width Z of the first region / second region along the second direction is 150~830μm.

4. The TBC solar cell according to claim 3, characterized in that, The width of the first / second region along the second direction is 28.3% to 60.0% of the distance between two adjacent first or second fine gates, and the width of the first / second region along the second direction is 300 to 780 μm.

5. The TBC solar cell according to claim 1, characterized in that, The width difference between the first region and the second region along the second direction is 50μm to 450μm; the width of the isolation region between adjacent first and second regions along the second direction is 50μm to 300μm.

6. The TBC solar cell according to claim 1, characterized in that, The first conductive passivation layer and / or the second conductive passivation layer are doped polycrystalline silicon layers.

7. The TBC solar cell according to claim 1, characterized in that, The first conductive passivation layer and / or the second conductive passivation layer are doped multilayer polycrystalline silicon layers containing silicon oxide layers.

8. A battery assembly, characterized in that, The TBC solar cell includes any one of claims 1-7.

9. The battery assembly according to claim 8, characterized in that, The first metal electrode further includes a plurality of first main gates spaced apart along the second direction and arranged along the first direction, wherein the first fine gates and the first main gates are connected along the second direction by a first interconnecting strip at their intersection positions; The second metal electrode further includes a plurality of second main gates spaced apart along the second direction and arranged along the first direction, wherein the intersection of the second fine gate and the second main gate is connected along the second direction by a second interconnecting strip.

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