Circuit board structure for improving parallel wiring signal crosstalk in BGA (Ball Grid Array)
By setting periodic triangular trace units to extend the spacing within the BGA area, the problem of signal crosstalk in high-density BGA design is solved, achieving a balance between signal quality optimization and cost-effectiveness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHANGSHA QUANBO ELECTRONIC TECH CO LTD
- Filing Date
- 2025-03-20
- Publication Date
- 2026-04-17
AI Technical Summary
In high-density BGA design, traditional spacing rules are difficult to implement, layered routing cannot completely avoid crosstalk between parallel routing lines, increasing the number of layers is costly, and existing local optimization methods have limitations in high-density scenarios, making it difficult to effectively solve the signal crosstalk problem.
Periodically distributed triangular trace units are set within the BGA area to expand the spacing between parallel traces. The signal line spacing is expanded to more than three times the original spacing through the triangular trace units. The area density is dynamically adjusted and optimized according to the signal frequency to disperse electromagnetic coupling effects and avoid crosstalk accumulation.
It effectively reduces signal noise, optimizes electromagnetic interference and crosstalk issues, maintains trace density, does not increase trace layers, and is suitable for high-density cabling designs.
Smart Images
Figure CN224139190U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit board technology, and more specifically, to a circuit board structure for improving crosstalk between parallel traces in a BGA. Background Technology
[0002] Printed Circuit Boards (PCBs), as core components of electronic devices, play a crucial role in electrical connections, mechanical support, and signal transmission. With the advancement of electronic technology towards high-performance computing and high-density integration, Ball Grid Array (BGA) packages are widely used in high-end chips such as CPUs, GPUs, and FPGAs due to their high pin density and excellent thermal and electrical performance. However, while BGA packaging increases integration, its internal routing design faces significant challenges. Due to the compact layout of the BGA pad array, signal lines often need to be routed in parallel over long distances within a limited space when extending from the chip pins. This parallel routing structure is highly susceptible to electromagnetic coupling interference (i.e., crosstalk) between signals, leading to decreased signal integrity, transmission errors, or distortion, becoming a key issue restricting high-density PCB design.
[0003] In high-speed signal transmission scenarios, crosstalk between parallel traces is mainly caused by capacitive and inductive coupling effects. Traditionally, the common method to suppress crosstalk is to increase the spacing between adjacent signal lines, following the empirical rule of "spacing ≥ twice the trace width." For example, if the signal trace width is 0.1mm, the spacing should be at least 0.2mm to reduce coupling strength by minimizing electric field overlap. However, this rule is difficult to implement in high-density BGA designs. Taking a 1.0mm pitch BGA as an example, when two signal lines need to be routed between two adjacent pads, the trace width and spacing are typically compressed to 0.1mm (i.e., trace width / spacing / trace width are all 0.1mm). At this point, the available space is insufficient to meet the twice-spacing requirement, meaning that crosstalk problems in parallel traces cannot be resolved by conventional spacing adjustments.
[0004] To avoid long parallel traces, existing technologies typically employ a layered routing strategy, distributing some signal lines across different PCB layers and reducing parallel lengths through interlayer isolation. However, the number of routing layers in the BGA package area is limited by physical space and process complexity, making it difficult for layered designs to completely eliminate parallel traces. Another solution is to increase the number of PCB routing layers to expand routing space, thereby reducing parallel traces within the same layer. For cost-sensitive products such as consumer electronics, this solution lacks economic viability. Therefore, most designs are forced to ignore crosstalk issues with BGA leads in practical applications, sacrificing signal quality for cost control.
[0005] The above problems are worth solving. Utility Model Content
[0006] In order to overcome the problem that crosstalk in long-distance parallel traces is difficult to effectively solve in existing high-density BGA designs due to the inability to meet traditional spacing rules, the difficulty in completely avoiding parallelism in layered routing, and the high cost of increasing the number of layers, this utility model provides a circuit board structure to improve signal crosstalk in parallel traces within a BGA.
[0007] The technical solution of this utility model is as follows:
[0008] A circuit board structure for improving signal crosstalk of parallel traces in a BGA includes a BGA region disposed on the circuit board, wherein a plurality of parallel traces are disposed in the BGA region, and each pair of parallel traces is provided with a periodically distributed trace optimization region, wherein the trace optimization region is used to extend the spacing of the parallel traces.
[0009] According to the above-described scheme of this utility model, the routing optimization area includes a triangular routing unit disposed between adjacent surface mount pads in the BGA area. The triangular routing unit is disposed on one side of the parallel routing line, and the triangular routing unit expands the spacing of the parallel routing lines to more than three times the original spacing.
[0010] According to the above-described scheme of this utility model, the interval between adjacent triangular wiring units is 3-5mm.
[0011] According to the above-described scheme of this utility model, the line width of the triangular routing unit is consistent with the original line width of the parallel routing line.
[0012] According to the above-described scheme of this utility model, the triangular routing unit includes a first hypotenuse, a top side, and a second hypotenuse. The length of the first hypotenuse is not less than twice the routing line width, the length of the top side is not less than 1.5 times the routing line width, and the length of the second hypotenuse is not less than twice the routing line width.
[0013] According to the above-described scheme of this utility model, the top edge is parallel to the original direction of the parallel walking line.
[0014] According to the above-described scheme of this utility model, the line width of the parallel walking lines is 0.1mm, and the spacing between the parallel walking lines is 0.1mm.
[0015] According to the above-described scheme of this utility model, the periodic distribution density of the routing optimization area is dynamically adjusted according to the signal frequency, and the distribution density of the high-frequency signal area is higher than that of the low-frequency signal area.
[0016] According to the above-described solution, the beneficial effects of this utility model are that by periodically optimizing the spacing of parallel traces in the BGA area, the electromagnetic coupling effect is dispersed, the continuous interference accumulation of long-distance parallel traces is avoided, and the trace density is maintained. This can optimize and improve the electromagnetic interference and crosstalk between signal lines, reduce signal noise, and eliminate the need to add trace layers. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the structure of this utility model.
[0018] In the figure, the various attached figures are labeled as follows:
[0019] 10. BGA area; 11. Surface mount pad; 12. Parallel trace; 13. Triangle trace unit; 131. First hypotenuse; 132. Top edge; 133. Second hypotenuse. Detailed Implementation
[0020] To make the technical problems, technical solutions and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments.
[0021] It should be noted that the terms "comprising" and "having," and any variations thereof, in the specification and claims of this utility model are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices. Terms such as "set up" should be interpreted broadly; for example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two elements or the interaction between two elements, unless otherwise expressly defined. Terms such as "upper," "lower," "left," "right," "front," "rear," and "bottom" indicate orientations or positions based on the orientations or positions shown in the accompanying drawings, and are only for ease of description and should not be construed as limiting the present technical solution.
[0022] It should be noted that in high-speed signal transmission scenarios, crosstalk between parallel lines is mainly caused by capacitive and inductive coupling effects. In traditional designs, the conventional method to suppress crosstalk is to increase the spacing between adjacent signal lines, following the empirical rule of "spacing ≥ twice the line width". For example, if the signal line width is 0.1mm, the spacing should be at least 0.2mm to reduce coupling strength by minimizing electric field overlap. However, this rule is difficult to implement in high-density BGA designs. Taking a 1.0mm pitch BGA as an example, when two signal lines need to be routed between two adjacent pads, the line width and spacing are usually compressed to 0.1mm (i.e., line width / spacing / line width are all 0.1mm). At this point, the available space is insufficient to meet the twice-spacing requirement, meaning that crosstalk problems in parallel lines cannot be solved by conventional spacing adjustments.
[0023] To avoid long parallel traces, existing technologies typically employ a layered routing strategy, distributing some signal lines across different PCB layers and reducing parallel lengths through interlayer isolation. However, the number of routing layers in the BGA package area is limited by physical space and process complexity, making it difficult to completely eliminate parallel traces with layered design. For example, in a four-layer board design, typically only two signal layers are available for BGA area routing, with the remaining layers used for power and ground planes, resulting in some signal lines still needing to run parallel over long distances within the same layer. Furthermore, layered routing may introduce vias and cross-layer connections, increasing impedance discontinuities and delays in signal paths, which can negatively impact high-frequency signal transmission.
[0024] Another solution is to expand the routing space by increasing the number of PCB layers, thereby reducing parallel traces on the same layer. For example, upgrading a four-layer board to a six- or eight-layer board provides more signal layers. However, increasing the number of layers significantly increases manufacturing costs (the processing cost of multilayer boards is usually exponential with the number of layers), while also leading to increased board thickness and greater difficulty in thermal management. For cost-sensitive products such as consumer electronics, this solution is not economical, so most designs are forced to ignore crosstalk issues of BGA traces in practical applications, sacrificing signal quality for cost control.
[0025] Furthermore, existing technologies have attempted to employ local optimization techniques such as differential signals, shielded ground lines, or serpentine routing, but these methods also have limitations in high-density BGA scenarios. For example, differential pair routing requires more space, which contradicts the high-density requirements; the introduction of shielded ground lines may increase routing complexity; while serpentine routing can reduce parallel length through path twists, it introduces additional signal delay and phase distortion, and its applicability is limited, especially in GHz-level high-speed signals.
[0026] like Figure 1As shown, this embodiment provides a circuit board structure to improve signal crosstalk between parallel traces in a BGA. By periodically optimizing the spacing of the parallel traces 12 in the BGA chip, the electromagnetic coupling effect is dispersed, and the continuous interference accumulation of long-distance parallel traces is avoided. At the same time, the trace density is maintained, which can optimize and improve the electromagnetic interference and crosstalk between signal lines, reduce signal noise, and eliminate the need to add trace layers.
[0027] Specifically, the circuit board structure for improving crosstalk of parallel traces in a BGA includes a BGA region 10 disposed on the circuit board, wherein a plurality of parallel traces 12 are disposed in the BGA region 10, and each pair of parallel traces 12 is provided with a periodically distributed trace optimization region, wherein the trace optimization region is used to extend the spacing of the parallel traces 12.
[0028] In one embodiment, the routing optimization area includes triangular routing units 13 disposed between adjacent surface mount pads 11 within the BGA region 10. The triangular routing units 13 are located on one side of the parallel routing lines 12, and the triangular routing units 13 extend the spacing of the parallel routing lines 12 to more than three times the original spacing. The triangular routing units 13 suppress crosstalk by changing the path direction and locally expanding the spacing. By placing triangular routing units 13 on one side of the parallel routing lines 12 between adjacent surface mount pads 11 within the BGA region 10, the spacing between adjacent signal lines is extended to three times the original spacing (e.g., from 0.1mm to 0.3mm). This locally increased spacing significantly reduces capacitive coupling strength and disperses electromagnetic coupling effects, avoiding the continuous accumulation of interference in long-distance parallel routing lines 12, thereby effectively reducing signal crosstalk and noise.
[0029] In one embodiment, the line width of the triangular routing unit 13 is consistent with the original line width of the parallel routing line 12 to balance signal integrity and reduce layout complexity, and avoid impedance mismatch problems caused by structural abrupt changes.
[0030] In one embodiment, the spacing between adjacent triangular trace units 13 is 3-5mm. The triangular trace unit 13 includes a first hypotenuse 131, a top side 132, and a second hypotenuse 133. The length of the first hypotenuse 131 is not less than twice the trace width, the length of the top side 132 is not less than 1.5 times the trace width, and the length of the second hypotenuse 133 is not less than twice the trace width.
[0031] The top edge 132 is parallel to the original direction of the parallel routing line 12, ensuring the consistency of signal transmission direction and avoiding timing deviations caused by sudden changes in the path. The first inclined edge 131 and the second inclined edge 133 form a transition region, which gradually expands the trace spacing, avoids abrupt changes in spacing, ensures the smoothness of the trace path, and reduces electromagnetic field distortion of high-frequency signals at the spacing change points through a gradual layout, further reducing reflection noise and crosstalk accumulation.
[0032] In one embodiment, in a 1.0mm pitch BGA, the line width of the parallel trace 12 is 0.1mm, and the spacing of the parallel trace 12 is 0.1mm. This effectively suppresses crosstalk while maintaining high-density routing capabilities, overcoming the limitations of the traditional 2x spacing rule.
[0033] In one embodiment, the periodic distribution density of the routing optimization region is dynamically adjusted according to the signal frequency, with a higher distribution density in the high-frequency signal region than in the low-frequency signal region. The distribution density of the triangular routing structure is dynamically adjusted based on signal frequency differences (e.g., high-speed versus low-speed signals). A denser periodic distribution (e.g., 3mm interval) is used in the high-frequency signal region, while the spacing is appropriately wider (e.g., 5mm interval) in the low-frequency region, achieving optimized resource allocation while balancing signal quality and design efficiency.
[0034] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
[0035] The present utility model patent has been described above with reference to the accompanying drawings. Obviously, the implementation of the present utility model patent is not limited to the above-described manner. Any improvements made by adopting the inventive concept and technical solution of the present utility model patent, or the direct application of the inventive concept and technical solution of the present utility model patent to other occasions without modification, are all within the protection scope of the present utility model.
Claims
1. A circuit board structure for improving signal crosstalk in parallel traces within a BGA, characterized in that, It includes a BGA area disposed on a circuit board, wherein a plurality of parallel traces are provided in the BGA area, and each pair of parallel traces is provided with a periodically distributed trace optimization area, wherein the trace optimization area is used to extend the spacing of the parallel traces.
2. The circuit board structure for improving signal crosstalk of parallel traces within a BGA of claim 1, wherein, The routing optimization area includes triangular routing units located between adjacent surface mount pads within the BGA area. The triangular routing units are located on one side of the parallel routing lines, and the triangular routing units expand the spacing of the parallel routing lines to more than three times the original spacing.
3. The circuit board structure for improving signal crosstalk among parallel traces in a BGA of claim 2, wherein, The spacing between adjacent triangular wiring units is 3-5mm.
4. The circuit board structure for improving signal crosstalk among parallel traces in a BGA of claim 3, wherein, The line width of the triangular routing unit is consistent with the original line width of the parallel routing line.
5. A circuit board structure for improving signal crosstalk among parallel traces in a BGA according to any one of claims 2-4, wherein, The triangular routing unit includes a first hypotenuse, a top side, and a second hypotenuse. The length of the first hypotenuse is not less than twice the routing width, the length of the top side is not less than 1.5 times the routing width, and the length of the second hypotenuse is not less than twice the routing width.
6. The circuit board structure for improving signal crosstalk among parallel traces in a BGA of claim 5, wherein, The top edge is parallel to the original direction of the parallel walking line.
7. A circuit board structure for improving crosstalk of parallel traces within a BGA according to claim 1 or 6, characterized in that, The line width of the parallel walking lines is 0.1 mm, and the spacing between the parallel walking lines is 0.1 mm.
8. The circuit board structure for improving signal crosstalk among parallel traces in a BGA of claim 1 or 6, wherein, The periodic distribution density of the routing optimization area is dynamically adjusted according to the signal frequency, with the distribution density in the high-frequency signal area being higher than that in the low-frequency signal area.