Level conversion circuit
By designing level conversion modules and hysteresis modules in the level conversion circuit, the problem of level conversion between different modules in electronic product circuit systems is solved, achieving adaptability and noise immunity of level conversion, making it suitable for various circuit environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TIANSHUI TIANGUANG SEMICON
- Filing Date
- 2025-04-28
- Publication Date
- 2026-04-21
AI Technical Summary
Different modules in electronic product circuit systems require different level conversions, and existing technologies struggle to effectively achieve level conversions to meet the needs of different modules.
Design a level conversion circuit, including a level conversion module, a first hysteresis module and a second hysteresis module. The level conversion module amplifies or reduces the input voltage and outputs the converted voltage to the hysteresis module for locking and conversion. The hysteresis characteristic of the hysteresis module is used to avoid frequent output jumps caused by noise or jitter near the critical voltage.
The level conversion circuit adapts to the required levels of different modules, enhances noise immunity, and is suitable for electronic systems in various circuit environments.
Smart Images
Figure CN224154209U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of level conversion technology, and more specifically, to a level conversion circuit. Background Technology
[0002] As electronic products become increasingly feature-rich, their internal components also become more complex. Different modules within the circuitry of electronic products may require different voltage levels. This necessitates that the circuitry support voltage level conversion.
[0003] Therefore, how to design a module for level conversion in a circuit system is a problem that needs to be solved. Utility Model Content
[0004] The purpose of this application is to provide a level conversion circuit to address the shortcomings of the prior art and solve the level conversion problem.
[0005] To achieve the above objectives, the technical solution adopted in this application is as follows:
[0006] In a first aspect, this application provides a level conversion circuit, which includes: a level conversion module, a first hysteresis module, and a second hysteresis module;
[0007] The first input terminal of the level conversion module is used to connect to a first input voltage, the second input terminal of the level conversion module is used to connect to a second input voltage, the first input voltage and the second input voltage are differential input voltages, the first power supply terminal and the second power supply terminal of the level conversion module are used to connect to a power supply voltage, and the ground terminal of the level conversion module is used to ground.
[0008] The first input terminal of the first hysteresis module is connected to the first output terminal of the level conversion module, the second input terminal of the second hysteresis module is connected to the second output terminal of the level conversion module, and the ground terminal of the first hysteresis module is used for grounding, and the ground terminal of the second hysteresis module is used for grounding.
[0009] The output terminal of the first hysteresis module is used to output the first output voltage corresponding to the first input voltage, and the output terminal of the second hysteresis module is used to output the second output voltage corresponding to the second input voltage.
[0010] The level conversion module is used to amplify or reduce the voltage at the first output terminal and the second output terminal of the level conversion module when the first input voltage and the second input voltage change, and output a first conversion voltage to the first hysteresis module and a second conversion voltage to the second hysteresis module, wherein the first input voltage and the second input voltage change in opposite directions, and the first conversion voltage and the second conversion voltage change in opposite directions.
[0011] The first hysteresis module is used to lock and convert the first conversion voltage to obtain and output the first output voltage, and the second hysteresis module is used to lock and convert the second conversion voltage to obtain and output the second output voltage.
[0012] Optionally, the level conversion module includes: a level conversion unit and a step-down unit;
[0013] The first input terminal of the level conversion unit is used to connect to a first input voltage, and the second input terminal of the level conversion unit is used to connect to a second input voltage;
[0014] The first power supply terminal of the level conversion unit is connected to the first output terminal of the step-down unit, the second power supply terminal of the level conversion unit is connected to the second output terminal of the step-down unit, and the ground terminal of the level conversion unit is used for grounding.
[0015] The first output terminal of the level conversion unit is connected to the input terminal of the first hysteresis module, and the second output terminal of the level conversion unit is connected to the input terminal of the second hysteresis module.
[0016] The first and second input terminals of the step-down unit are used to connect to the power supply voltage. The step-down unit is used to step down the power supply voltage and output it to the level conversion unit.
[0017] Optionally, the level conversion unit includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
[0018] The gate of the first NMOS transistor is used to connect to the first input voltage, the gate of the second NMOS transistor is used to connect to the second input voltage, and the source of the first NMOS transistor and the source of the second NMOS transistor are grounded.
[0019] The drain of the first NMOS transistor is connected to the source of the first PMOS transistor and the gate of the second PMOS transistor, respectively, and the drain of the second NMOS transistor is connected to the gate of the first PMOS transistor and the source of the second PMOS transistor, respectively.
[0020] The drain of the first PMOS transistor is connected to the first output terminal of the buck unit, and the drain of the second PMOS transistor is connected to the second output terminal of the buck unit.
[0021] The drain of the second NMOS transistor and the source of the second PMOS transistor are also connected to the input terminal of the first hysteresis module.
[0022] Optionally, the step-down unit includes: a third PMOS transistor and a fourth PMOS transistor;
[0023] The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor.
[0024] The source of the third PMOS transistor is connected to the first power supply terminal of the level conversion unit, and the source of the fourth PMOS transistor is connected to the second power supply terminal of the level conversion unit.
[0025] The drains of the third PMOS transistor and the fourth PMOS transistor are used to connect to the power supply voltage.
[0026] Optionally, the first hysteresis module includes: a first inversion unit and a first flipping unit;
[0027] The input terminal of the first inverting unit is connected to the first output terminal of the level conversion module, and the output terminal of the first inverting unit is connected to the input terminal of the first flipping unit.
[0028] The output terminal of the first flip unit is connected to the input terminal of the first inverting unit, and the power supply terminal of the first flip unit is used to connect to the power supply voltage.
[0029] The output terminal of the first inverting unit is also used to output the first output voltage.
[0030] Optionally, the first inverting unit includes: a third NMOS transistor and a fifth PMOS transistor;
[0031] The gates of the third NMOS transistor and the fifth PMOS transistor are connected to the first output terminal of the level conversion module.
[0032] The source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the source of the fifth PMOS transistor and the input terminal of the first flip unit, respectively. The drain of the fifth PMOS transistor is used to connect to the power supply voltage.
[0033] The drain of the third NMOS transistor is also used to output the first output voltage.
[0034] Optionally, the first switching unit includes: a sixth PMOS transistor;
[0035] The gate of the sixth PMOS transistor is connected to the output terminal of the first switching unit, the source of the sixth PMOS transistor is connected to the input terminal of the first switching unit, and the drain of the sixth PMOS transistor is used to connect to the power supply voltage.
[0036] Optionally, the second hysteresis module includes: a second inversion unit and a second flipping unit;
[0037] The input terminal of the second inverting unit is connected to the second output terminal of the level conversion module, and the output terminal of the second inverting unit is connected to the input terminal of the second flipping unit.
[0038] The output terminal of the second flip unit is connected to the input terminal of the second inverting unit, and the power supply terminal of the second flip unit is used to connect to the power supply voltage;
[0039] The output terminal of the second inverting unit is also used to output a second output voltage.
[0040] Optionally, the second inverting unit includes: a fourth NMOS transistor and a seventh PMOS transistor;
[0041] The gates of the fourth NMOS transistor and the seventh PMOS transistor are connected to the second output terminal of the level conversion module.
[0042] The source of the fourth NMOS transistor is grounded, and the drain of the fourth NMOS transistor is connected to the source of the seventh PMOS transistor and the input terminal of the second flip unit, respectively. The drain of the seventh PMOS transistor is used to connect to the power supply voltage.
[0043] The drain of the fourth NMOS transistor is also used to output a second output voltage.
[0044] Optionally, the second switching unit includes: an eighth PMOS transistor;
[0045] The gate of the eighth PMOS transistor is connected to the output terminal of the second switching unit, the source of the eighth PMOS transistor is connected to the input terminal of the second switching unit, and the drain of the eighth PMOS transistor is used to connect to the power supply voltage.
[0046] Secondly, this application provides a circuit system including a level conversion circuit, a differential signal output circuit, and a level receiving circuit as described in the first aspect.
[0047] The beneficial effects of this application are as follows: The level conversion circuit includes a level conversion module, a first hysteresis module, and a second hysteresis module. The level conversion module amplifies or reduces the voltages at its first and second output terminals respectively when the first and second input voltages change in opposite directions, thereby inputting the reverse-changing first and second conversion voltages to the first and second hysteresis modules respectively, thus adapting to the required level of different modules. The first hysteresis module locks and converts the first conversion voltage to obtain and output the first output voltage, and the second hysteresis module locks and converts the second conversion voltage to obtain and output the second output voltage. Through the locking and conversion of the first and second conversion voltages by the first and second hysteresis modules, frequent output jumps caused by noise or jitter near the critical voltage are avoided. This embodiment adapts to the required level of different modules and enhances noise immunity through the level conversion circuit, thus adapting to electronic systems in various circuit environments. Attached Figure Description
[0048] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 This is a schematic diagram of a level conversion circuit provided in an embodiment of this application;
[0050] Figure 2 This is a schematic diagram of another level conversion circuit provided in an embodiment of this application;
[0051] Figure 3 This is a schematic diagram of another level conversion circuit provided in an embodiment of this application;
[0052] Figure 4 This is a schematic diagram of a circuit system provided in an embodiment of this application. Detailed Implementation
[0053] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.
[0054] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0055] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.
[0056] Different modules in the circuit system of an electronic product may require different voltage levels. This necessitates that the circuit system support level conversion. Therefore, how to design a level conversion module in the circuit system is a problem that needs to be solved.
[0057] This application proposes a level conversion circuit, comprising a level conversion module, a first hysteresis module, and a second hysteresis module. The level conversion module amplifies or reduces the voltages at its first and second output terminals when the received first and second input voltages change, converting the signal from a high-voltage domain to a low-voltage domain, or vice versa, thereby adapting to the required voltage levels of different modules. Then, the level conversion module outputs a first converted voltage and a second converted voltage to the first and second hysteresis modules respectively, allowing the first and second hysteresis modules to delay and convert the first and second converted voltages, respectively, to obtain and output the first and second output voltages. The hysteresis characteristics of the first and second hysteresis modules prevent frequent output jumps near the critical voltage due to noise or jitter.
[0058] Next, refer to Figure 1 The specific structure of the level conversion circuit is described. Among other things, Figure 1 This is a schematic diagram of a level conversion circuit provided in an embodiment of this application.
[0059] Optionally, the level conversion circuit includes: a level conversion module 10, a first hysteresis module 20, and a second hysteresis module 30.
[0060] Optionally, the first input terminal of the level conversion module 10 is used to connect to the first input voltage VCCA+, the second input terminal of the level conversion module 10 is used to connect to the second input voltage VCCA-, the first input voltage VCCA+ and the second input voltage VCCA- are differential input voltages, the first power supply terminal and the second power supply terminal of the level conversion module 10 are used to connect to the power supply voltage VCCB, and the grounding terminal GND of the level conversion module 10 is used to ground GND.
[0061] Optionally, the first input voltage VCCA+ and the second input voltage VCCA- are complementary signals. When in a balanced state, the first input voltage VCCA+ and the second input voltage VCCA- are equal. When the first input voltage VCCA+ rises, the second input voltage VCCA- falls, and when the first input voltage VCCA+ falls, the second input voltage VCCA- rises.
[0062] Optionally, the first input terminal of the first hysteresis module 20 is connected to the first output terminal of the level conversion module 10, the second input terminal of the second hysteresis module 30 is connected to the second output terminal of the level conversion module 10, and the grounding GND terminal of the first hysteresis module 20 is used for grounding GND, and the grounding GND terminal of the second hysteresis module 30 is used for grounding GND.
[0063] Optionally, the output terminal of the first hysteresis module 20 is used to output the first output voltage VO1 corresponding to the first input voltage VCCA+, and the output terminal of the second hysteresis module 30 is used to output the second output voltage VO2 corresponding to the second input voltage VCCA-.
[0064] Optionally, the level conversion module 10 is used to amplify or reduce the voltage at the first output terminal and the second output terminal of the level conversion module 10 when the first input voltage VCCA+ and the second input voltage VCCA- change, and output a first conversion voltage to the first hysteresis module 20 and a second conversion voltage to the second hysteresis module 30, wherein the first input voltage VCCA+ and the second input voltage VCCA- change in opposite directions, and the first conversion voltage and the second conversion voltage change in opposite directions.
[0065] Specifically, when the first input voltage VCCA+ rises and the second input voltage VCCA- falls, the level conversion module 10 amplifies its output voltage based on this change. Specifically, it amplifies the voltage at the first output terminal of the level conversion module and reduces the voltage at the second output terminal, thereby accelerating the voltage transition. This causes the first output voltage VO1 to rise rapidly and the second output voltage VO2 to fall rapidly. Conversely, when the first input voltage VCCA+ falls and the second input voltage VCCA- rises, the level conversion module 10 amplifies this change, accelerating the voltage transition, causing the first input voltage VCCA+ to fall rapidly and the second output voltage VO2 to rise rapidly.
[0066] Optionally, the first conversion voltage varies with the first input voltage VCCA+, and the second conversion voltage varies with the second input voltage VCCA-. Furthermore, the changing trends of the first and second conversion voltages are more pronounced than those of the first and second input voltages VCCA+ and VCCA-.
[0067] For example, if the first input voltage VCCA+ is 1.5 volts, the second input voltage VCCA- is 1.5 volts, and the voltages at the first and second output terminals of the level conversion module 10 are both 2.5 volts, then when the first input voltage VCCA+ rises to 2 volts and the second input voltage VCCA- drops to 1 volt, the first conversion voltage output by the first output terminal can be 4 volts, and the second conversion voltage output by the second output terminal can be 1 volt.
[0068] Optionally, the first hysteresis module 20 is used to lock and convert the first conversion voltage to obtain and output the first output voltage VO1, and the second hysteresis module 30 is used to lock and convert the second conversion voltage to obtain and output the second output voltage VO2.
[0069] Optionally, both the first hysteresis module 20 and the second hysteresis module 30 have toggling thresholds, including a rising toggling threshold and a falling toggling threshold. Based on this, during the process of the first conversion voltage gradually increasing from a low level to a high level, when the first conversion voltage does not exceed the rising threshold voltage, the first output voltage of the first hysteresis module is locked at a low level; when the first conversion voltage exceeds the rising threshold voltage, the output first output voltage VO1 transitions from a low level to a high level. During the process of the first conversion voltage gradually decreasing from a high level to a low level, when the first conversion voltage does not exceed the falling threshold voltage, the first output voltage of the first hysteresis module is locked at a high level; when the first conversion voltage is lower than the falling threshold voltage, the output first output voltage VO1 transitions from a high level to a low level. The working principle of the second hysteresis module 30 is the same as that of the first hysteresis module 20, and will not be described again here.
[0070] Optionally, the switching threshold can be adjusted by changing the series resistor value, thereby regulating the hysteresis window width. The hysteresis window width is the voltage width between the rising threshold voltage and the falling threshold voltage. A larger hysteresis window width results in better hysteresis performance.
[0071] In this embodiment, the level conversion circuit includes a level conversion module, a first hysteresis module, and a second hysteresis module. The level conversion module amplifies or reduces the voltages at its first and second output terminals respectively when the first and second input voltages change in opposite directions. This amplifies or reduces the voltages at the first and second output terminals respectively, thus inputting the reverse-changing first and second conversion voltages to the first and second hysteresis modules, thereby adapting to the required level of different modules. The first hysteresis module locks and converts the first conversion voltage to obtain and output the first output voltage, and the second hysteresis module locks and converts the second conversion voltage to obtain and output the second output voltage. By locking and converting the first and second conversion voltages through the first and second hysteresis modules, frequent output jumps caused by noise or jitter near the critical voltage are avoided. This embodiment adapts to the required level of different modules and enhances noise immunity through the level conversion circuit, thus adapting to electronic systems in various circuit environments.
[0072] Next, refer to Figure 2 The specific structure of the level conversion module 10 in the level conversion circuit is described below. Optionally, Figure 2 This is a schematic diagram of another level conversion circuit provided in an embodiment of this application.
[0073] Optionally, the level conversion module 10 includes a level conversion unit 101 and a step-down unit 102.
[0074] Optionally, the first input terminal of the level conversion unit 101 is used to connect to the first input voltage VCCA+, and the second input terminal of the level conversion unit 101 is used to connect to the second input voltage VCCA-.
[0075] Optionally, the first power supply terminal of the level conversion unit 101 is connected to the first output terminal of the step-down unit 102, the second power supply terminal of the level conversion unit 101 is connected to the second output terminal of the step-down unit 102, and the ground GND terminal of the level conversion unit 101 is used for grounding GND.
[0076] Optionally, the first output terminal of the level conversion unit 101 is connected to the input terminal of the first hysteresis module 20, and the second output terminal of the level conversion unit 101 is connected to the input terminal of the second hysteresis module 30.
[0077] Optionally, the first and second input terminals of the step-down unit 102 are used to connect to the power supply voltage VCCB, and the step-down unit 102 is used to step down the power supply voltage VCCB and output it to the level conversion unit 101.
[0078] Specifically, the step-down unit 102 steps down the power supply voltage VCCB and inputs the stepped-down voltage to the first power supply terminal and the second power supply terminal of the level conversion unit 101, thereby providing a flexible power supply for the level conversion unit 101.
[0079] For example, if the power supply voltage VCCB is 5 volts, the step-down unit 102 can step down the 5 volts to obtain a stepped-down voltage of 4.3 volts, and use the 4.3 volts as the power supply for the level conversion unit 101.
[0080] In this embodiment, the step-down unit provides the step-down voltage to the level conversion unit, thereby enabling the level conversion unit to operate stably based on the step-down voltage.
[0081] As an optional implementation method, Figure 3 This is a schematic diagram of another level conversion circuit provided in an embodiment of this application. For example... Figure 3 As shown, the level conversion unit 101 includes: a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, and a second PMOS transistor M4.
[0082] Optionally, the gate of the first NMOS transistor M1 is used to connect to the first input voltage VCCA+, the gate of the second NMOS transistor M2 is used to connect to the second input voltage VCCA-, and the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are grounded to GND.
[0083] Optionally, the drain of the first NMOS transistor M1 is connected to the source of the first PMOS transistor M3 and the gate of the second PMOS transistor M4, respectively, and the drain of the second NMOS transistor M2 is connected to the gate of the first PMOS transistor M3 and the source of the second PMOS transistor M4, respectively.
[0084] Optionally, the drain of the first PMOS transistor M3 is connected to the first output terminal of the buck unit 102, and the drain of the second PMOS transistor M4 is connected to the second output terminal of the buck unit 102.
[0085] Optionally, the drain of the second NMOS transistor M2 and the source of the second PMOS transistor M4 are also connected to the input terminal of the first hysteresis module 20, and the drain of the first NMOS transistor M1 and the source of the first PMOS transistor M3 are also connected to the input terminal of the second hysteresis module 30.
[0086] Among them, the first NMOS transistor M1 and the second NMOS transistor M2 are symmetrical, and the first PMOS transistor M3 and the second PMOS transistor M4 are symmetrical to avoid DC offset caused by positive feedback imbalance.
[0087] Next, the working principle of the level conversion unit 101 will be introduced: In the balanced state, the first input signal and the second input signal are equal. At this time, the gate voltages of the first NMOS transistor M1 and the second NMOS transistor M2 are comparable, and the drain currents are the same. The gate voltages of the first PMOS transistor M3 and the second PMOS transistor M4 are controlled by the drain voltages of the first NMOS transistor M1 and the second NMOS transistor M2, so the conduction degree is symmetrical.
[0088] When the first input voltage VCCA+ increases and the second input voltage VCCA- decreases, the drain current of the first NMOS transistor M1 increases, and its drain voltage decreases. Because the drain voltage of the first NMOS transistor M1 decreases, the gate voltage of the second PMOS transistor M4 at the same potential decreases, thus enhancing the conduction of the second PMOS transistor M4 and increasing its drain current. Current flows from the second current terminal through the drain to the source of the second PMOS transistor M4, causing the first conversion voltage output from the first output terminal to increase. At this time, the gate voltage of the first PMOS transistor M3 increases, causing its conduction to weaken and its drain current to decrease. Furthermore, the source current of the first PMOS transistor M3 decreases, and the drain voltage of the first NMOS transistor M1 decreases further.
[0089] Based on this, as the drain voltage of the first NMOS transistor M1 decreases, the second PMOS transistor M4 further turns on, the drain voltage of the second NMOS transistor M2 further increases, the conduction of the first PMOS transistor M3 further weakens, and the drain voltage of the first NMOS transistor M1 further decreases. This forms a positive feedback loop, accelerating signal transitions.
[0090] During this process, positive feedback causes the equivalent impedance of the first and second output terminals of the level conversion module 10 to be negative, thereby canceling parasitic resistance, reducing the time constant, and improving bandwidth and conversion rate. This allows the circuit to be used in circuits with high edge rate requirements, such as high-speed comparators, differential amplifiers, and clock data recovery.
[0091] Similarly, when the first input voltage VCCA+ decreases and the second input voltage VCCA- increases, the drain current of the first NMOS transistor M1 decreases and its drain voltage increases, the conduction of the second PMOS transistor M4 weakens, the drain voltage of the second NMOS transistor M2 decreases, the conduction of the first PMOS transistor M3 strengthens, its drain current increases, and the drain voltage of the first NMOS transistor M1 further increases, thereby forming reverse positive feedback and accelerating signal conversion.
[0092] In this embodiment, by using the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor, an equivalent negative resistance is generated by utilizing the cascading reaction of current and voltage when the first input voltage and the second input voltage change, thereby improving signal conversion efficiency and generating the required levels for different modules.
[0093] As an optional implementation method, Figure 3 This is a schematic diagram of another level conversion circuit provided in an embodiment of this application. For example... Figure 3 As shown, the step-down unit 102 includes a third PMOS transistor M5 and a fourth PMOS transistor M6.
[0094] Optionally, the gate of the third PMOS transistor M5 and the gate of the fourth PMOS transistor M6 are connected.
[0095] Optionally, the source of the third PMOS transistor M5 is connected to the first power supply terminal of the level conversion unit 101, and the source of the fourth PMOS transistor M6 is connected to the second power supply terminal of the level conversion unit 101.
[0096] Optionally, the drain of the third PMOS transistor M5 and the drain of the fourth PMOS transistor M6 are used to connect to the power supply voltage VCCB.
[0097] With this simple structure of the third PMOS transistor M5 and the fourth PMOS transistor M6, the power supply voltage VCCB can be stepped down without external feedback, providing a low-voltage power supply for the level conversion unit 101.
[0098] In addition, the third PMOS transistor M5 and the fourth PMOS transistor M6 are connected in parallel to reduce the output impedance, provide a larger load current, and enhance stability.
[0099] In this embodiment, the power supply voltage is stepped down by the third and fourth PMOS transistors to provide a stable voltage for the level conversion unit.
[0100] Next, refer to Figure 2 The specific structure of the first hysteresis module 20 is described below. The first hysteresis module 20 includes: a first inversion unit 201 and a first flip unit 202.
[0101] Optionally, the input terminal of the first inverting unit 201 is connected to the first output terminal of the level conversion module 10, and the output terminal of the first inverting unit 201 is connected to the input terminal of the first flipping unit 202.
[0102] Optionally, the output terminal of the first flip unit 202 is connected to the input terminal of the first inverting unit 201, and the power supply terminal of the first flip unit 202 is used to connect to the power supply voltage VCCB.
[0103] Optionally, the output terminal of the first inverting unit 201 is also used to output the first output voltage VO1.
[0104] The first inverting unit 201 receives the first conversion voltage output from the first output terminal of the level conversion module 10 and converts the first conversion voltage to its opposite level. Specifically, if the first conversion voltage is high, the output terminal outputs a low level; if the first conversion voltage is low, the output terminal outputs a high level.
[0105] Specifically, when the input voltage of the first inverting unit 201 increases, its output decreases. At this time, the current of the first flipping unit 202 increases, causing the input of the first inverting unit 201 to continue to increase, thus achieving a hysteresis effect. Similarly, when the input voltage of the first inverting unit 201 decreases, its output increases. At this time, the current of the first flipping unit 202 decreases, causing the input of the first inverting unit 201 to continue to decrease, thus achieving a hysteresis effect.
[0106] In this embodiment, the first conversion voltage output by the level conversion module is regulated by the first inverting unit and the first flipping unit, thereby suppressing noise interference and improving circuit stability.
[0107] Next, refer to Figure 3 The specific structure of the first inverting unit 201 is described below. The first inverting unit 201 includes: a third NMOS transistor M7 and a fifth PMOS transistor M8.
[0108] Optionally, the gates of the third NMOS transistor M7 and the fifth PMOS transistor M8 are connected to the first output terminal of the level conversion module 10.
[0109] Optionally, the source of the third NMOS transistor M7 is grounded to GND, and the drain of the third NMOS transistor M7 is connected to the source of the fifth PMOS transistor M8 and the input terminal of the first switching unit 202, respectively. The drain of the fifth PMOS transistor M8 is used to connect to the power supply voltage VCCB.
[0110] Optionally, the drain of the third NMOS transistor M7 is also used to output the first output voltage VO1.
[0111] Optionally, based on the characteristics of the third NMOS transistor M7 and the fifth PMOS transistor M8, the first inverting unit 201 also has a threshold voltage. The threshold voltage determines when the first switching voltage triggers the output state flip of the first inverting unit 201.
[0112] Specifically, by alternating the conduction of the third NMOS transistor M7 and the fifth PMOS transistor M8, the output decreases when the input increases and increases when the input decreases, while ensuring low power consumption.
[0113] In this embodiment, the input first conversion voltage is reverse-converted by the third NMOS transistor and the fifth PMOS transistor.
[0114] Furthermore, referring to Figure 3 The specific structure of the first switching unit 202 is described below. The first switching unit 202 includes: the sixth PMOS transistor M9.
[0115] Optionally, the gate of the sixth PMOS transistor M9 is connected to the output terminal of the first switching unit 202, the source of the sixth PMOS transistor M9 is connected to the input terminal of the first switching unit 202, and the drain of the sixth PMOS transistor M9 is used to connect to the power supply voltage VCCB.
[0116] Based on this, the working principle of the first hysteresis module 20 will be introduced next. Assuming the input of the first inverting unit 201 is low, the output of the first inverting unit 201 is high, i.e., the power supply voltage VCCB. At this time, the sixth PMOS transistor M9 is turned on, providing current support. The input of the first inverting unit 201 begins to rise. When it rises to near the voltage threshold of the first inverting unit 201, the output of the first inverting unit 201 decreases, the conduction of the sixth PMOS transistor M9 is further enhanced, the current increases, and its source injects more current into the input terminal of the first inverting unit 201, causing the input of the first inverting unit 201 to rise further, so that the first conversion voltage of the input quickly exceeds the voltage threshold of the first inverting unit 201. When the input of the first inverting unit 201 begins to fall, the output voltage of the first inverting unit 201 increases, the conduction of the sixth PMOS transistor M9 weakens, the current decreases, the input terminal of the first inverting unit 201 is pulled low, and the input voltage decreases further, thus causing the first conversion voltage of the input to quickly exceed the voltage threshold of the first inverting unit 201.
[0117] Furthermore, due to the conduction characteristics of the sixth PMOS transistor M9, a rising threshold voltage and a falling threshold voltage can be generated based on the threshold voltage of the first inverting unit 201. Therefore, voltage switching is triggered only when the first switching voltage rises above the rising threshold voltage; similarly, voltage switching is triggered only when the first switching voltage falls below the falling threshold voltage.
[0118] In this embodiment, the first inverting unit is fed back through the sixth PMOS transistor, thereby decoupling the rate of change and amplitude of the first conversion voltage through positive feedback, achieving noise suppression and signal shaping.
[0119] Next, refer to Figure 2 The second hysteresis module 30 in the level conversion circuit is described below. The second hysteresis module 30 includes: a second inverting unit 301 and a second flipping unit 302.
[0120] Optionally, the input terminal of the second inverting unit 301 is connected to the second output terminal of the level conversion module 10, and the output terminal of the second inverting unit 301 is connected to the input terminal of the second flipping unit 302.
[0121] Optionally, the output terminal of the second flip unit 302 is connected to the input terminal of the second flip unit 302, and the power supply terminal of the second flip unit 302 is used to connect to the power supply voltage VCCB.
[0122] Optionally, the output terminal of the second inverting unit 301 is also used to output a second output voltage VO2.
[0123] The second inverting unit 301 receives the second converted voltage output from the second output terminal of the level conversion module 10 and converts the second converted voltage to its opposite level. Specifically, if the second converted voltage is high, the output terminal outputs a low level; if the second converted voltage is low, the output terminal outputs a high level.
[0124] Specifically, when the input voltage of the second inverting unit 301 increases, its output decreases. At this time, the current of the second flipping unit 302 increases, causing the input of the second inverting unit 301 to continue to increase, thus achieving a hysteresis effect. Similarly, when the input voltage of the second inverting unit 301 decreases, its output increases. At this time, the current of the second flipping unit 302 decreases, causing the input of the second inverting unit 301 to continue to decrease, thus achieving a hysteresis effect.
[0125] In this embodiment, the second conversion voltage output by the level conversion module is stabilized by the second inverting unit and the second flipping unit, thereby suppressing noise interference and improving circuit stability.
[0126] Furthermore, referring to Figure 3 The specific structure of the second inverting unit 301 is described below. The second inverting unit 301 includes: a fourth NMOS transistor M10 and a seventh PMOS transistor M11.
[0127] Optionally, the gates of the fourth NMOS transistor M10 and the seventh PMOS transistor M11 are connected to the second output terminal of the level conversion module 10.
[0128] Optionally, the source of the fourth NMOS transistor M10 is grounded to GND, and the drain of the fourth NMOS transistor M10 is connected to the source of the seventh PMOS transistor M11 and the input terminal of the second flip unit 302, respectively. The drain of the seventh PMOS transistor M11 is used to connect to the power supply voltage VCCB.
[0129] Optionally, the drain of the fourth NMOS transistor M10 is also used to output the second output voltage VO2.
[0130] Optionally, based on the characteristics of the fourth NMOS transistor M10 and the seventh PMOS transistor M11, the second inverting unit 301 also has a threshold voltage. The threshold voltage determines when the second switching voltage triggers the output state flip of the second inverting unit 301.
[0131] Specifically, by alternating the conduction of the fourth NMOS transistor M10 and the seventh PMOS transistor M11, the output decreases when the input increases and increases when the input decreases, while ensuring low power consumption.
[0132] In this embodiment, the input second conversion voltage is reverse-converted by the fourth NMOS transistor and the seventh PMOS transistor.
[0133] Furthermore, referring to Figure 3 The specific structure of the second switching unit 302 is described below. The second switching unit 302 includes: the eighth PMOS transistor M12.
[0134] The gate of the eighth PMOS transistor M12 is connected to the output terminal of the second flip unit 302, the source of the eighth PMOS transistor M12 is connected to the input terminal of the second flip unit 302, and the drain of the eighth PMOS transistor M12 is used to connect to the power supply voltage VCCB.
[0135] Based on this, the working principle of the second hysteresis module 30 will be described below. Assuming the input of the second inverting unit 301 is low, its output is high, i.e., the power supply voltage VCCB. At this time, the eighth PMOS transistor M12 is turned on, providing current support. The input of the second inverting unit 301 begins to rise. When it approaches the voltage threshold of the second inverting unit 301, its output decreases, the conduction of the eighth PMOS transistor M12 is further enhanced, the current increases, and its source injects more current into the input of the second inverting unit 301, causing the input of the second inverting unit 301 to rise further, allowing the input second conversion voltage to quickly exceed the voltage threshold of the second inverting unit 301. When the input of the second inverting unit 301 begins to fall, its output voltage increases, the conduction of the eighth PMOS transistor M12 weakens, the current decreases, the input of the second inverting unit 301 is pulled low, and the input voltage decreases further, thus allowing the input second conversion voltage to quickly exceed the voltage threshold of the second inverting unit 301.
[0136] Furthermore, due to the conduction characteristics of the eighth PMOS transistor M12, a rising threshold voltage and a falling threshold voltage can be generated based on the threshold voltage of the second inverting unit 301. Therefore, voltage switching is triggered only when the second switching voltage rises above the rising threshold voltage; similarly, voltage switching is triggered only when the second switching voltage falls below the falling threshold voltage.
[0137] In this embodiment, the second inverting unit is fed back through the eighth PMOS transistor, thereby decoupling the rate of change and amplitude of the second conversion voltage through positive feedback, achieving noise suppression and signal shaping.
[0138] This application also provides a circuit system, such as Figure 4 As shown, where, Figure 4 This is a schematic diagram of a circuit system provided in an embodiment of this application. The circuit system includes the level conversion circuit, differential signal output circuit, and level receiving circuit described above.
[0139] Specifically, the first and second output terminals of the differential signal output circuit are connected to the first and second input terminals of the level conversion circuit, and the first and second output terminals of the level conversion circuit are connected to the first and second input terminals of the level receiving circuit, respectively.
[0140] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A level shifting circuit, characterized by, The level conversion circuit includes: a level conversion module, a first hysteresis module, and a second hysteresis module; The first input terminal of the level conversion module is used to connect to a first input voltage, the second input terminal of the level conversion module is used to connect to a second input voltage, the first input voltage and the second input voltage are differential input voltages, the first power supply terminal and the second power supply terminal of the level conversion module are used to connect to a power supply voltage, and the ground terminal of the level conversion module is used to ground. The first input terminal of the first hysteresis module is connected to the first output terminal of the level conversion module, the second input terminal of the second hysteresis module is connected to the second output terminal of the level conversion module, and the ground terminal of the first hysteresis module is used for grounding, and the ground terminal of the second hysteresis module is used for grounding. The output terminal of the first hysteresis module is used to output the first output voltage corresponding to the first input voltage, and the output terminal of the second hysteresis module is used to output the second output voltage corresponding to the second input voltage. The level conversion module is used to amplify or reduce the voltage at the first output terminal and the second output terminal of the level conversion module when the first input voltage and the second input voltage change, and output a first conversion voltage to the first hysteresis module and a second conversion voltage to the second hysteresis module, wherein the first input voltage and the second input voltage change in opposite directions, and the first conversion voltage and the second conversion voltage change in opposite directions. The first hysteresis module is used to lock and convert the first conversion voltage to obtain and output the first output voltage, and the second hysteresis module is used to lock and convert the second conversion voltage to obtain and output the second output voltage.
2. The level shifting circuit of claim 1, wherein, The level conversion module includes: a level conversion unit and a step-down unit; The first input terminal of the level conversion unit is used to connect to a first input voltage, and the second input terminal of the level conversion unit is used to connect to a second input voltage; The first power supply terminal of the level conversion unit is connected to the first output terminal of the step-down unit, the second power supply terminal of the level conversion unit is connected to the second output terminal of the step-down unit, and the ground terminal of the level conversion unit is used for grounding. The first output terminal of the level conversion unit is connected to the input terminal of the first hysteresis module, and the second output terminal of the level conversion unit is connected to the input terminal of the second hysteresis module. The first and second input terminals of the step-down unit are used to connect to the power supply voltage. The step-down unit is used to step down the power supply voltage and output it to the level conversion unit.
3. The level shifting circuit of claim 2, wherein, The level conversion unit includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; The gate of the first NMOS transistor is used to connect to the first input voltage, the gate of the second NMOS transistor is used to connect to the second input voltage, and the source of the first NMOS transistor and the source of the second NMOS transistor are grounded. The drain of the first NMOS transistor is connected to the source of the first PMOS transistor and the gate of the second PMOS transistor, respectively, and the drain of the second NMOS transistor is connected to the gate of the first PMOS transistor and the source of the second PMOS transistor, respectively. The drain of the first PMOS transistor is connected to the first output terminal of the buck unit, and the drain of the second PMOS transistor is connected to the second output terminal of the buck unit. The drain of the second NMOS transistor and the source of the second PMOS transistor are also connected to the input terminal of the first hysteresis module.
4. The level shifting circuit of claim 2, wherein, The step-down unit includes: a third PMOS transistor and a fourth PMOS transistor; The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the third PMOS transistor is connected to the first power supply terminal of the level conversion unit, and the source of the fourth PMOS transistor is connected to the second power supply terminal of the level conversion unit. The drains of the third PMOS transistor and the fourth PMOS transistor are used to connect to the power supply voltage.
5. The level shifting circuit of claim 1, wherein, The first hysteresis module includes: a first inversion unit and a first flip unit; The input terminal of the first inverting unit is connected to the first output terminal of the level conversion module, and the output terminal of the first inverting unit is connected to the input terminal of the first flipping unit. The output terminal of the first flip unit is connected to the input terminal of the first inverting unit, and the power supply terminal of the first flip unit is used to connect to the power supply voltage. The output terminal of the first inverting unit is also used to output the first output voltage.
6. The level shifting circuit of claim 5, wherein, The first inverting unit includes: a third NMOS transistor and a fifth PMOS transistor; The gates of the third NMOS transistor and the fifth PMOS transistor are connected to the first output terminal of the level conversion module. The source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the source of the fifth PMOS transistor and the input terminal of the first flip unit, respectively. The drain of the fifth PMOS transistor is used to connect to the power supply voltage. The drain of the third NMOS transistor is also used to output the first output voltage.
7. The level shifting circuit of claim 5, wherein, The first switching unit includes: a sixth PMOS transistor; The gate of the sixth PMOS transistor is connected to the output terminal of the first switching unit, the source of the sixth PMOS transistor is connected to the input terminal of the first switching unit, and the drain of the sixth PMOS transistor is used to connect to the power supply voltage.
8. The level shifting circuit of claim 1, wherein, The second hysteresis module includes: a second inversion unit and a second flipping unit; The input terminal of the second inverting unit is connected to the second output terminal of the level conversion module, and the output terminal of the second inverting unit is connected to the input terminal of the second flipping unit. The output terminal of the second flip unit is connected to the input terminal of the second inverting unit, and the power supply terminal of the second flip unit is used to connect to the power supply voltage; The output terminal of the second inverting unit is also used to output a second output voltage.
9. The level shifting circuit of claim 8, wherein, The second inverting unit includes: a fourth NMOS transistor and a seventh PMOS transistor; The gates of the fourth NMOS transistor and the seventh PMOS transistor are connected to the second output terminal of the level conversion module. The source of the fourth NMOS transistor is grounded, and the drain of the fourth NMOS transistor is connected to the source of the seventh PMOS transistor and the input terminal of the second flip unit, respectively. The drain of the seventh PMOS transistor is used to connect to the power supply voltage. The drain of the fourth NMOS transistor is also used to output a second output voltage.
10. The level shifting circuit of claim 8, wherein, The second switching unit includes: an eighth PMOS transistor; The gate of the eighth PMOS transistor is connected to the output terminal of the second switching unit, the source of the eighth PMOS transistor is connected to the input terminal of the second switching unit, and the drain of the eighth PMOS transistor is used to connect to the power supply voltage.