Analog signal transmission circuit

Abstract

The utility model relates to an analog signal transmission circuit, which comprises a voltage conversion chip, an operational amplifier circuit, a first anti-interference circuit, a second anti-interference circuit and a protection circuit, the voltage conversion chip is suitable for accessing a rotating speed signal, and the output end of the voltage conversion chip is electrically connected with the input end of the operational amplification circuit; the positive phase input end of the first operational amplifier is electrically connected with the output end of the voltage conversion chip, and the output end of the first operational amplifier is electrically connected with the positive phase input end of the second operational amplifier; the output end of the second operational amplifier is electrically connected with the input end of the first inductor, and the output end of the first inductor is electrically connected with the input end of the second inductor; the output end of the second inductor is electrically connected with the input end of the third inductor; the output end of the third inductor is electrically connected with the input end of the fourth inductor; the protection circuit includes: a transient suppression diode; and the fourth inductor outputs a rotating speed signal through the transient suppression diode.

Description

Technical Field

[0001] This application relates to the field of signal transmission technology, and in particular to an analog signal transmission circuit. Background Technology

[0002] With the rapid development of industrial technology, special equipment often needs to collect signals. For example, flight control equipment needs to collect the rotational speed information of each rotor of the aircraft in order to achieve precise control of the aircraft's attitude. In this process, the accuracy of rotational speed signal transmission is becoming increasingly important. At present, rotational speed signals often suffer from poor anti-interference ability and unstable transmission during transmission, resulting in low signal accuracy, inaccurate rotational speed acquisition, affecting the working stability of flight control equipment, and making it difficult to meet the needs of actual applications.

[0003] This application proposes an analog signal transmission circuit suitable for improving the stability of signal transmission. Summary of the Invention

[0004] In view of this, this application proposes an analog signal transmission circuit.

[0005] According to one aspect of this application, an analog signal transmission circuit is provided, comprising: a voltage conversion chip U8, an operational amplifier circuit, a first anti-interference circuit, a second anti-interference circuit, and a protection circuit;

[0006] The input terminal of voltage conversion chip U8 is suitable for receiving speed signals, and the output terminal of voltage conversion chip U8 is electrically connected to the input terminal of operational amplifier circuit;

[0007] The operational amplifier circuit includes: a first operational amplifier U7A and a second operational amplifier U7B; the non-inverting input terminal of the first operational amplifier U7A is electrically connected to the output terminal of the voltage conversion chip U8, and the output terminal of the first operational amplifier U7A is electrically connected to the non-inverting input terminal of the second operational amplifier U7B.

[0008] The first anti-interference circuit includes: a first inductor TA5, a second inductor TA6, a capacitor C56, a capacitor C58, and a capacitor C59; the output terminal of the second operational amplifier is electrically connected to the input terminal of the first inductor TA5 through the capacitor C56, and the output terminal of the first inductor TA5 is electrically connected to the input terminal of the second inductor TA6 through the capacitor C58.

[0009] The second anti-interference circuit includes: a third inductor TA8, a fourth inductor TA7, capacitors C70, C71, C64, and C65; the output terminal of the second inductor TA6 is electrically connected to the input terminal of the third inductor TA8 through capacitors C59 and C70, and the output terminal of the third inductor TA8 is electrically connected to the input terminal of the fourth inductor TA7 through capacitors C71 and C64.

[0010] The protection circuit includes: a transient suppression diode TVSA1; the output terminal of the fourth inductor TA7 is electrically connected to the transient suppression diode TVSA1 through a capacitor C65, and the fourth inductor TA7 is suitable for outputting a speed signal through the transient suppression diode TVSA1.

[0011] In one possible implementation, the output of the voltage conversion chip U8 is electrically connected to the non-inverting input of the first operational amplifier U7A through a filter circuit.

[0012] In one possible implementation, the output of the second operational amplifier U7B is electrically connected to the input of the first inductor TA5 through a filter circuit.

[0013] In one possible implementation, the output of the second inductor TA6 is electrically connected to the input of the third inductor TA8 through two filter circuits.

[0014] In one possible implementation, the output of the third inductor TA8 is electrically connected to the input of the fourth inductor TA7 through two filter circuits.

[0015] In one possible implementation, the filter circuit includes a resistor and a capacitor connected in series.

[0016] In one possible implementation, the protection circuit also includes: a third operational amplifier U9A;

[0017] The non-inverting input of the third operational amplifier U9A is electrically connected to the output of the fourth inductor TA7, and the output of the third operational amplifier U9A is electrically connected to the transient suppression diode TVSA1.

[0018] In one possible implementation, the protection circuit also includes a fifth inductor U10, and the output of the third operational amplifier U9A is electrically connected to the transient suppression diode TVSA1 through the fifth inductor U10.

[0019] Beneficial Effects: The voltage conversion chip U8 is suitable for voltage conversion processing of acquired data to adapt to the transmission requirements of specific transmission protocols. The operational amplifier circuit amplifies and isolates the speed signal to ensure continuous data transmission. The first and second anti-interference circuits are suitable for improving the stability and security of signal transmission, avoiding external electromagnetic interference from affecting normal signal transmission, and also avoiding sending excessive noise interference to the outside world to avoid affecting the normal operation of other systems or devices. The transient suppression diode TVSA1 is suitable for quickly guiding excessively high voltages to the ground or power line, eliminating the effects of sudden or instantaneous overvoltages, avoiding damage to other components in the circuit by transient voltages, and making the circuit more stable. The hardware design circuits of this application, including the voltage conversion circuit, operational amplifier circuit, anti-interference circuit, and protection circuit, perform voltage conversion, signal amplification, and anti-interference processing on the speed input signal to achieve high-precision, low-noise speed signal transmission, thereby meeting the high-precision requirements of speed signal transmission for special equipment.

[0020] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0022] Figure 1 A partial circuit diagram of an analog signal transmission circuit according to an embodiment of this application is shown;

[0023] Figure 2 A partial circuit diagram of an analog signal transmission circuit according to an embodiment of this application is shown. Detailed Implementation

[0024] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0025] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model or simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0027] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0028] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0029] Figure 1 A partial circuit diagram of an analog signal transmission circuit according to an embodiment of this application is shown; Figure 2 A partial circuit diagram of an analog signal transmission circuit according to an embodiment of this application is shown. Figure 1As shown, this analog signal transmission circuit includes: a voltage conversion chip U8, an operational amplifier circuit, a first anti-interference circuit, a second anti-interference circuit, and a protection circuit; the input terminal of the voltage conversion chip U8 is suitable for receiving a speed signal, and the output terminal of the voltage conversion chip U8 is electrically connected to the input terminal of the operational amplifier circuit; the operational amplifier circuit includes: a first operational amplifier U7A and a second operational amplifier U7B; the non-inverting input terminal of the first operational amplifier U7A is electrically connected to the output terminal of the voltage conversion chip U8, and the output terminal of the first operational amplifier U7A is electrically connected to the non-inverting input terminal of the second operational amplifier U7B; the first anti-interference circuit includes: a first inductor TA5, a second inductor TA6, capacitors C56, C58, and C59; the output terminal of the second operational amplifier U7B is connected to capacitor C56. The first inductor TA5 is electrically connected to its input terminal, and the output terminal of the first inductor TA5 is electrically connected to the input terminal of the second inductor TA6 via capacitor C58. The second anti-interference circuit includes: a third inductor TA8, a fourth inductor TA7, capacitors C70, C71, C64, and C65. The output terminal of the second inductor TA6 is electrically connected to the input terminal of the third inductor TA8 via capacitors C59 and C70, and the output terminal of the third inductor TA8 is electrically connected to the input terminal of the fourth inductor TA7 via capacitors C71 and C64. The protection circuit includes: a transient suppression diode TVSA1. The output terminal of the fourth inductor TA7 is electrically connected to the transient suppression diode TVSA1 via capacitor C65. The fourth inductor TA7 is suitable for outputting a speed signal through the transient suppression diode TVSA1.

[0030] It should be noted here that the voltage conversion chip U8 is used to perform voltage conversion processing on the acquired data to adapt to the transmission requirements of specific transmission protocols. The operational amplifier circuit amplifies and isolates the speed signal to ensure continuous data transmission. The first and second anti-interference circuits are used to improve the stability and safety of signal transmission, avoiding external electromagnetic interference from affecting the normal transmission of the signal, and also avoiding sending excessive noise interference to the outside world to avoid affecting the normal operation of other systems or devices. The transient suppression diode TVSA1 is used to quickly guide excessively high voltages to the ground or power line, eliminating the effects of sudden or instantaneous overvoltages, avoiding damage to other components in the circuit by transient voltages, and making the circuit more stable. The hardware design circuits of this application, including the voltage conversion circuit, operational amplifier circuit, anti-interference circuit, and protection circuit, perform voltage conversion, signal amplification, and anti-interference processing on the speed input signal to achieve high-precision, low-noise speed signal transmission to meet the high-precision requirements of special equipment for speed signal transmission. The series connection of two operational amplifiers in the operational amplifier circuit further increases the stability of signal transmission.

[0031] Furthermore, pin 3 of voltage conversion chip U8 is connected to -15V voltage, pin 2 of voltage conversion chip U8 is connected to +15V operating voltage, pin 4 and pin 5 of voltage conversion chip U8 are connected to speed signal, and pin 1 of voltage conversion chip U8 is electrically connected to the non-inverting input terminal of the first operational amplifier U7A.

[0032] In one possible implementation, pin 4 of the voltage conversion chip is connected in series with resistors R18 and R16.

[0033] In one possible implementation, the output of the voltage conversion chip U8 is electrically connected to the non-inverting input of the first operational amplifier U7A via a filter circuit. For example... Figure 1 As shown, the filter circuit includes: resistor R21 and capacitor C60; one end of resistor R21 is electrically connected to pin 1 of voltage conversion chip U8, the other end of resistor R21 is electrically connected to the non-inverting input terminal of first operational amplifier U7A, one terminal of capacitor C60 is electrically connected to the circuit between resistor R21 and first operational amplifier U7A, and the other terminal of capacitor C60 is grounded.

[0034] In one possible implementation, one end of resistor R21 is electrically connected to pin 1 of voltage conversion chip U8 via a voltage divider resistor R23, and the other end of voltage divider resistor R23 is connected to ground.

[0035] Furthermore, the inverting input terminal (pin 2) of the first operational amplifier U7A is grounded through resistor R19, and the inverting input terminal (pin 2) of the first operational amplifier U7A is electrically connected to the output terminal (pin 1) of the first operational amplifier U7A through resistor R17. Pin 8 of the first operational amplifier U7A is connected to a +15V voltage, and pin 4 of the first operational amplifier U7A is connected to a -15V voltage.

[0036] In one possible implementation, the non-inverting input (pin 5) of the second operational amplifier U7B is electrically connected to the output (pin 1) of the first operational amplifier U7A; the inverting input (pin 6) of the second operational amplifier U7B is electrically connected to the output (pin 7) of the second operational amplifier U7B.

[0037] In one possible implementation, the output terminal (pin 7) of the second operational amplifier U7B is connected to the input terminal of the first inductor TA5 via a filter circuit. Further, this filter circuit includes a resistor R20 and a capacitor C57 connected in series; one end of resistor R20 is electrically connected to the output terminal (pin 7) of the second operational amplifier U7B, and the other end of resistor R20 is electrically connected to the first inductor TA5; one terminal of capacitor C57 is electrically connected to the circuit between the output terminal of the second operational amplifier U7B and the first inductor TA5, and the other terminal of capacitor C57 is grounded.

[0038] In one possible implementation, it also includes: a voltage divider resistor R22, one end of which is electrically connected between the output terminal of the second operational amplifier U7B and the resistor R20, and the other end of which is grounded.

[0039] In one possible implementation, a sixth inductor H6 is also included, with one end of the sixth inductor electrically connected to one end of the resistor R20, and the other end of the sixth inductor H6 electrically connected to the input terminal of the first inductor TA5.

[0040] Furthermore, pin 1 of the first inductor TA5 is electrically connected to the sixth inductor H6; pin 4 of the first inductor TA5 is electrically connected to pin 1 of the second inductor TA6; pins 2 and 3 of the first inductor TA5 are grounded; pin 4 of the second inductor TA6 is electrically connected to pin 1 of the third inductor TA8; pins 2 and 3 of the second inductor TA6 are grounded; one terminal of capacitor C56 is electrically connected between the sixth inductor H6 and the first inductor TA5; the other terminal of capacitor C56 is grounded; one terminal of capacitor C58 is electrically connected between the first inductor TA5 and the second inductor TA6; the other terminal of capacitor C58 is grounded; one terminal of capacitor C59 is electrically connected between the second inductor TA6 and the third inductor TA8; the other terminal of capacitor C59 is grounded.

[0041] In one possible implementation, the first anti-interference circuit further includes a capacitor C55, one end of which is electrically connected between the sixth inductor H6 and the first inductor TA5, and the other end of which is grounded.

[0042] In one possible implementation, the output of the second inductor TA6 is electrically connected to the input of the third inductor TA8 via two filter circuits. One filter circuit includes a resistor R24 ​​and a capacitor C68 connected in series, and the other filter circuit includes a resistor R25 and a capacitor C69 connected in series. One end of resistor R24 ​​is electrically connected to pin 4 of the second inductor TA6, and the other end of resistor R24 ​​is electrically connected to resistor R25. One terminal of capacitor C68 is electrically connected to the circuit between resistors R24 and R25, and the other terminal of capacitor C68 is grounded. One end of resistor R25 is electrically connected to pin 1 of the third inductor TA8, and the other end of resistor R25 is connected to resistor R24. One terminal of capacitor C69 is electrically connected to the circuit between resistor R25 and pin 1 of the third inductor TA8, and the other terminal of capacitor C69 is grounded.

[0043] In one possible implementation, the second anti-interference circuit includes: a third inductor TA8, a fourth inductor TA7, capacitors C64, C65, C70, and C71; pin 1 of the third inductor TA8 is electrically connected to resistor R25, pin 4 of the third inductor TA8 is electrically connected to pin 1 of the fourth inductor TA7, and pins 2 and 3 of the third inductor TA8 are grounded; one terminal of capacitor C70 is electrically connected to the circuit between resistor R25 and pin 1 of the third inductor TA8, and the other terminal of capacitor C70 is grounded. One terminal of capacitor C71 is electrically connected to the circuit between pin 4 of the third inductor TA8 and pin 1 of the fourth inductor TA7, and the other terminal of capacitor C71 is grounded. Pin 1 of the fourth inductor TA7 is electrically connected to pin 4 of the third inductor TA8. Pin 4 of the fourth inductor TA7 is electrically connected to the non-inverting input of the third operational amplifier U9A. Pins 2 and 3 of the fourth inductor TA7 are grounded. One terminal of capacitor C64 is electrically connected in the circuit between pin 1 of the fourth inductor TA7 and pin 4 of the third inductor TA8, and the other terminal of capacitor C64 is grounded. One terminal of capacitor C65 is electrically connected in the circuit between pin 4 of the fourth inductor TA7 and the third operational amplifier U9A, and the other terminal of capacitor C65 is grounded.

[0044] The second anti-interference circuit also includes capacitors C62 and C63. One terminal of capacitor C62 is electrically connected between resistor R27 and pin 1 of the fourth inductor TA7, and the other terminal of capacitor C62 is grounded.

[0045] One terminal of capacitor C63 is electrically connected between the fourth inductor TA7 and the third operational amplifier U9A, and the other terminal of capacitor C63 is grounded. One terminal of capacitor C72 is electrically connected to pin 3 of the fourth inductor TA7, and the other terminal of capacitor C72 is grounded.

[0046] In one possible implementation, the output of the third inductor TA8 is electrically connected to the input of the fourth inductor TA7 via two filter circuits. One filter circuit includes a resistor R26 and a capacitor C66 connected in series, and the other filter circuit includes a resistor R27 and a capacitor C67 connected in series. One end of resistor R26 is electrically connected to pin 4 of the third inductor TA8, and the other end of resistor R26 is electrically connected to resistor R27. One terminal of capacitor C66 is electrically connected to the circuit between resistors R26 and R27, and the other terminal of capacitor C66 is grounded. One end of resistor R27 is electrically connected to pin 1 of the fourth inductor TA7, and the other end of resistor R27 is connected to resistor R26. One terminal of capacitor C67 is electrically connected to the circuit between resistor R27 and pin 1 of the fourth inductor TA7, and the other terminal of capacitor C67 is grounded.

[0047] In one possible implementation, the protection circuit further includes: a third operational amplifier U9A; the non-inverting input (pin 3) of the third operational amplifier U9A is electrically connected to the output of the fourth inductor TA7, and the output (pin 1) of the third operational amplifier U9A is electrically connected to pin 2 of the transient suppression diode TVSA1. The inverting input (pin 2) of the third operational amplifier U9A is electrically connected to its output (pin 1); pin 8 of the third operational amplifier U9A is connected to a +15V voltage; and pin 4 of the third operational amplifier U9A is connected to a -15V voltage. The third operational amplifier U9A can further improve the stability of signal transmission.

[0048] In one possible implementation, the protection circuit further includes a resistor R28, one end of which is electrically connected to the output terminal (pin 4) of the fourth inductor TA7, and the other end of which is electrically connected to the input terminal of the fifth inductor U10.

[0049] In one possible implementation, the protection circuit further includes a fifth inductor U10, with the output of the third operational amplifier U9A electrically connected to the transient suppression diode TVSA1 via the fifth inductor U10. Furthermore, pin 1 of the fifth inductor U10 is electrically connected to resistor R28 and the output of the third operational amplifier U9A, and pin 4 of the fifth inductor U10 is used to output signal OUT1_1 via the transient suppression diode TVSA1.

[0050] Furthermore, pin 2 of transient suppression diode TVSA1 is electrically connected to pin 4 of the fifth inductor U10, and pins 1 and 3 of transient suppression diode TVSA1 are grounded.

[0051] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An analog signal transmission circuit, characterized by comprising: include: Voltage conversion chip U8, operational amplifier circuit, first anti-interference circuit, second anti-interference circuit and protection circuit; The input terminal of the voltage conversion chip U8 is suitable for receiving speed signals, and the output terminal of the voltage conversion chip U8 is electrically connected to the input terminal of the operational amplifier circuit. The operational amplifier circuit includes: a first operational amplifier U7A and a second operational amplifier U7B; the non-inverting input terminal of the first operational amplifier U7A is electrically connected to the output terminal of the voltage conversion chip U8, and the output terminal of the first operational amplifier U7A is electrically connected to the non-inverting input terminal of the second operational amplifier U7B. The first anti-interference circuit includes: a first inductor TA5, a second inductor TA6, a capacitor C56, a capacitor C58, and a capacitor C59; the output terminal of the second operational amplifier U7B is electrically connected to the input terminal of the first inductor TA5 through the capacitor C56, and the output terminal of the first inductor TA5 is electrically connected to the input terminal of the second inductor TA6 through the capacitor C58. The second anti-interference circuit includes: a third inductor TA8, a fourth inductor TA7, capacitors C70, C71, C64, and C65; the output terminal of the second inductor TA6 is electrically connected to the input terminal of the third inductor TA8 through capacitors C59 and C70, and the output terminal of the third inductor TA8 is electrically connected to the input terminal of the fourth inductor TA7 through capacitors C71 and C64. The protection circuit includes: a transient suppression diode TVSA1; the output terminal of the fourth inductor TA7 is electrically connected to the transient suppression diode TVSA1 through a capacitor C65, and the fourth inductor TA7 is suitable for outputting a speed signal through the transient suppression diode TVSA1.

2. The analog signal transmission circuit according to claim 1, characterized by The output terminal of the voltage conversion chip U8 is electrically connected to the non-inverting input terminal of the first operational amplifier U7A through a filter circuit.

3. The analog signal transmission circuit according to claim 1, characterized by The output terminal of the second operational amplifier U7B is electrically connected to the input terminal of the first inductor TA5 through a filter circuit.

4. The analog signal transmission circuit according to claim 1, characterized in that, The output terminal of the second inductor TA6 is electrically connected to the input terminal of the third inductor TA8 through two filter circuits.

5. The analog signal transmission circuit according to claim 1, characterized in that, The output terminal of the third inductor TA8 is electrically connected to the input terminal of the fourth inductor TA7 through two filter circuits.

6. The analog signal transmission circuit according to any one of claims 2-5, characterized in that, The filter circuit includes a resistor and a capacitor connected in series.

7. The analog signal transmission circuit of claim 1, wherein The protection circuit also includes: a third operational amplifier U9A; The non-inverting input terminal of the third operational amplifier U9A is electrically connected to the output terminal of the fourth inductor TA7, and the output terminal of the third operational amplifier U9A is electrically connected to the transient suppression diode TVSA1.

8. The analog signal transmission circuit according to claim 7, characterized by The protection circuit further includes a fifth inductor U10, and the output terminal of the third operational amplifier U9A is electrically connected to the transient suppression diode TVSA1 through the fifth inductor U10.

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