System-level test circuit of chip and electronic equipment

Abstract

The embodiment of the utility model discloses a system-level test circuit of a chip and electronic equipment, and relates to the field of integrated circuit testing. The specific amplifier chip and the analog-to-digital conversion chip are adopted to construct the test circuit, use of an expensive special programmable instrument is avoided, and the purchase and maintenance cost of test equipment is remarkably reduced. The circuit design is simplified, so that the cost of the whole test system is more controllable, and the whole competitiveness of the product is improved. The design of the current and voltage conversion unit and the result measurement unit is relatively simple and clear, and the requirements for professional skills and knowledge reserve of test engineers are reduced. The test process is simplified, the operation steps are reduced, and the test efficiency is improved.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit testing, and in particular to a system-level test circuit and electronic device for a chip. Background Technology

[0002] In the integrated circuit (IC) industry, system-level testing of chips is a crucial step in ensuring that products function properly and meet quality standards. System-level testing aims to simulate the operating conditions of chips in real-world application environments, comprehensively verifying key indicators such as performance, power consumption, stability, and reliability. Among these, the accurate measurement of electrical parameters such as voltage and current is one of the important indicators for evaluating chip performance, directly affecting whether the chip can meet design requirements and its performance in end products.

[0003] Traditionally, system-level testing of chips relies on dedicated programmable instruments to measure parameters such as voltage and current. These instruments typically possess high precision, high resolution, and good programmability, meeting the needs of complex testing scenarios. However, with the rapid development of integrated circuit technology and the increasing complexity of chip design, the requirements for testing equipment are also rising, posing numerous challenges to existing testing methods and technologies.

[0004] Dedicated programmable instruments are expensive, requiring significant investment from chip design companies or test service providers in purchasing and maintaining them, increasing testing costs and consequently impacting the overall competitiveness of their products. The operation and use of programmable instruments are relatively complex, demanding high levels of expertise and knowledge from test engineers. This not only increases the cost and time of personnel training but may also compromise the accuracy of test results due to improper operation. Utility Model Content

[0005] This application provides a system-level test circuit and electronic equipment for chips, which can solve the problems of high cost and complex operation in system-level chip testing. The technical solution is as follows:

[0006] In a first aspect, embodiments of this application provide a RAM multiplexing circuit, including:

[0007] Current-to-voltage conversion unit and result measurement unit;

[0008] The current-to-voltage conversion unit includes: an amplifier chip, a sampling resistor, an input filter circuit, a gain setting circuit, and a power supply filter circuit.

[0009] The amplifier chip is model AD620, and the amplifier chip is provided with a first gain setting pin, a second gain setting pin, a positive input pin, a negative input pin, a power supply pin, a ground pin, an output pin, a reference pin, and an output pin.

[0010] The first end of the sampling resistor is connected to the power supply pin of the chip under test, and the second end of the sampling resistor is connected to the positive terminal of the power supply circuit.

[0011] The first end of the sampling resistor is connected to the first input terminal of the input filter circuit, and the second end of the sampling resistor is connected to the second input terminal of the input filter circuit.

[0012] The first output terminal of the input filter circuit is connected to the negative input pin of the amplifier chip, and the second output terminal of the input filter circuit is connected to the positive input pin of the amplifier chip.

[0013] The first gain setting pin and the second gain setting pin of the amplifier chip are connected to the gain setting circuit.

[0014] The power supply pin of the amplifier chip is connected to the positive terminal of the first DC power supply through a power supply filter circuit.

[0015] The output pin of the amplifier chip is connected to one of the analog input pins of the analog-to-digital converter chip;

[0016] The amplifier chip's ground pin and reference pin are grounded;

[0017] The result measurement unit includes an analog-to-digital converter chip, wherein the model of the analog-to-digital converter chip is AD7091R-8;

[0018] The first analog input pin of the analog-to-digital converter chip is connected to the output pin of the amplifier chip. The analog-to-digital converter chip is used to convert the analog voltage signal from the current-to-voltage conversion unit into a digital voltage signal, and to provide the converted digital voltage signal to the main control chip to measure the operating voltage and operating current of the chip under test.

[0019] Secondly, this application provides an electronic device including the aforementioned system-level test circuit.

[0020] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:

[0021] This approach allows the CPU to dynamically access and reuse RAM resources when functional modules are not in operation. This significantly improves overall memory utilization, especially when there are multiple functional modules in the system that are not always running at full load.

[0022] By reducing memory access conflicts and latency, this solution optimizes data transfer paths, thereby improving overall system performance. The CPU can utilize available memory resources more efficiently, thus accelerating data processing.

[0023] The dynamic connection characteristics of the switching circuit allow the CPU to flexibly access different RAM resources as needed. This flexibility not only improves the system's scalability but also facilitates future system upgrades and functional expansions.

[0024] When a functional module is not in operation, its RAM resources can be reused by the CPU, thereby reducing power consumption caused by idle memory. This is especially important for embedded systems that pursue low power consumption and high efficiency.

[0025] By integrating switching circuits and dynamic connection mechanisms, this solution simplifies the complexity of system design. Designers no longer need to design memory access logic separately for each functional module; instead, they can rely on the switching circuits to automatically manage the allocation and reuse of memory resources.

[0026] The dynamic connection mechanism of the switching circuit helps avoid data conflicts and memory access errors, thereby improving the stability and reliability of the system. When a functional module is operating, its RAM resources are exclusively accessed, ensuring data integrity and consistency. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the current-to-voltage conversion unit provided in the embodiments of this application;

[0029] Figure 2 This is a structural diagram of the power supply circuit provided in the embodiments of this application;

[0030] Figure 3 This is a schematic diagram of the structure of the result measurement unit provided in the embodiment of this application. Detailed Implementation

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0032] Please see Figure 1 , Figure 2 and Figure 3The diagram shown is a schematic of the structure of a system-level test circuit for a chip according to an embodiment of this utility model.

[0033] exist Figure 1 The current-to-voltage conversion unit includes: an amplifier chip U15, a sampling resistor R107, an input filter circuit, a gain setting circuit, and a power supply filter circuit. The sampling resistor R107 is used to step down the DC voltage signal output from the power supply circuit to provide the operating voltage signal for the chip under test. The amplifier chip U15 amplifies the voltage signal across the sampling resistor R107. The input filter circuit filters the voltage signal across the sampling resistor R107, suppressing AC components. The gain setting circuit sets the amplification factor of the amplifier chip U15, and the power supply filter circuit filters the DC voltage signal from the external first DC power supply, suppressing AC components, and then provides the operating voltage signal for the amplifier chip U15.

[0034] The amplifier chip U15 is model AD620. The amplifier chip has a first gain setting pin RG1, a second gain setting pin RG2, a positive input pin IN+, a negative input pin IN-, a power supply pin VDD, a ground pin GND, a reference pin REF, and an output pin OUT.

[0035] The first gain setting pin RG1 and the second gain pin RG2 are used to set the amplification factor of the amplifier chip U15. The amplification factor is determined by the resistance value between the first gain pin RG1 and the second gain pin RG2. The formula for calculating the gain is: G = 49.4KΩ / Rg, where Rg represents the resistance value across the first gain pin RG1 and the second gain pin RG2.

[0036] The positive input pin IN+ is the non-inverting input, used to receive the positive input from the differential input signal. The negative input pin IN- is the inverting input, used to receive the negative input from the differential input signal.

[0037] The reference pin REF is used to set the reference level of the output signal, and is typically grounded or connected to a reference voltage.

[0038] The output pin OUT is used to output the amplified signal. The output signal Vout = (V IN+ -V IN- )×G+V REF .

[0039] The connection relationships of the various components in the current-to-voltage conversion unit are as follows:

[0040] The first terminal of sampling resistor R107 is connected to the power supply pin DUT_MARS_3V3 of the chip under test (DUT), and the second terminal of sampling resistor R107 is connected to the positive terminal DUT_3V3 of the power supply circuit. The chip under test is not shown in the diagram; it represents the chip to be tested. The chip under test can be a chip that supports the WiFi protocol.

[0041] The first terminal of the sampling resistor R107 is connected to the first input terminal of the input filter circuit, and the second terminal of the sampling resistor R107 is connected to the second input terminal of the input filter circuit. The first output terminal of the input filter circuit is connected to the negative input pin IN- of the amplifier chip, and the second output terminal of the input filter circuit is connected to the positive input pin IN+ of the amplifier chip.

[0042] The first gain setting pin RG1 and the second gain setting pin RG2 of amplifier chip U15 are connected to the gain setting circuit.

[0043] The power supply pin VDD of amplifier chip U15 is connected to the positive terminal VCC5V of the first DC power supply through a power supply filter circuit.

[0044] The output pin OUT of amplifier chip U15 is connected to an analog input pin VIN1 of analog-to-digital converter chip U14;

[0045] The ground pin GND and the reference pin REF of amplifier chip U15 are grounded.

[0046] The operation of the current-to-voltage conversion unit includes:

[0047] The sampling resistor R107 steps down the DC voltage signal output from the power supply circuit (from DUT_3V3) to serve as the operating voltage signal for the chip under test (not shown). This means the operating voltage of the chip under test is obtained from DUT_3V3 through R107. The voltage signal across the sampling resistor R107 represents the voltage drop caused by the current flowing through the chip under test. These voltage signals are input to the input filter circuit. The input filter circuit filters the voltage signal across the sampling resistor R107 to suppress AC components, ensuring that the signal input to the amplifier chip U15 is a relatively clean DC signal or low-frequency signal. The filtered signal is sent to the positive input pin IN+ and the negative input pin IN- of the amplifier chip U15. U15 is an AD620 amplifier that amplifies these differential input signals. The amplification factor of the amplifier chip U15 is determined by the resistance value between the first gain setting pin RG1 and the second gain setting pin RG2. The gain setting circuit is connected to the RG1 and RG2 pins of the amplifier chip U15 to set the desired amplification factor. The power supply pin VDD of amplifier chip U15 is connected to the positive terminal VCC5V of the first DC power supply through a power supply filter circuit. The power supply filter circuit suppresses AC components in VCC5V, ensuring a stable DC operating voltage for U15. Amplifier chip U15 outputs an amplified signal based on the input signal and the set gain. The output pin OUT of amplifier chip U15 is connected to an analog input pin VIN1 of analog-to-digital converter chip U14, meaning the amplified signal will be further converted into a digital signal for subsequent processing or analysis. The ground pin GND and reference pin REF of amplifier chip U15 are grounded, ensuring stable circuit operation and a correct signal reference level.

[0048] In summary, the current-to-voltage conversion unit obtains the voltage drop of the chip under test during operation through a sampling resistor. After filtering and amplification, the signal is converted into a form suitable for analog-to-digital conversion, so that the signal can be digitally processed and analyzed subsequently.

[0049] See Figure 3As shown, the result measurement unit includes an analog-to-digital converter chip U14 and peripheral circuitry. The specific structure of the peripheral circuitry is not detailed here. The analog-to-digital converter chip is model AD7091R-8, and includes a chip select input pin CS, a reset pin RESET, a power input pin VDD, a decoupling capacitor pin REGCAP, a reference voltage input / output pin REF, a ground pin GND, a multiplexer output pin MUXOUT, first analog input pins to eighth analog input pins VIN0 to VIN7, a multi-function pin GPO0, a general-purpose output pin GPO1, an ADC input pin ADCIN, a serial data input pin SDI, a serial data output pin SDO, a serial clock pin SCLK, a conversion start pin CONVST, and a logic power input pin VDRIVE. The main control chip can be a microcontroller.

[0050] The first analog input pin VIN1 of the analog-to-digital converter chip is connected to the output pin OUT of the amplifier chip U15. The analog-to-digital converter chip is used to convert the analog voltage signal from the current-to-voltage conversion unit into a digital voltage signal. The converted digital voltage signal is then provided to the main control chip to measure the operating voltage and operating current of the chip under test.

[0051] Specifically, the first analog input pin VIN1 of the analog-to-digital converter chip U14 is connected to the output pin OUT of the amplifier chip U15. This means that the analog voltage signal output by the amplifier chip U15 is transmitted to the VIN1 pin of the analog-to-digital converter chip U14 as the input signal to be converted. Here, VIN1 is one of multiple analog input pins of the analog-to-digital converter chip; different analog input pins can be selected to receive signals according to actual application requirements.

[0052] The main task of the analog-to-digital converter chip U14 is to convert the analog voltage signal from the current-to-voltage conversion unit into a digital voltage signal. This process is achieved through the chip's internal analog-to-digital converter (ADC). When the analog voltage signal is input to the VIN1 pin, the ADC samples, quantizes, and encodes the signal, ultimately outputting a corresponding digital voltage signal.

[0053] In addition to the first analog input pin VIN1, the analog-to-digital converter chip U14 is equipped with a chip select input pin CS, a reset pin RESET, a power input pin VDD, a decoupling capacitor pin REGCAP, a reference voltage input / output pin REF, and a ground pin GND. These pins are used to implement the chip's basic functions such as control, configuration, and power supply. Additionally, there are multiplexer output pins MUXOUT, GPO0 (multi-function pin), and GPO1 (general-purpose output pin), which provide extra flexibility and functional expandability. Serial data input pins SDI, SDO, and SCLK are used for data communication between the chip and external devices.

[0054] During the conversion process, once the CONVST pin receives the start signal, the analog-to-digital converter chip U14 begins converting the signal under test. After conversion, the digital voltage signal is output through the serial data output pin SDO for subsequent reading and processing by the main control chip.

[0055] After receiving the digital voltage signal, the main control chip performs further analysis and calculations to measure the operating voltage and current of the chip under test. In this way, the measurement unit converts analog signals into digital signals, providing accurate data support for subsequent measurements and analysis.

[0056] In summary, the result measurement unit, through the cooperation of the analog-to-digital converter chip U14 and its peripheral circuits, realizes the function of converting analog voltage signals into digital voltage signals, providing a reliable technical means for measuring the operating voltage and operating current of the chip under test.

[0057] See Figure 1 As shown, in some embodiments of this application, the input filtering circuit includes: a first capacitor C111, a second capacitor C112, a first resistor R106, and a second resistor R108.

[0058] Wherein, the first terminal of the first capacitor C111 is connected to the first terminal of the sampling resistor R107, and the second terminal of the first capacitor C111 is connected to the second terminal of the sampling resistor R107.

[0059] The first end of the first resistor R106 is connected to the first end of the first capacitor C111, and the second end of the first resistor R106 is connected to the first end of the second capacitor C112.

[0060] The first end of the second resistor R108 is connected to the second end of the first capacitor C111, and the second end of the second resistor R108 is connected to the second end of the second capacitor C112.

[0061] The first end of the second capacitor C112 is connected to the negative input pin of the amplifier chip U15, and the second end of the second capacitor C112 is connected to the positive input pin of the amplifier chip U15.

[0062] The working principle of the input filter circuit includes:

[0063] The first capacitor C111 is connected in parallel with the sampling resistor R107. This connection allows C111 to respond to changes in the current flowing through R107, thus performing preliminary filtering of the input signal. Capacitors have the characteristic of "passing AC and blocking DC," therefore C111 can effectively filter out high-frequency noise components in the input signal.

[0064] One end of the first resistor R106 is connected to the first terminal of the first capacitor C111, and the other end is connected to the first terminal of the second capacitor C112. Similarly, one end of the second resistor R108 is connected to the second terminal of the first capacitor C111, and the other end is connected to the second terminal of the second capacitor C112. This series and parallel combination of resistors and capacitors constitutes an RC filter network, which further filters the input signal. The RC filter network can attenuate signals within a specific frequency range, and the specific frequency range attenuated depends on the values ​​of the resistors and capacitors.

[0065] The first terminal of the second capacitor C112 is connected to the negative input pin of the amplifier chip U15, and the second terminal is connected to the positive input pin of U15. This connection method allows the filtered signal to be transmitted to the amplifier chip U15 for subsequent amplification and processing. Since the input signal has already been filtered, the signal transmitted to U15 is cleaner, which helps to improve the performance and stability of the entire circuit.

[0066] See Figure 1 As shown, in some embodiments of this application, the gain setting circuit includes: a third resistor R100, a fourth resistor R102, and a fifth resistor R105; the resistance of the third resistor R100 is infinite, the resistance of the fourth resistor R102 is 49.9 ohms, and the resistance of the fifth resistor R105 is 1K ohms.

[0067] Specifically, the resistance of the third resistor R100 is infinite, which means that in the circuit, R100 is actually equivalent to an open circuit and has no effect on the circuit (under ideal conditions). Therefore, R100 is not involved in the actual parallel resistance calculation during the gain setting process.

[0068] The fourth resistor, R102, has a resistance of 49.9 ohms, and the fifth resistor, R105, has a resistance of 1K ohms (i.e., 1000 ohms). These two resistors are key components in the gain setting circuit, and their resistance values ​​determine the adjustable range of the amplifier gain.

[0069] Users can select at least two resistors to be connected in parallel using a switch. The total resistance of the parallel resistors can be calculated using the parallel resistor formula: 1 / Rtotal = 1 / R1 + 1 / R2 + ... + 1 / Rn (where R1, R2, ..., Rn are the parallel resistance values). In this gain setting circuit, users can choose to connect R102 and R105 in parallel, or select only one of the resistors (in practice, since R100 has an infinite resistance, it is not usually selected alone).

[0070] When the user chooses to connect R102 and R105 in parallel, the total resistance of the bridging resistor will be less than the resistance of either resistor alone; the specific value depends on the result of the parallel connection formula. This total resistance will affect the gain characteristics of the amplifier chip U15. Generally speaking, the smaller the value of the bridging resistor, the higher the amplifier gain may be (the specific relationship also depends on the amplifier's internal circuit design and gain control mechanism).

[0071] Therefore, by selecting different combinations of resistors in parallel using a switch, users can flexibly adjust the gain settings of the amplifier chip U15 to meet different application requirements.

[0072] See Figure 1 As shown, in some embodiments of this application, the power supply filtering circuit includes: a third capacitor C113, a fourth capacitor C114, and a fifth capacitor C115.

[0073] Among them, the first terminals of the third capacitor C113, the fourth capacitor C114 and the fifth capacitor C115 are respectively connected to the power supply pin VDD of the amplifier chip U15.

[0074] The positive terminal VCC5V of the first DC power supply is connected to the power supply pin VDD of the amplifier chip U15.

[0075] The second terminals of the third capacitor C113, the fourth capacitor C114, and the fifth capacitor C115 are respectively grounded.

[0076] Specifically, the first terminals of the third capacitor C113, the fourth capacitor C114, and the fifth capacitor C115 are all connected to the power supply pin VDD of the amplifier chip U15. That is, these three capacitors are directly connected in parallel to the power supply pin of U15 to provide the filtered power signal to U15.

[0077] The positive terminal VCC5V of the first DC power supply is connected to the power supply pin VDD of the amplifier chip U15. This is the input terminal of the power supply filter circuit. The DC power signal provided by VCC5V will be filtered by the capacitor and then supplied to U15.

[0078] The second terminals of the third capacitor C113, the fourth capacitor C114, and the fifth capacitor C115 are grounded. This grounding connection allows the capacitors to form a low-impedance loop, providing a low-impedance path to ground for high-frequency noise and fluctuations in the power supply, thereby effectively bypassing these noises and fluctuations.

[0079] Specifically, the role of a capacitor in a power supply filtering circuit is to "pass AC and block DC" (AC mainly refers to high-frequency noise and fluctuations in the power supply, not actual AC signals). When high-frequency noise or fluctuations exist in the power supply signal, these noises and fluctuations will flow to ground through the capacitor and will not be transmitted to the power supply pins of the amplifier chip U15. In this way, the capacitor acts as a filter, making the power supply signal provided to U15 more stable and cleaner.

[0080] In summary, this power supply filtering circuit effectively filters out high-frequency noise and fluctuations in the power signal by connecting multiple capacitors in parallel on the power supply pins of the amplifier chip U15 and grounding them, providing a stable and clean power supply environment for U15.

[0081] See Figure 2 and Figure 3 As shown, in some embodiments of this application, the power supply circuit includes:

[0082] The following components are included: sixth capacitor C69, seventh capacitor C70, eighth capacitor C71, ninth capacitor C74, tenth capacitor C75, eleventh capacitor C76, sixth resistor R49, seventh resistor R43, eighth resistor R40, light-emitting diode D4, and power management chip U11. The power management chip model is TPS2553DBVR.

[0083] Among them, the first terminals of the sixth capacitor C69, the seventh capacitor C70, and the eighth capacitor C71 are connected to the positive terminal VCC33 of the second DC power supply; the second terminals of the sixth capacitor C69, the seventh capacitor C70, and the eighth capacitor C71 are grounded.

[0084] The voltage input pin IN of the power management chip U11 is connected to the first end of the eighth capacitor C71, and the ground pin of the power management chip U11 is grounded.

[0085] The first end of the sixth resistor R49 is connected to the positive terminal VCC33 of the second DC power supply, and the second end of the sixth resistor R49 is connected to an analog input pin VIN4 of the analog-to-digital converter chip U14 and the fault indication pin FAULT of the power management chip U11.

[0086] The current limiting pin ILIM of the power management chip U11 is grounded through the seventh resistor R43;

[0087] The voltage output pin OUT of the power management chip U11 is connected to the first terminals of the ninth capacitor C74, the tenth capacitor C75, and the eleventh capacitor C76, respectively; the second terminals of the ninth capacitor C74, the tenth capacitor C75, and the eleventh capacitor C76 are grounded.

[0088] The first terminal of the eleventh capacitor C76 is connected to the first terminal of the eighth resistor R40 and the second terminal of the sampling resistor R107, respectively.

[0089] The second end of the eighth resistor R40 is connected to the anode of the light-emitting diode D4, and the cathode of the light-emitting diode D4 is grounded.

[0090] Specifically, the first terminals of the sixth capacitor C69, the seventh capacitor C70, and the eighth capacitor C71 are connected to the positive terminal VCC33 of the second DC power supply, while their second terminals are grounded. These three capacitors form a power supply filter network to filter out high-frequency noise and fluctuations in the power supply, ensuring a more stable voltage signal supplied to the power management chip U11.

[0091] The voltage input pin IN of the power management chip U11 is connected to the first terminal of the eighth capacitor C71. Thus, the voltage signal filtered by the eighth capacitor C71 is input into U11. Simultaneously, the ground pin of U11 is connected to ground, ensuring the chip's normal operating ground potential.

[0092] The first terminal of the sixth resistor R49 is connected to the positive terminal VCC33 of the second DC power supply, and its second terminal is connected to an analog input pin VIN4 of the analog-to-digital converter chip U14 and the fault indicator pin FAULT of the power management chip U11. The sixth resistor R49 is used for current limiting or as part of fault detection. When the power management chip U11 malfunctions, the fault signal can be transmitted to the analog-to-digital converter chip U14 for further processing through the FAULT pin and the sixth resistor R49.

[0093] The current limit pin ILIM of the power management chip U11 is grounded through the seventh resistor R43. The seventh resistor R43 works with the internal current limit circuit of U11 to set or adjust the output current limit value to prevent overcurrent.

[0094] The voltage output pin OUT of the power management chip U11 is connected to the first terminals of the ninth capacitor C74, the tenth capacitor C75, and the eleventh capacitor C76, respectively. These three capacitors form an output filter network to further filter out noise and fluctuations in the output voltage, ensuring a more stable and cleaner voltage signal supplied to the load.

[0095] The first terminal of the eleventh capacitor C76 is also connected to the first terminal of the eighth resistor R40 and the second terminal of the sampling resistor R107. The eighth resistor R40 and the LED D4 are connected in series to form a simple indicator circuit. When the power management chip U11 is working normally, the output voltage drives the LED D4 to light up through the eighth resistor R40, indicating the normal working status of the power supply circuit.

[0096] In summary, this power supply circuit, through the collaborative efforts of the power management chip U11 and its peripheral components such as capacitors and resistors, achieves functions such as filtering, voltage regulation, current limiting, and fault indication of the power signal, providing a stable and reliable power output for the load.

[0097] The embodiments of this application have the following technical effects:

[0098] By using specific amplifier chips (such as AD620) and analog-to-digital converter chips (such as AD7091R-8) to construct the test circuit, the use of expensive dedicated programmable instruments is avoided, significantly reducing the procurement and maintenance costs of test equipment. The simplified circuit design makes the overall cost of the test system more controllable, improving the overall competitiveness of the product.

[0099] The design of the current-to-voltage conversion unit and the result measurement unit is relatively simple and straightforward, reducing the requirements for the professional skills and knowledge of test engineers. This simplifies the testing process, reduces operational steps, and improves testing efficiency.

[0100] The amplifier and analog-to-digital converter chips were selected based on their high precision and high resolution, ensuring the accuracy of the test results. The current-to-voltage conversion unit, through the coordinated operation of components such as sampling resistors, input filtering circuits, and gain setting circuits, accurately converts and amplifies the current signal. The result measurement unit converts the analog voltage signal into a digital voltage signal, facilitating subsequent processing and analysis by the main control chip, further improving the accuracy and reliability of the test.

[0101] This application also provides an electronic device, including the system-level test circuit of the chip described above. The electronic device can be various test equipment.

[0102] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A system-level test circuit for a chip, characterized in that, include: Current-to-voltage conversion unit and result measurement unit; The current-to-voltage conversion unit includes: an amplifier chip, a sampling resistor, an input filter circuit, a gain setting circuit, and a power supply filter circuit. The amplifier chip is model AD620, and the amplifier chip is provided with a first gain setting pin, a second gain setting pin, a positive input pin, a negative input pin, a power supply pin, a ground pin, an output pin, a reference pin, and an output pin. The first end of the sampling resistor is connected to the power supply pin of the chip under test, and the second end of the sampling resistor is connected to the positive terminal of the power supply circuit. The first end of the sampling resistor is connected to the first input terminal of the input filter circuit, and the second end of the sampling resistor is connected to the second input terminal of the input filter circuit. The first output terminal of the input filter circuit is connected to the negative input pin of the amplifier chip, and the second output terminal of the input filter circuit is connected to the positive input pin of the amplifier chip. The first gain setting pin and the second gain setting pin of the amplifier chip are connected to the gain setting circuit. The power supply pin of the amplifier chip is connected to the positive terminal of the first DC power supply through a power supply filter circuit. The output pin of the amplifier chip is connected to an analog input pin of the analog-to-digital converter chip; The amplifier chip's ground pin and reference pin are grounded; The result measurement unit includes an analog-to-digital converter chip, wherein the model of the analog-to-digital converter chip is AD7091R-8; The first analog input pin of the analog-to-digital converter chip is connected to the output pin of the amplifier chip. The analog-to-digital converter chip is used to convert the analog voltage signal from the current-to-voltage conversion unit into a digital voltage signal, and to provide the converted digital voltage signal to the main control chip to measure the operating voltage and operating current of the chip under test.

2. The circuit according to claim 1, characterized in that, The input filtering circuit includes: a first capacitor, a second capacitor, a first resistor, and a second resistor; Wherein, the first terminal of the first capacitor is connected to the first terminal of the sampling resistor, and the second terminal of the first capacitor is connected to the second terminal of the sampling resistor; The first end of the first resistor is connected to the first end of the first capacitor, and the second end of the first resistor is connected to the first end of the second capacitor. The first end of the second resistor is connected to the second end of the first capacitor, and the second end of the second resistor is connected to the second end of the second capacitor. The first end of the second capacitor is connected to the negative input pin of the amplifier chip, and the second end of the second capacitor is connected to the positive input pin of the amplifier chip.

3. The circuit according to claim 1 or 2, characterized in that, The gain setting circuit includes a third resistor, a fourth resistor, and a fifth resistor; the third resistor has an infinite resistance, the fourth resistor has a resistance of 49.9 ohms, and the fifth resistor has a resistance of 1K ohms.

4. The circuit according to claim 3, characterized in that, The power supply filtering circuit includes: a third capacitor, a fourth capacitor, and a fifth capacitor; The first terminals of the third capacitor, the fourth capacitor, and the fifth capacitor are respectively connected to the power supply pins of the amplifier chip. The positive terminal of the first DC power supply is connected to the power supply pin of the amplifier chip; The second terminals of the third capacitor, the fourth capacitor, and the fifth capacitor are respectively grounded.

5. The circuit according to claim 1, characterized in that, The power supply circuit includes: The sixth capacitor, the seventh capacitor, the eighth capacitor, the ninth capacitor, the tenth capacitor, the eleventh capacitor, the sixth resistor, the seventh resistor, the eighth resistor, the light-emitting diode, and the power management chip, wherein the power management chip is model TPS2553DBVR; The first terminals of the sixth, seventh, and eighth capacitors are connected to the positive terminal of the second DC power supply; the second terminals of the sixth, seventh, and eighth capacitors are grounded. The voltage input pin of the power management chip is connected to the first terminal of the eighth capacitor, and the ground pin of the power management chip is connected to the second terminal of the eighth capacitor. The first end of the sixth resistor is connected to the positive terminal of the second DC power supply, and the second end of the sixth resistor is connected to an analog input pin of the analog-to-digital converter chip and a fault indication pin of the power management chip, respectively. The current limiting pin of the power management chip is grounded through the seventh resistor; The voltage output pins of the power management chip are connected to the first terminals of the ninth, tenth, and eleventh capacitors, respectively; the second terminals of the ninth, tenth, and eleventh capacitors are grounded. The first terminal of the eleventh capacitor is connected to the first terminal of the eighth resistor and the second terminal of the sampling resistor, respectively. The second end of the eighth resistor is connected to the anode of the light-emitting diode, and the cathode of the light-emitting diode is grounded.

6. The circuit according to claim 5, characterized in that, The voltage of the first DC power supply is 5V, and the DC voltage output by the power supply circuit is 3.3V.

7. An electronic device, characterized in that, Includes the system-level test circuit as described in any one of claims 1 to 6.

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