1T2FC ferroelectric memory cell, memory array and AI chip
By using a 1T2FC ferroelectric memory cell structure, two reverse-polarized ferroelectric capacitors and a selection transistor, the limitations of existing ferroelectric memories in terms of area efficiency and signal margin are overcome, achieving high-density scalability and CMOS compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI SHENMING AOSI SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2025-07-31
- Publication Date
- 2026-05-05
AI Technical Summary
Existing ferroelectric memories have limitations in area efficiency and signal margin, making it difficult to meet the needs of in-memory computing.
A 1T2FC ferroelectric memory cell structure employing two reverse-polarized ferroelectric capacitors and one selection transistor is used to improve reliability and signal margin through differential sensing technology.
It improves the area efficiency and signal margin of memory cells, achieves high-density scalability, and is compatible with CMOS processes, suitable for 28nm and below nodes.
Smart Images
Figure CN224205520U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of in-memory computing memory technology, and in particular to a 1T2FC ferroelectric memory cell, a memory array, and an AI chip. Background Technology
[0002] Ferroelectric RAM (FRAM) is a new type of non-volatile memory (NVM) that can immediately capture and save critical data when power is interrupted. It is ideal for mission-critical data logging applications. Ferroelectric RAM adopts a low-power, miniaturized design and can provide instant non-volatility and almost unlimited endurance without affecting speed or energy efficiency.
[0003] Compute-in-Memory (CiM) is an architecture that integrates computing capabilities directly into a storage array, reducing energy consumption during data movement.
[0004] In-memory computing designs need to have a structure that features multi-bit storage, high durability, and simplified array operation. Figure 1 This diagram illustrates the ferroelectric field-effect transistor (FeFET) in existing technologies and its multi-bit capability in AI. Figure 1 In the image, (a) shows a FeFET device, and (b) shows the transfer characteristics of FeFET devices programmed with different voltage pulses, such as... Figure 1 As shown, by controlling the gate voltage (commonly referred to as the WL voltage, or Word Line voltage), FeFETs can have stable multi-level states, enabling the design of appropriate sensing circuits to sense current or threshold voltage to distinguish between various states in AI applications (in-memory computing). However, existing ferroelectric memories, primarily relying on the ferroelectric field-effect transistor (FeFET) architecture, suffer from significant limitations in area efficiency. Summary of the Invention
[0005] To address the shortcomings of existing technologies, this application aims to provide a 1T2FC ferroelectric memory cell, memory array, and AI chip, which employs two reverse-polarized ferroelectric capacitors (FeCAPs) and a selection transistor to improve area efficiency and signal margin.
[0006] To achieve the above objectives, this application provides a 1T2FC ferroelectric memory cell, comprising:
[0007] A silicon substrate, wherein an active device region is provided on the silicon substrate;
[0008] A gate stack structure is disposed on the active device region;
[0009] The source diffusion region is disposed on the active device region and located on one side of the gate stack structure;
[0010] The drain diffusion region is disposed on the active device region and located on the other side of the gate stack structure;
[0011] The first ferroelectric capacitor is disposed between the first plate line and the gate stack structure;
[0012] The second ferroelectric capacitor is disposed between the second plate line and the gate stack structure;
[0013] Word lines are electrically connected to the gate stack structure;
[0014] The source line is electrically connected to the source diffusion region;
[0015] The bit line is electrically connected to the drain diffusion region.
[0016] Furthermore, the first ferroelectric capacitor or the second ferroelectric capacitor receives a first polarization voltage through a plate line, causing its polarization direction to face the gate stack structure; or receives a second polarization voltage through a plate line, causing its polarization direction to face away from the gate stack structure.
[0017] The first polarization voltage has the opposite polarity to the second polarization voltage.
[0018] Furthermore, it also includes a shallow trench isolation region and an oxide located within the shallow trench isolation region; the shallow trench isolation region is arranged around the active device region.
[0019] Furthermore, the gate stack structure includes: a gate oxide layer, a high dielectric constant dielectric layer, and a TiN gate electrode; the gate oxide layer is disposed on the active device region; the high dielectric constant dielectric layer and the TiN gate electrode are sequentially stacked on the gate oxide layer.
[0020] Furthermore, each of the first ferroelectric capacitor and the second ferroelectric capacitor includes: a TiN bottom electrode, a ferroelectric dielectric layer, and a TiN top electrode; the TiN bottom electrode is electrically connected to the gate stack structure; the ferroelectric dielectric layer and the TiN top electrode are sequentially stacked on the TiN bottom electrode.
[0021] Furthermore, it also includes a bottom electrode disposed at one end of the ferroelectric capacitor; the bottom electrode is electrically connected to the gate stack structure.
[0022] Furthermore, it also includes an interlayer dielectric disposed on the source diffusion region and the drain diffusion region, wherein the interlayer dielectric has multiple contact holes and the multiple contact holes are filled with conductive metal.
[0023] Furthermore, the source line and the bit line are electrically connected to the source diffusion region and the drain diffusion region respectively through the conductive metal in the contact hole.
[0024] To achieve the above objectives, this application also provides a memory array including the 1T2FC ferroelectric memory cell as described above.
[0025] To achieve the above objectives, this application also provides an AI chip, including the memory array described above.
[0026] The 1T2FC ferroelectric memory cell provided in this application improves area efficiency and signal margin while maintaining compatibility with CMOS technology by employing two ferroelectric capacitors and one transistor; it allows each ferroelectric capacitor to be independently polarized, and can utilize differential sensing technology to improve reliability.
[0027] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description
[0028] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings:
[0029] Figure 1 A schematic diagram of ferroelectric field-effect transistors in existing technology and their multi-bit capabilities in AI;
[0030] Figure 2 This is a schematic diagram of the 1T2FC ferroelectric memory cell structure according to an embodiment of this application;
[0031] Figure 3 This is a top view of a 1T2FC ferroelectric memory cell according to an embodiment of this application;
[0032] Figure 4 This is a schematic diagram of a memory array structure according to an embodiment of this application.
[0033] Figure label:
[0034] 101-Silicon substrate; 102-Gate stack structure; 1021-Gate oxide layer; 1022-High dielectric constant (K) dielectric layer; 1023-TiN gate electrode; 103-Source diffusion region; 104-Drain diffusion region; 105-First ferroelectric capacitor; 106-Second ferroelectric capacitor; 107-Word line; 108-Source line; 109-Bit line; 110-First board line; 111-Second board line; 112-Active device region; 113-Shallow trench isolation region; 114-TiN bottom electrode; 115-Ferroelectric dielectric layer; 116-TiN top electrode; 117-Bottom electrode; 118-Ferroelectric contact hole; 119-Source contact hole; 120-Drain contact hole;
[0035] 201-1T2FC Ferroelectric memory cell; 202-Active device area; 203-Shallow trench isolation area; 204-Drain diffusion area. Detailed Implementation
[0036] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application.
[0037] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.
[0038] The term "comprising" and its variations as used herein are open-ended inclusion, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.
[0039] It should be noted that the terms "first" and "second" may be used in this application only to distinguish different devices, components or parts, and are not used to define the order of functions performed by these devices, components or parts or their interdependence.
[0040] It should be noted that the terms "one" and "more" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.
[0041] The following terms may be used in this application:
[0042] CFA: First Ferroelectric Capacitor;
[0043] CFB: Second ferroelectric capacitor;
[0044] Transistor: transistor;
[0045] PLA: First Plate Line;
[0046] PLB: Second Plate Line;
[0047] WL (Word Line): A word line is a wire that connects to the gate of a transistor and is used to control the transistor's on and off states.
[0048] BL (Bit Line): The wire connecting the drain of a transistor, used as a channel for data reading;
[0049] SL (Source Line): The source line is the wire connecting the source of a transistor. It serves as a current loop or voltage reference line and works in conjunction with the bit line to complete data read and write operations.
[0050] +Vpp: Positive polarization voltage;
[0051] -Vpp: Negative polarization voltage.
[0052] Definitions for other terms will be provided in the following description.
[0053] Example 1
[0054] In an embodiment of this application, a 1T2FC ferroelectric memory cell is provided, comprising: a silicon substrate, wherein an active device region is disposed on the silicon substrate; a gate stack structure disposed on the active device region; a source diffusion region disposed on the active device region and located on one side of the gate stack structure; a drain diffusion region disposed on the active device region and located on the other side of the gate stack structure; a first ferroelectric capacitor disposed between a first board line and the gate stack structure; a second ferroelectric capacitor disposed between a second board line and the gate stack structure; a word line electrically connected to the gate stack structure; a source line electrically connected to the source diffusion region; and a bit line electrically connected to the drain diffusion region.
[0055] Figure 2 This is a schematic diagram of the 1T2FC ferroelectric memory cell structure according to an embodiment of this application. Figure 3 This is a top view of a 1T2FC ferroelectric memory cell according to an embodiment of this application. The following will be combined with... Figure 2 and Figure 3 The 1T2FC ferroelectric memory cell of this application will be described in further detail.
[0056] The 1T2FC ferroelectric memory cell of this application embodiment includes: a silicon substrate 101; a gate stack structure 102, a source diffusion region 103, and a drain diffusion region 104 disposed on the silicon substrate 101, which respectively constitute the gate, source, and drain of a selection transistor for access control and current modulation in read and write operations; a first ferroelectric capacitor 105 (CFA) and a second ferroelectric capacitor 106 (CFB) symmetrically disposed on both sides of the gate stack structure 102 as ferroelectric memory elements for encoding binary information through polarization direction; a word line 107 (WL) electrically connected to the gate stack structure 102; a source line 108 (SL) electrically connected to the source diffusion region 103; and a bit line 109 (BL) electrically connected to the drain diffusion region 104.
[0057] One end of the first ferroelectric capacitor 105 is electrically connected to the gate stack structure 102, and the other end is connected to the first plate line 110 (PLA) for receiving polarization signals; one end of the second ferroelectric capacitor 106 is electrically connected to the gate stack structure 102, and the other end is connected to the second plate line 111 (PLB) for receiving polarization signals.
[0058] In the embodiments of this application, when a logic value is written to the 1T2FC ferroelectric memory cell, the first ferroelectric capacitor 105 receives a first polarization voltage through the first plate line 110, causing its polarization direction to face the gate stack structure 102; or receives a second polarization voltage through the first plate line 110, causing its polarization direction to face away from the gate stack structure 102. Simultaneously, the second ferroelectric capacitor 106 (CFB) receives a second polarization voltage through the second plate line 111, causing its polarization direction to face away from the gate stack structure 102; or receives a first polarization voltage through the second plate line 111, causing its polarization direction to face the gate stack structure 102. The first polarization voltage and the second polarization voltage have opposite polarities.
[0059] For example, when a logic "1" is written to the 1T2FC ferroelectric memory cell, the first ferroelectric capacitor 105 receives +Vpp (positive polarization voltage) through the first plate line 110, while the other end of the first ferroelectric capacitor 105 is grounded, so that the polarization vector of the first ferroelectric capacitor 105 is aligned in one direction, that is, its polarization direction is towards the gate stack structure 102; at the same time, the second ferroelectric capacitor 106 receives -Vpp (negative polarization voltage) through the second plate line 111, so that its polarization direction is opposite to that of the first ferroelectric capacitor 105, that is, away from the gate stack structure 102.
[0060] When a logic "0" is written to the 1T2FC ferroelectric memory cell, the polarity of the first ferroelectric capacitor 105 and the second ferroelectric capacitor 106 is reversed, that is:
[0061] The first ferroelectric capacitor 105 receives -Vpp through the first plate line 110, and the second ferroelectric capacitor 106 receives +Vpp through the second plate line 111, making the polarization states of the first ferroelectric capacitor 105 and the second ferroelectric capacitor 106 opposite to those when a logic "1" is written. The binary state is achieved by encoding the relative ferroelectric polarization of the two ferroelectric capacitors, ensuring non-volatile bistable switching. Independent ferroelectric polarization of each ferroelectric capacitor is allowed, and reliability is improved using differential sensing technology.
[0062] For example, when the 1T2FC ferroelectric memory cell reads data, the second ferroelectric capacitor 106 receives a small read voltage (Vread) through the second plate line 111, which is sufficient to generate a measurable current without interfering with the ferroelectric state.
[0063] The first ferroelectric capacitor 105 is grounded (0V) via the first plate line 110 to provide a reference potential;
[0064] Word line 107 is floating, so that the gate potential is completely determined by the net effect of the polarized ferroelectric capacitor, thereby realizing the gate-controlled channel conduction.
[0065] Bit line 109 receives the read voltage; then, based on the drain-to-source current, i.e., the drain current (Ids), it determines the logic state: high drain current (on state) indicates that the polarization configuration results in a low effective threshold voltage; low drain current (off state) indicates that the reverse polarization configuration results in a high threshold voltage.
[0066] In the embodiments of this application, the small read voltage refers to a voltage in the range of 0.2V-0.7V.
[0067] In the embodiments of this application, high drain current refers to the current from drain to source reaching a saturation value when the gate voltage of the selection transistor exceeds the threshold voltage, the channel is fully turned on. Low drain current refers to the current from drain to source dropping to an extremely low value when the gate voltage of the selection transistor is below the threshold voltage, the channel does not form a conductive path.
[0068] In the embodiments of this application, the logic state is determined by detecting the drain current of the selection transistor and based on the net polarization effect of the CFA and CFB on the gate potential. The logic state is determined as follows: a high drain current represents logic "1", and a low drain current represents logic "0".
[0069] In the embodiments of this application, the silicon substrate 101 is provided with an active device region 112, the gate stack structure 102 is disposed on the active device region 112, the source diffusion region 103 is disposed on one side of the gate stack structure 102 as the source of the selection transistor, and the drain diffusion region 104 is disposed on the other side of the gate stack structure 102 as the drain of the selection transistor.
[0070] In the embodiments of this application, both the source diffusion region 103 and the drain diffusion region 104 are N+ diffusion regions (representing highly doped N-type semiconductor regions).
[0071] In some other embodiments of the application, the silicon substrate 101 is further provided with a shallow trench isolation region 113 surrounding the active device region 112, the shallow trench isolation region 113 being filled with oxide to isolate the active device region 112 from other active device regions.
[0072] The gate stack structure 102 of this application embodiment includes, from bottom to top, a gate oxide layer 1021, a high dielectric constant (K) dielectric layer 1022, and a TiN gate electrode 1023. The gate oxide layer 1021 is disposed on the active device region 112, and the high dielectric constant dielectric layer 1022 and the TiN gate electrode 1023 are stacked and disposed on the gate oxide layer 1021.
[0073] Each of the first ferroelectric capacitor 105 and the second ferroelectric capacitor 106 in this embodiment includes, from bottom to top, a TiN bottom electrode 114, a ferroelectric dielectric layer 115, and a TiN top electrode 116. The TiN bottom electrode 114 is electrically connected to the TiN gate electrode 1023 of the gate stack structure 102.
[0074] In the embodiments of this application, the 1T2FC ferroelectric memory cell further includes a bottom electrode 117 disposed at the bottom of two ferroelectric capacitors, and a ferroelectric contact hole 118 for connecting the bottom electrode 117 and the TiN gate electrode 1023.
[0075] In the embodiments of this application, the 1T2FC ferroelectric memory cell further includes an interlayer dielectric (not shown in the figure) disposed on the source diffusion region 103 and the drain diffusion region 104. The interlayer dielectric has a source contact hole 119 and a drain contact hole 120. Both the source contact hole 119 and the drain contact hole 120 are filled with conductive metal. The source contact hole 119 is used to connect the source diffusion region 103 and the source line 108, and the drain contact hole 120 is used to connect the drain diffusion region 104 and the bit line 109.
[0076] The 1T2FC ferroelectric memory cell of this application improves area efficiency and signal margin through two ferroelectric capacitors and one selection transistor; it allows each ferroelectric capacitor to be independently polarized, and can utilize differential sensing technology to improve reliability; it has a footprint of 8F² (2F × 4F), ensuring high-density scalability and compatibility with 28nm, 22nm and more advanced nodes; its structure is fully compatible with CMOS back-end process integration and is suitable for nodes below 40nm.
[0077] Example 2
[0078] In the embodiments of this application, a memory array is also provided, including multiple 1T2FC ferroelectric memory cells as described in Embodiment 1, wherein the multiple 1T2FC ferroelectric memory cells perform in-memory computation operations in parallel.
[0079] Figure 4 This is a schematic diagram of a memory array structure according to an embodiment of this application, such as... Figure 4 As shown, the memory array in this embodiment includes a plurality of 1T2FC ferroelectric memory cells 201 as described above.
[0080] In the embodiments of this application, to further reduce the area of the memory array, every two 1T2FC ferroelectric memory cells 201 are arranged on the same active device region 202, and each active device region 202 is isolated by a shallow trench isolation region 203. The two 1T2FC ferroelectric memory cells 201 on the same active device region 202 share a drain diffusion region 204.
[0081] In the embodiments of this application, each 1T2FC ferroelectric memory cell 201 stores logic values through differential polarization between two ferroelectric capacitors, and improves the read margin and noise immunity of the memory array through differential current sensing.
[0082] In embodiments of this application, the memory array accesses selected rows by accepting multi-step voltage access to avoid interference with partially selected and unselected cells. Interference with unselected or partially selected cells is avoided by accepting appropriate Vpp and Vdd (voltages on the bit lines and source lines).
[0083] Furthermore, when the memory array in this application embodiment performs a write operation, it includes:
[0084] In the first stage, graded voltages (such as 2 / 3Vpp, 1 / 3Vpp) are accepted to reduce the stress on the half-selected and unselected cells;
[0085] In the second stage, complementary fractional voltage or full voltage is accepted to complete the polarization switching of the target cell.
[0086] Complementary graded voltage: This refers to the two complementary ferroelectric capacitors of the target unit receiving voltages with opposite polarities but different amplitudes, such as one ferroelectric capacitor receiving +0.6V and the other receiving -0.4V, achieving state switching through differential polarization.
[0087] Full voltage: refers to the maximum permissible voltage of 3Vpp, which is much higher than Vc, that the two complementary ferroelectric capacitors of the target memory cell accept with opposite polarities, forcing the ferroelectric domains to completely flip, thereby achieving state switching.
[0088] Example 3
[0089] In the embodiments of this application, an AI chip is also provided, including a memory array as described in Embodiment 2. AI chips employing this memory array significantly improve area efficiency and signal tolerance.
[0090] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A 1T2FC ferroelectric memory cell, characterized in that, include: A silicon substrate, wherein an active device region is provided on the silicon substrate; A gate stack structure is disposed on the active device region; The source diffusion region is disposed on the active device region and located on one side of the gate stack structure; The drain diffusion region is disposed on the active device region and located on the other side of the gate stack structure; The first ferroelectric capacitor is disposed between the first plate line and the gate stack structure; The second ferroelectric capacitor is disposed between the second plate line and the gate stack structure; Word lines are electrically connected to the gate stack structure; The source line is electrically connected to the source diffusion region; The bit line is electrically connected to the drain diffusion region.
2. The 1T2FC ferroelectric memory cell according to claim 1, characterized in that, The first ferroelectric capacitor or the second ferroelectric capacitor receives a first polarization voltage through a plate line, causing its polarization direction to face the gate stack structure; or receives a second polarization voltage through a plate line, causing its polarization direction to face away from the gate stack structure. The first polarization voltage has the opposite polarity to the second polarization voltage.
3. The 1T2FC ferroelectric memory unit according to claim 1, characterized in that, It also includes a shallow trench isolation region and oxides located within the shallow trench isolation region; the shallow trench isolation region is arranged around the active device region.
4. The 1T2FC ferroelectric memory cell according to claim 1, characterized in that, The gate stack structure includes: a gate oxide layer, a high dielectric constant dielectric layer, and a TiN gate electrode; the gate oxide layer is disposed on the active device region; the high dielectric constant dielectric layer and the TiN gate electrode are stacked sequentially on the gate oxide layer.
5. The 1T2FC ferroelectric memory cell according to claim 1, characterized in that, Each of the first ferroelectric capacitor and the second ferroelectric capacitor includes: a TiN bottom electrode, a ferroelectric dielectric layer, and a TiN top electrode; the TiN bottom electrode is electrically connected to the gate stack structure; the ferroelectric dielectric layer and the TiN top electrode are sequentially stacked on the TiN bottom electrode.
6. The 1T2FC ferroelectric memory cell according to claim 1, characterized in that, It also includes a bottom electrode disposed at one end of the ferroelectric capacitor; the bottom electrode is electrically connected to the gate stack structure.
7. The 1T2FC ferroelectric memory unit according to claim 1, characterized in that, It also includes an interlayer dielectric disposed on the source diffusion region and the drain diffusion region, wherein the interlayer dielectric has multiple contact holes and the multiple contact holes are filled with conductive metal.
8. The 1T2FC ferroelectric memory cell according to claim 7, characterized in that, The source line and the bit line are electrically connected to the source diffusion region and the drain diffusion region respectively through the conductive metal in the contact hole.
9. A memory array, characterized in that, It includes the 1T2FC ferroelectric memory cell as described in any one of claims 1-8.
10. An AI chip, characterized in that, Includes the memory array as described in claim 9.