Bonding-free Micro LED structure

Abstract

The utility model discloses a bonding-free Micro LED structure, which comprises a silicon substrate, an LED epitaxial layer growing on the front surface of the silicon substrate, a CMOS circuit layer growing on the back surface of the silicon substrate, and a first conductive through hole and a second conductive through hole which are arranged along the surface of the CMOS circuit layer towards the direction of the LED epitaxial layer and penetrate through the silicon substrate, and the CMOS circuit layer and the LED epitaxial layer are directly conducted and connected through the first conductive through hole and the second conductive through hole. According to the utility model, electrical interconnection is realized through double-sided integration and internal conduction, and a bonding step is not needed.

Description

Technical Field

[0001] This utility model relates to the field of LED manufacturing technology, and in particular to a bonding-free Micro LED structure. Background Technology

[0002] Currently, the manufacturing process of Micro LED devices typically involves the following steps: growing CMOS control circuits on a silicon substrate; growing LED epitaxial structures (such as N-type layers, quantum wells, and P-type layers) on a sapphire or gallium nitride (GaN) substrate, or further dicing them into individual wafer particles; and connecting the individual wafers or the CMOS circuits with the LED epitaxial structures through mass transfer bonding processes to form electrical interconnects.

[0003] Traditional manufacturing processes are complex, requiring the fabrication of CMOS and LED structures on different substrates, involving multiple bonding and electrode fabrication steps. These processes are costly, with high precision requirements for bonding, low yields, and high equipment costs. Furthermore, traditional manufacturing processes are prone to stress or thermal mismatch at the bonding interface due to bonding issues, leading to device performance degradation. Moreover, limitations in bonding processes and heat dissipation requirements restrict structural integration and hinder further reduction in pixel size. For example, the LED chip structure fabrication method and patent for LED chip structure (CN119677269A) suffer from thermal mismatch problems. While using substrates of the same material to bond alleviates differences in thermal expansion, it does not address the issue of interface stress accumulation when bonding dissimilar materials (such as GaN and Si). Similarly, the compensation alignment bonding method for an LED display panel (CN118763156A) faces precision bottlenecks, requiring additional photolithography alignment steps, increasing process complexity, and adding 2-3 photolithography masks. Referring to the patent CN119767918A, which describes an integrated microdisplay chip structure and fabrication method, and citing SEMI industry report data, the investment in bonding process equipment accounts for over 35% of the total cost. In summary, current technologies focus on optimizing bonding processes and have not broken through the bond-free integration technology route, resulting in limitations on pixel miniaturization; the minimum pixel size in existing technologies is ≥20μm. Utility Model Content

[0004] The technical problem to be solved by this utility model is to overcome the shortcomings of the prior art and provide a bonding-free Micro LED structure that achieves electrical interconnection through double-sided integration and internal conduction without the need for bonding steps.

[0005] To solve the above-mentioned technical problems, the technical solution of this utility model is as follows:

[0006] A bonding-free Micro LED structure includes a silicon substrate, an LED epitaxial layer grown on the front side of the silicon substrate, and a CMOS circuit layer grown on the back side of the silicon substrate. A first conductive via and a second conductive via are formed along the surface of the CMOS circuit layer toward the LED epitaxial layer, penetrating the silicon substrate. The first conductive via and the second conductive via directly connect the CMOS circuit layer and the LED epitaxial layer.

[0007] Furthermore, the LED epitaxial layer includes an N-type layer, a quantum well layer, and a P-type layer distributed from the outside to the inside, with the first conductive via extending to the N-type layer and the second conductive via extending to the P-type layer.

[0008] Furthermore, a passivation layer is also provided on the outside of the LED epitaxial layer.

[0009] Furthermore, the surface of the CMOS circuit layer is also provided with multiple light source electrodes.

[0010] Furthermore, the CMOS circuit layer also has several non-through-hole, internally conductive third conductive vias.

[0011] Furthermore, the inner walls of the first, second, and third conductive vias are electroplated with copper layers.

[0012] Furthermore, the diameters of the first conductive via, the second conductive via, and the third conductive via are 5 μm.

[0013] Furthermore, the CMOS circuit layer includes driving transistors, logic circuits, and interconnect metals.

[0014] By adopting the above technical solution, this utility model has the following beneficial effects:

[0015] 1. This invention grows a CMOS circuit layer and an LED epitaxial layer on both sides of a single silicon substrate, and then connects the CMOS circuit layer and the LED epitaxial layer through the first and second conductive vias to achieve electrical interconnection. Therefore, there is no need for bonding steps, which reduces the process flow, lowers manufacturing costs, avoids bonding interface stress, and improves device lifespan and stability.

[0016] 2. This utility model uses a double-sided integrated structure on a single silicon substrate, which can reduce the overall structural size while ensuring heat dissipation performance. The high integration can achieve smaller pixel size, making it suitable for high-resolution displays.

[0017] 3. This utility model omits the bonding step, reduces errors, improves the accuracy of structural integration, and increases production yield. Attached Figure Description

[0018] Figure 1This is a schematic diagram of the structure of this utility model;

[0019] Among them, 1. silicon substrate; 2. LED epitaxial layer; 21. N-type layer; 22. quantum well layer; 23. P-type layer; 3. CMOS circuit layer; 4. first conductive via; 5. second conductive via; 6. third conductive via; 7. passivation layer; 8. light source electrode. Detailed Implementation

[0020] To make the contents of this utility model easier to understand, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0021] like Figure 1 As shown, in this embodiment, a bond-free Micro LED structure is provided, which consists of a passivation layer 7, an LED epitaxial layer 2, a silicon substrate 1, and a CMOS circuit layer 3 from top to bottom. The passivation layer 7 covers the outside of the LED epitaxial layer 2, providing protection and optical optimization; its refractive index is between that of the LED material and air, n=1.8-2.2. The LED epitaxial layer 2 is grown on the front side of the silicon substrate 1, i.e., above the silicon substrate 1 in the figure, and the CMOS circuit layer 3 is grown on the back side of the silicon substrate 1, i.e., below the silicon substrate 1 in the figure.

[0022] To connect the CMOS circuit layer 3 to the LED epitaxial layer 2, a first conductive via 4 and a second conductive via 5 are formed along the surface of the CMOS circuit layer 3 towards the LED epitaxial layer 2, penetrating the silicon substrate 1. These vias are arranged from bottom to top in the figure. The first conductive via 4 and the second conductive via 5 directly connect the CMOS circuit layer 3 and the LED epitaxial layer 2, allowing the driving current generated by the CMOS circuit layer 3 to be smoothly conducted to the LED epitaxial layer 2. By establishing this electrical path, the necessary electrical energy input is provided for the normal operation of the LED device, driving the LED to emit light.

[0023] Specifically, in this embodiment, the LED epitaxial layer 2 includes an N-type layer 21, a quantum well layer 22, and a P-type layer 23 distributed from the outside in, i.e., distributed from top to bottom in the figure. The CMOS circuit layer 3 includes driving transistors, logic circuits, and interconnect metals. The first conductive via 4 extends to and connects to the N-type layer 21, i.e., one end is connected to the negative electrode of the N-type layer 21, and the other end is connected to the logic circuit; the second conductive via 5 extends to and connects to the P-type layer 23, i.e., one end is connected to the positive electrode of the P-type layer 23, and the other end is connected to the logic circuit.

[0024] Of course, this embodiment has more than just the first conductive via 4 and the second conductive via 5. In order to facilitate internal conduction, several non-penetrating third conductive vias 6 are also provided on the CMOS circuit layer 3, which can facilitate the connection of logic circuits inside the CMOS circuit layer 3, save space, and improve light efficiency.

[0025] It is worth mentioning that, in this embodiment, the inner walls of the first conductive through hole 4, the second conductive through hole 5, and the third conductive through hole 6 are electroplated with copper layers to achieve conductivity, and the diameters of the first conductive through hole 4, the second conductive through hole 5, and the third conductive through hole 6 are 5μm.

[0026] In addition, multiple light source electrodes 8 are provided on the surface of the CMOS circuit layer 3 in this embodiment, which can be connected to external circuit devices to facilitate power supply and transmission of control signals.

[0027] Through the above design, this embodiment uses a single silicon substrate 1 to grow a CMOS circuit layer 3 and an LED epitaxial layer 2 on both sides. The CMOS circuit layer 3 and the LED epitaxial layer 2 are then connected via an internal first conductive via 4 and a second conductive via 5, achieving electrical interconnection. Therefore, no bonding step is required, reducing the process flow, lowering manufacturing costs, and avoiding bonding interface stress, thus improving device lifespan and stability. Furthermore, the double-sided integrated structure on a single silicon substrate 1 allows for a reduction in overall structural size while ensuring heat dissipation performance. High integration allows for smaller pixel sizes, suitable for high-resolution displays. Simultaneously, omitting the bonding step reduces errors, improves the accuracy of structural integration, and increases production yield.

[0028] In this embodiment, the manufacturing process can be achieved through the following steps:

[0029] First, a high-resistivity silicon substrate with a resistivity >1000Ω·cm and a thickness of 200μm is used; this improves power efficiency and light efficiency.

[0030] Secondly, GaN-based LED epitaxial layers, including N-GaN layers, InGaN / GaN multiple quantum wells, and P-GaN layers, are grown on the front side of the high-resistivity silicon substrate via MOCVD. The MOCVD growth conditions are: pressure 200 mbar, NH3 flow rate 15 slm, and V / III ratio 2000.

[0031] Next, a driving circuit, including NMOS / PMOS transistors and metal interconnects, is fabricated on the back side of the high-resistivity silicon substrate using CMOS technology; Cu / TaN stack: Cu thickness 500nm, TaN thickness 50nm.

[0032] Then, DRIE technology is used to etch through-holes with a diameter of 5μm, and copper is filled to form conductive channels; TSV filling: copper electroplating + annealing, 450°C, H2 atmosphere environment.

[0033] Next, photolithography defines the pixel size as 8μm×8μm, and the LED epitaxial layer is etched onto the silicon substrate.

[0034] Finally, a SiO2 passivation layer is deposited to complete the encapsulation and improve luminescence efficiency.

[0035] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0036] The above specific embodiments further illustrate the technical problems, technical solutions, and beneficial effects of this utility model. It should be understood that the above descriptions are merely specific embodiments of this utility model and are not intended to limit this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A bonding-free Micro LED structure, characterized in that: The device includes a silicon substrate (1), an LED epitaxial layer (2) grown on the front side of the silicon substrate (1), and a CMOS circuit layer (3) grown on the back side of the silicon substrate (1). A first conductive via (4) and a second conductive via (5) are provided along the surface of the CMOS circuit layer (3) towards the LED epitaxial layer (2) and penetrate the silicon substrate (1). The first conductive via (4) and the second conductive via (5) directly connect the CMOS circuit layer (3) and the LED epitaxial layer (2).

2. The bonding-free Micro LED structure according to claim 1, characterized in that: The LED epitaxial layer (2) includes an N-type layer (21), a quantum well layer (22) and a P-type layer (23) distributed from the outside to the inside. The first conductive via (4) extends to the N-type layer (21) and the second conductive via (5) extends to the P-type layer (23).

3. The bonding-free Micro LED structure according to claim 1, characterized in that: The LED epitaxial layer (2) is further covered with a passivation layer (7).

4. The bonding-free Micro LED structure according to claim 1, characterized in that: The surface of the CMOS circuit layer (3) is also provided with multiple light source electrodes (8).

5. The bonding-free Micro LED structure according to claim 1, characterized in that: The CMOS circuit layer (3) also has several non-penetrating and internally conductive third conductive vias (6).

6. The bonding-free Micro LED structure according to claim 5, characterized in that: The inner walls of the first conductive through hole (4), the second conductive through hole (5) and the third conductive through hole (6) are filled with copper plating.

7. A bonding-free Micro LED structure according to claim 5, characterized in that: The diameters of the first conductive via (4), the second conductive via (5), and the third conductive via (6) are 5 μm.

8. The bonding-free Micro LED structure according to claim 1, characterized in that: The CMOS circuit layer (3) includes driving transistors, logic circuits, and interconnect metals.

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