Chip packaging structure and electronic equipment

Abstract

The utility model discloses a chip packaging structure and electronic equipment, the chip packaging structure comprises a plurality of first packaging bodies, a second substrate and a first reinforcing rib, each first packaging body comprises a first bare chip, a first substrate and a first packaging layer, the first bare chip is welded on the first substrate, the first bare chip is electrically connected with the first substrate, and the second substrate is electrically connected with the first packaging layer. The first packaging layer is located on the first substrate and wraps the side face of the first bare chip, the multiple first packaging bodies are welded to the second substrate, the first substrate is electrically connected with the second substrate, the first substrate is at least used for achieving electric connection between the first bare chip and the second substrate, and the second substrate is at least used for achieving electric connection between the first bare chip and the second substrate. The second substrate is at least used for realizing interconnection between the first packaging bodies and electric connection between the first packaging bodies and other devices, the first reinforcing ribs are fixed on the second substrate, and the first reinforcing ribs are positioned between the adjacent first packaging bodies, so that the warping of the second substrate and the chip packaging structure is relatively small.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to a chip packaging structure and an electronic device. Background Technology

[0002] Current chip packaging structures consist of a packaging substrate and dies soldered onto it. The dies can be electrically connected to other devices, such as printed circuit boards, via signal lines and pads on the packaging substrate. However, as chip integration increases, the number of dies soldered onto a single packaging substrate also increases, leading to greater warpage of the packaging substrate and consequently, greater warpage of the chip packaging structure. Utility Model Content

[0003] This application discloses a chip packaging structure and an electronic device to solve the problem that the warpage of the chip packaging structure is becoming increasingly large as the integration density of chips increases.

[0004] In a first aspect, this application discloses a chip packaging structure, comprising: a plurality of first packages; each first package includes a first die, a first substrate, and a first encapsulation layer; the first die is soldered onto the first substrate and is electrically connected to the first substrate; the first encapsulation layer is located on the first substrate and covers the side of the first die; a second substrate; the plurality of first packages are soldered onto the second substrate and are electrically connected to the second substrate; the first substrate is at least used to realize the electrical connection between the first die and the second substrate; the second substrate is at least used to realize the interconnection between the first packages and the electrical connection between the first packages and other devices; a first reinforcing rib; the first reinforcing rib is fixed on the second substrate and is located between adjacent first packages.

[0005] In this way, firstly, because multiple first packages can be soldered onto the second substrate, the area difference between the first substrate and the die is smaller compared to the area difference between the second substrate and the die. This results in less warpage of the first substrate after soldering the die, and consequently, less warpage of the second substrate and the chip package structure. Secondly, the first reinforcing ribs fixed to the second substrate and located between adjacent first packages further reduce the warpage of the second substrate and the chip package structure. Thirdly, by first soldering the first die onto the first substrate and forming a first encapsulation layer on the first substrate to cover the sides of the first die to form the first package, and then soldering multiple first packages onto the second substrate, the spacing of the pads on the first substrate can be made larger than the spacing of the pads on the first die. This reduces the probability of short circuits or other soldering risks between the first packages and the second substrate, and further reduces the probability of soldering risks in the chip package structure. Furthermore, even if a short circuit or other soldering problem occurs between one first package and the second substrate, it will not affect the soldering between other first packages and the second substrate, thus improving the yield and stability of the chip package structure.

[0006] In some embodiments of this application, the first package includes a first package and / or a second package; the first package includes a first die and a first substrate; the second package includes a plurality of first dies, a first substrate and a second reinforcing rib; the first substrate in the second package is further used to realize interconnection between the first dies; the second reinforcing rib is fixed on the first substrate and the second reinforcing rib is located between adjacent first dies.

[0007] In this way, not only can the integration of the chip packaging structure be improved, but the warpage of the first substrate and chip packaging structure with multiple first dies can also be reduced by the second reinforcing ribs between adjacent first dies.

[0008] In some embodiments of this application, the second type of package further includes a third reinforcing rib; the third reinforcing rib is fixed on the first substrate and is disposed around all the first bare dies of the second type of package.

[0009] In this way, the warpage of the first substrate and chip package structure can be further reduced by using a third reinforcing rib that surrounds all the first dies.

[0010] In some embodiments of this application, the chip packaging structure further includes a fourth reinforcing rib; the fourth reinforcing rib is fixed on the second substrate and is disposed around the plurality of first package bodies.

[0011] In this way, the warpage of the second substrate and the chip package structure can be further reduced by using fourth reinforcing ribs that surround multiple first packages.

[0012] In some embodiments of this application, the chip packaging structure further includes a packaging cover plate; the packaging cover plate is fixedly connected to the side of the fourth reinforcing rib facing away from the second substrate; or, the packaging cover plate and the fourth reinforcing rib are integrally formed; and the packaging cover plate, the fourth reinforcing rib and the second substrate form a receiving space; the plurality of first packages are located within the receiving space.

[0013] In this way, not only can the warpage of the second substrate and chip packaging structure be further reduced by the fourth reinforcing ribs surrounding the multiple first packages, but the multiple first packages can also be protected and cooled by the package cover.

[0014] In some embodiments of this application, the chip packaging structure further includes a second die and a fifth reinforcing rib; the second die is soldered onto the second substrate and is electrically connected to the second substrate; the fifth reinforcing rib is located on the second substrate and is located between the first package and the second die.

[0015] In this way, the warpage of the second substrate and chip package structure having the first package and the second die can be reduced by the fifth reinforcing rib located between the first package and the second die.

[0016] In some embodiments of this application, the materials of both the first substrate and the second substrate include organic materials; the material of the first reinforcing rib includes an inert metal material.

[0017] In this way, the first and second substrates can have good mechanical and electrical properties, are easy to process and assemble, and have low manufacturing costs.

[0018] In some embodiments of this application, the first die has a plurality of first pads on the side facing the first substrate; the first substrate has a plurality of second pads on the side away from the first die; the second substrate has a plurality of third pads on the side away from the first package; the spacing between the second pads is greater than the spacing between the first pads; and / or, the spacing between the third pads is greater than the spacing between the second pads.

[0019] In this way, not only can the probability of short circuits and other welding risks between the first package and the second substrate be reduced by making the spacing of the second pads greater than that of the first pads, but the probability of short circuits and other welding risks between the second substrate and other components such as printed circuit boards can also be reduced by making the spacing of the third pads greater than that of the second pads, thereby reducing the probability of welding risks in the chip package structure.

[0020] In some embodiments of this application, the chip packaging structure further includes a first passive device and / or a second passive device; the first passive device is disposed on the first substrate and is electrically connected to the first substrate; the second passive device is disposed on the second substrate and is electrically connected to the second substrate.

[0021] In this way, signal interference between the first and second substrates can be eliminated to the greatest extent, thereby improving the signal quality of the chip packaging structure.

[0022] Secondly, this application discloses an electronic device including a chip packaging structure as described in any of the preceding claims.

[0023] In this way, the yield and stability of electronic devices can be improved. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0025] Figure 1 This is a cross-sectional schematic diagram of a chip packaging structure disclosed in this application.

[0026] Figure 2 This is a top view schematic diagram of a chip packaging structure disclosed in an embodiment of this application.

[0027] Figure 3 for Figure 2 The diagram shows a cross-sectional view of the chip packaging structure along the cutting line AA.

[0028] Figure 4 This is a top view of another chip packaging structure disclosed in an embodiment of this application.

[0029] Figure 5 for Figure 4 The diagram shows a cross-sectional view of the chip packaging structure along the cutting line AA.

[0030] Figure 6 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0031] Figure 7 for Figure 6 The diagram shows a cross-sectional view of the chip packaging structure along the cutting line AA.

[0032] Figure 8 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0033] Figure 9 for Figure 8 The diagram shows a cross-sectional view of the chip packaging structure along the cutting line AA.

[0034] Figure 10 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0035] Figure 11 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0036] Figure 12 for Figure 11 The diagram shows a cross-sectional view of the chip package structure along the cutting line BB.

[0037] Figure 13 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0038] Figure 14 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0039] Figure 15 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0040] Figure 16 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0042] like Figure 1 As shown, Figure 1This is a cross-sectional schematic diagram of a chip packaging structure disclosed in this application. The chip packaging structure includes multiple dies 10, a packaging substrate 11, and a packaging cover 12. The packaging cover 12 and the packaging substrate 11 form a receiving space, within which the multiple dies 10 are located and electrically connected to the packaging substrate 11. The packaging substrate 11 is used to realize electrical connections between the multiple dies 10 and electrical connections between the multiple dies 10 and other devices such as printed circuit boards.

[0043] During the fabrication of the chip package structure, the reflow soldering process is used to melt the solder balls 100 between the die 10 and the package substrate 11 to achieve electrical connection between the die 10 and the package substrate 11. However, the applicant's research found that as the integration density of chips increases, the number of dies 10 soldered on a single package substrate 11 increases, resulting in greater warpage of the package substrate 11 after the reflow soldering process, which in turn leads to greater warpage of the chip package structure.

[0044] Based on this, this application discloses a chip packaging structure in which a first die is first welded onto a first substrate to form a first package, and then multiple first packages are welded onto a second substrate. Reinforcing ribs are provided between adjacent first packages to reduce the warping of the chip packaging structure.

[0045] As an optional implementation of the disclosure in this application, an embodiment of this application discloses a chip packaging structure, such as... Figure 2 and Figure 3 As shown, Figure 2 This is a top view schematic diagram of a chip packaging structure disclosed in an embodiment of this application. Figure 3 for Figure 2 The schematic diagram of the chip packaging structure shown is a cross-sectional view along the cutting line AA. The chip packaging structure includes multiple first package bodies 20, a second substrate 21, and a first reinforcing rib 22.

[0046] The first package 20 includes a first die 200, a first substrate 201, and a first encapsulation layer 202. The first die 200 is soldered to the first substrate 201 and is electrically connected to the first substrate 201. The first encapsulation layer 202 is located on the first substrate 201 and covers the side of the first die 200.

[0047] Multiple first packages 20 are soldered onto a second substrate 21, and the first substrates 201 of the multiple first packages 20 are electrically connected to the second substrate 21. The first substrate 201 is used at least to realize the electrical connection between the first die 200 and the second substrate 21. The second substrate 21 is used at least to realize the interconnection between the first packages 20 and the electrical connection between the first packages 20 and other devices such as printed circuit boards.

[0048] The first reinforcing rib 22 is fixed to the second substrate 21 and is located between adjacent first package bodies 20. The material of the first reinforcing rib 22 includes an inert metal. The first reinforcing rib 22 can be fixed to the second substrate 21 by welding or bonding. The first reinforcing rib 22 is used to suppress warping of the second substrate 21.

[0049] In this way, firstly, since multiple first packages 20 can be soldered onto the second substrate 21, the area difference between the first substrate 201 and the first die 200 is smaller compared to the area difference between the second substrate 21 and the first die 200. This results in less warping of the first substrate 201 after soldering the first die 200, and consequently, less warping of the second substrate 21 and the chip package structure.

[0050] Secondly, the warpage of the second substrate 21 and the chip packaging structure can be further reduced by fixing the first reinforcing rib 22 on the second substrate 21 and located between adjacent first package bodies 20.

[0051] Secondly, the first die 200 is first soldered onto the first substrate 201, and a first encapsulation layer 202 is formed on the first substrate 201 to encapsulate the side of the first die 200 to form a first package 20. Then, multiple first packages 20 are soldered onto the second substrate 21. By making the spacing of the pads on the first substrate 201 larger than the spacing of the pads on the first die 200, the probability of short circuits and other soldering risks between the first packages 20 and the second substrate 21 can be reduced, thereby further reducing the probability of soldering risks in the chip packaging structure.

[0052] Furthermore, even if a short circuit or other welding problem occurs between a certain first package 20 and the second substrate 21, it will not affect the welding between other first packages 20 and the second substrate 21, which can improve the yield and stability of the chip packaging structure.

[0053] In some embodiments of this application, the first package 20 includes a first type of package, such as... Figure 2 or Figure 3 As shown, the first type of package includes a first die 200 and a first substrate 201. Of course, this application is not limited to this; in other embodiments, such as... Figure 4 and Figure 5 As shown, Figure 4 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application. Figure 5 for Figure 4The schematic diagram of the chip package structure shown is a cross-sectional view along the cutting line AA. The first package 20 includes a second package, which comprises a plurality of first dies 200, a first substrate 201, and a second reinforcing rib 23. The second reinforcing rib 23 is fixed to the first substrate 201 and is located between adjacent first dies 200. The first substrate 201 is also used to realize interconnection between the first dies 200. In this way, not only can the integration of the chip package structure be improved, but the warpage of the first substrate 201 with multiple first dies 200 and the chip package structure can also be reduced by the second reinforcing rib 23 between adjacent first dies 200.

[0054] It should be noted that the number of first dies 200 included in the first package 20 can be set according to actual needs. However, to avoid excessive warping of the first substrate 201, the number of first dies 200 included in the first package 20 should not be too large. Furthermore, the material of the second reinforcing rib 23 includes an inert metal. The second reinforcing rib 23 can be fixed to the first substrate 201 by welding or bonding. The second reinforcing rib 23 is used to suppress warping of the first substrate 201.

[0055] In some embodiments of this application, such as Figure 6 and Figure 7 As shown, Figure 6 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application. Figure 7 for Figure 6 The schematic diagram of the chip package structure shown is a cross-sectional view along the cutting line AA. The second type of package also includes a third reinforcing rib 24, which is fixed to the first substrate 201 and surrounds all the first dies 200 of the second type of package. Similarly, the material of the third reinforcing rib 24 includes an inert metal. The third reinforcing rib 24 can be fixed to the first substrate 201 by means of welding or bonding. The third reinforcing rib 24 is used to suppress the warpage of the first substrate 201. In this way, the warpage of the first substrate 201 and the chip package structure can be further reduced by the third reinforcing rib 24 surrounding all the first dies 200 of the first package 20.

[0056] In some embodiments of this application, such as Figure 8 and Figure 9 As shown, Figure 8 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application. Figure 9 for Figure 8The schematic diagram of the chip package structure shown is a cross-sectional view along the cutting line AA. The chip package structure also includes a fourth reinforcing rib 25, which is fixed to the second substrate 21 and surrounds the plurality of first package bodies 20. Similarly, the material of the fourth reinforcing rib 25 includes an inert metal. The fourth reinforcing rib 25 can be fixed to the second substrate 21 by means of welding or bonding. The fourth reinforcing rib 25 is used to suppress warping of the second substrate 21. In this way, the warping of the second substrate 21 and the chip package structure can be further reduced by the fourth reinforcing rib 25 surrounding the plurality of first package bodies 20.

[0057] In some embodiments of this application, such as Figure 10 As shown, Figure 10 This is a cross-sectional view of another chip packaging structure disclosed in this application. The chip packaging structure further includes a packaging cover plate 30. The packaging cover plate 30 is fixedly connected to the side of the fourth reinforcing rib 25 facing away from the second substrate 21, or the packaging cover plate 30 and the fourth reinforcing rib 25 are integrally formed. Furthermore, the packaging cover plate 30, the fourth reinforcing rib 25, and the second substrate 21 form a receiving space, within which a plurality of first package bodies 20 are located. In this way, not only can the warpage of the second substrate 21 and the chip packaging structure be further reduced by the fourth reinforcing rib 25 surrounding the plurality of first package bodies 20, but the packaging cover plate 30 can also protect and dissipate heat from the plurality of first package bodies 20.

[0058] The encapsulation cover 30 is made of metal. Furthermore, the side of the first die 200 facing away from the first substrate 201 can contact the encapsulation cover 30 through a thermally conductive material, so that the heat generated by the first die 200 can be transferred to the encapsulation cover 30 via the thermally conductive material.

[0059] In some embodiments of this application, such as Figure 11 and Figure 12 As shown, Figure 11 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application. Figure 12 for Figure 11The schematic diagram of the chip package structure shown is a cross-sectional view along the cutting line BB. The chip package structure also includes a second die 211 and a fifth reinforcing rib 26. The second die 211 is soldered to the second substrate 21 and is electrically connected to the second substrate 21. The fifth reinforcing rib 26 is located on the second substrate 21 and between the first package body 20 and the second die 211. Similarly, the material of the fifth reinforcing rib 26 includes an inert metal material. The fifth reinforcing rib 26 can be fixed to the second substrate 21 by means of welding or bonding. The fifth reinforcing rib 26 is used to suppress the warpage of the second substrate 21. In this way, the warpage of the second substrate 21 having the first package body 20 and the second die 211 and the chip package structure can be reduced by the fifth reinforcing rib 26 located between the first package body 20 and the second die 211.

[0060] It should be noted that, in the embodiments of this application, the chip packaging structure may include two, three, four, five or even more first package bodies 20, and the multiple first package bodies 20 can be as follows: Figure 2 The array shown is arranged on the second substrate 21; however, this application is not limited to this, and in other embodiments, such as... Figure 13 or Figure 14 As shown, Figure 13 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application. Figure 14 This is a top view of another chip packaging structure disclosed in the embodiments of this application. The multiple first package bodies 20 can also be arranged in a non-array manner.

[0061] Of course, the chip packaging structure may also include multiple second dies 211, and the multiple first packages 20 and multiple second dies 211 may be arranged in an array or not in an array.

[0062] It should also be noted that the sizes of the first die 200 in each of the first package bodies 20 can be the same or different. In this embodiment, the arrangement can be set according to the size of the first package body 20, which will not be elaborated here.

[0063] In some embodiments of this application, such as Figure 15 As shown, Figure 15This is a cross-sectional view of another chip packaging structure disclosed in an embodiment of this application. The chip packaging structure further includes a second packaging layer 210, which is located on a second substrate 21 and wraps around the sides of a plurality of first package bodies 20 or a plurality of first package bodies 20 and a second die 211. In this way, the plurality of first package bodies 20 or a plurality of first package bodies 20 and the second die 211, together with the second substrate 21, constitute a second package, thereby improving the structural stability of the chip packaging structure. Of course, this application is not limited to this; in other embodiments, the chip packaging structure may not include the second packaging layer 210, which will not be elaborated here.

[0064] In some embodiments of this application, such as Figure 15 As shown, the first die 200 has a plurality of first pads 2001 on the side facing the first substrate 201, the first substrate 201 has a plurality of second pads 2010 on the side away from the first die 200, and the second substrate 21 has a plurality of third pads 211 on the side away from the first substrate 201. The spacing between the second pads 2010 is greater than the spacing between the first pads 2001, and / or the spacing between the third pads 211 is greater than the spacing between the second pads 2010.

[0065] In this way, not only can the probability of short circuits and other welding risks between the first package 20 and the second substrate 21 be reduced by making the spacing of the second pad 2010 greater than the spacing of the first pad 2001, but also the probability of short circuits and other welding risks between the second substrate 21 and other devices such as printed circuit boards can be reduced by making the spacing of the third pad 211 greater than the spacing of the second pad 2010, thereby reducing the probability of welding risks in the chip package structure.

[0066] Of course, this application is not limited to this. In some other embodiments, the spacing of the third pad 211 may also be equal to the spacing of the second pad 2010, which will not be elaborated here.

[0067] In some embodiments of this application, the first substrate 201 has multiple first signal lines, the second substrate 21 has multiple second signal lines, multiple first pads 2001 are electrically connected to multiple second pads 2010 through multiple first signal lines, and multiple second pads 2010 are electrically connected to multiple third pads 211 through multiple second signal lines. The width of the second signal lines is greater than the width of the first signal lines, and / or the spacing between the second signal lines is greater than the spacing between the first signal lines.

[0068] It is understandable that when the spacing of the second pad 2010 is greater than the spacing of the first pad 2001, the number of second signal lines can be greater, and the line width and line spacing of the second signal lines can be larger, thereby reducing the number of layers of the second substrate 21, thereby reducing the manufacturing process requirements of the second substrate 21, and thus reducing the manufacturing cost of the second substrate 21.

[0069] It should be noted that traditional packaging substrates not only need to achieve interconnection between the first dies 200 and electrical connection between the first dies 200 and other devices such as printed circuit boards, but also need to increase the spacing of the pads of the first dies 200 to match the lines of the first dies 200 with the lines of other devices such as printed circuit boards. In the embodiments of this application, by increasing the spacing of the pads of the first dies 200 through the first substrate 201, and by achieving interconnection between the first dies 200 and electrical connection between the first dies 200 and other devices such as printed circuit boards through the second substrate 21, not only can the lines of the first dies 200 be matched with those of other devices such as printed circuit boards, but the number of signal lines and pads in the packaging substrate, i.e., the second substrate 21, can also be reduced, thereby reducing the area and manufacturing cost of the packaging substrate, i.e., the second substrate 21.

[0070] In some embodiments of this application, such as Figure 15 As shown, the first pad 2001, the second pad 2010, and the third pad 211 all include solder balls. The spacing of the first pad 2001 refers to the distance L1 between the solder balls of adjacent first pads 2001, the spacing of the second pads 2010 refers to the distance L2 between the solder balls of adjacent second pads 2010, and the spacing of the third pad 211 refers to the distance L3 between the solder balls of adjacent third pads 211. Of course, this application is not limited to this; in some embodiments, the third pad 211 may not include solder balls, and the spacing of the third pad 211 may refer to the distance between adjacent third pads.

[0071] It should be noted that if the third pad 211 includes solder balls, the second substrate 21 can be directly soldered onto the printed circuit board through the solder balls of the third pad 211. However, if the third pad 211 does not include solder balls, the second substrate 21 needs to be electrically connected to the printed circuit board through a connector.

[0072] In some embodiments of this application, both the first substrate 201 and the second substrate 21 are made of organic materials. The second substrate 21 can be an ABF substrate or a PCB substrate, etc. In this way, the first substrate 201 and the second substrate 21 can have good mechanical and electrical properties, are easy to process and assemble, and have low manufacturing costs. Of course, this application is not limited to this; in other embodiments, the first substrate 201 can also be made of inorganic materials such as glass or silicon.

[0073] In some embodiments of this application, such as Figure 16 As shown, Figure 16 This is a cross-sectional view of another chip packaging structure disclosed in this application embodiment. The packaging cover plate 30 has multiple hollow areas 300 on the side away from the second substrate 21. The multiple hollow areas 300 expose the top surfaces of the first bare dies 200 of the multiple first package bodies 20. The hollow areas 300 are used to dissipate heat from the first bare dies 200.

[0074] In this way, the side of the first die 200 facing away from the first substrate 201 can contact the heat sink through the cutout area 300, so that the heat sink can directly dissipate heat from the first die 200, thereby improving the heat dissipation effect of the chip packaging structure.

[0075] In some embodiments of this application, such as Figure 16 As shown, Figure 16 This is a cross-sectional view of another chip packaging structure disclosed in an embodiment of this application. The chip packaging structure further includes a first passive device 203 and / or a second passive device 204. The first passive device 203 is disposed on the first substrate 201 and is electrically connected to the first substrate 201. The second passive device 204 is disposed on the second substrate 21 and is electrically connected to the second substrate 21.

[0076] The first passive device 203 and the second passive device 204 include capacitors or resistors, etc. Furthermore, the first passive device 203 may be located on the side of the first substrate 201 facing or away from the second substrate 21, and the second passive device 204 may also be located on the side of the second substrate 21 facing or away from the first substrate 201.

[0077] In this way, signal interference in the first substrate 201 and the second substrate 21 can be eliminated to the greatest extent, thereby improving the signal quality of the chip packaging structure.

[0078] As another optional implementation of the disclosure in this application, embodiments of this application also disclose an electronic device including the chip packaging structure disclosed in any of the above embodiments. In this way, the probability of soldering risks such as short circuits in the electronic device can be reduced, and the yield and stability of the electronic device can be improved.

[0079] In some embodiments of this application, the electronic device further includes a printed circuit board or the like that electrically connected to the chip package structure. This electronic device may be, for example, a computer server, a cloud server, or a distributed server.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The above embodiments are merely illustrative of several implementation methods described in detail, but they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A chip packaging structure, characterized in that, include: Multiple first packages; each first package includes a first die, a first substrate, and a first encapsulation layer; The first die is soldered onto the first substrate and is electrically connected to the first substrate; the first encapsulation layer is located on the first substrate and covers the side of the first die; A second substrate; the plurality of first packages are soldered onto the second substrate, and the first substrate is electrically connected to the second substrate; the first substrate is at least used to realize the electrical connection between the first die and the second substrate; the second substrate is at least used to realize the interconnection between the first packages and the electrical connection between the first packages and other devices; The first reinforcing rib is fixed on the second substrate and is located between adjacent first packages.

2. The chip packaging structure according to claim 1, characterized in that, The first package includes a first type of package and / or a second type of package; The first type of package includes a first die and a first substrate; The second type of package includes a plurality of first dies, a first substrate and a second reinforcing rib; the first substrate in the second type of package is also used to realize interconnection between the first dies; the second reinforcing rib is fixed on the first substrate and is located between adjacent first dies.

3. The chip packaging structure according to claim 2, characterized in that, The second type of package further includes a third reinforcing rib; the third reinforcing rib is fixed on the first substrate and is arranged around all the first bare dies of the second type of package.

4. The chip packaging structure according to any one of claims 1-3, characterized in that, The chip packaging structure further includes a fourth reinforcing rib; the fourth reinforcing rib is fixed on the second substrate and is arranged around the plurality of first packages.

5. The chip packaging structure according to claim 4, characterized in that, The chip packaging structure further includes a packaging cover plate; the packaging cover plate is fixedly connected to the side of the fourth reinforcing rib facing away from the second substrate; or, the packaging cover plate and the fourth reinforcing rib are integrally formed; and the packaging cover plate, the fourth reinforcing rib, and the second substrate form an accommodating space. The plurality of first encapsulation bodies are located within the accommodating space.

6. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a second die and a fifth reinforcing rib; the second die is soldered onto the second substrate and is electrically connected to the second substrate; the fifth reinforcing rib is located on the second substrate and is located between the first package and the second die.

7. The chip packaging structure according to claim 1, characterized in that, Both the first substrate and the second substrate are made of organic materials; the first reinforcing rib is made of an inert metal material.

8. The chip packaging structure according to claim 1, characterized in that, The first die has a plurality of first pads on the side facing the first substrate; the first substrate has a plurality of second pads on the side away from the first die; the second substrate has a plurality of third pads on the side away from the first package; the spacing between the second pads is greater than the spacing between the first pads; and / or, the spacing between the third pads is greater than the spacing between the second pads.

9. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a first passive device and / or a second passive device; the first passive device is disposed on the first substrate and is electrically connected to the first substrate; the second passive device is disposed on the second substrate and is electrically connected to the second substrate.

10. An electronic device, characterized in that, Includes the chip packaging structure described in any one of claims 1-9.

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