Chip packaging structure and electronic equipment

Abstract

The utility model discloses a chip packaging structure and electronic equipment, the chip packaging structure comprises a packaging substrate, a bare chip, a protection ring and a reinforcing ring, the bare chip is fixed on the packaging substrate and is electrically connected with the packaging substrate, the protection ring is fixed on the packaging substrate, the protection ring is arranged around the bare chip, the reinforcing ring is fixed on the packaging substrate, the reinforcing ring is arranged around the bare chip, and the bare chip is electrically connected with the bare chip. At least part of the reinforcing ring is located between the protection ring and the packaging substrate, so that warping of the chip packaging structure can be reduced through the reinforcing ring, the area, additionally occupied by the reinforcing ring, of the packaging substrate can be reduced by enabling at least part of the reinforcing ring to be located between the protection ring and the packaging substrate, and the integration level of the chip packaging structure is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to a chip packaging structure and an electronic device. Background Technology

[0002] Current chip packaging structures consist of a packaging substrate and bare dies fixed on the packaging substrate. However, as chip integration becomes increasingly sophisticated, the number of bare dies fixed on the packaging substrate is also increasing, leading to greater warpage in the chip packaging structure. Utility Model Content

[0003] This application discloses a chip packaging structure and an electronic device to solve the problem that the warpage of the chip packaging structure is becoming increasingly large as the integration density of chips increases.

[0004] In a first aspect, this application discloses a chip packaging structure, comprising: a packaging substrate; a bare die, the bare die being fixed to and electrically connected to the packaging substrate; a protective ring, the protective ring being fixed to the packaging substrate and surrounding the bare die; and a reinforcing ring, the reinforcing ring being fixed to the packaging substrate and surrounding the bare die, with at least a portion of the reinforcing ring located between the protective ring and the packaging substrate. In this way, not only can the warpage of the chip packaging structure be reduced by the reinforcing ring, but also the area of ​​the packaging substrate additionally occupied by the reinforcing ring can be reduced by having at least a portion of the reinforcing ring located between the protective ring and the packaging substrate, thereby improving the integration density of the chip packaging structure.

[0005] In some embodiments of this application, the reinforcing ring includes a first sub-reinforcing ring and a second sub-reinforcing ring; the protective ring includes a first sub-protective ring and a second sub-protective ring; the first sub-protective ring is located between the first sub-reinforcing ring and the packaging substrate, and the second sub-reinforcing ring is located between the die and the second sub-protective ring. In this way, the warpage of the chip packaging structure can be suppressed to the greatest extent while improving the integration density of the chip packaging structure.

[0006] In some embodiments of this application, the extension directions of the first sub-protective ring and the first sub-reinforcing ring are the same as the extension direction of the short side of the die, and the extension directions of the second sub-protective ring and the second sub-reinforcing ring are the same as the extension direction of the long side of the die. Because the warpage in the extension direction of the long side of the die is greater than the warpage in the extension direction of the short side of the die, this method can suppress the warpage of the chip package structure to the greatest extent while improving the integration density of the chip package structure.

[0007] In some embodiments of this application, the distance between the second sub-reinforcing ring and the bare sheet, as well as the distance between the second sub-reinforcing ring and the second sub-protective ring, is greater than 0.5 mm. In this way, by reasonably setting the positional relationship between the second sub-reinforcing ring and the bare sheet and the second sub-protective ring, the reinforcing ring can achieve the best anti-warping effect.

[0008] In some embodiments of this application, the chip packaging structure further includes a packaging cover plate, which is thermally connected to the side of the bare die opposite to the packaging substrate, and the packaging cover plate is fixedly connected to the side of the protective ring opposite to the packaging substrate. In this way, the packaging cover plate and the protective ring form a packaging shell, making the chip packaging structure suitable for devices with less stringent thickness requirements.

[0009] In some embodiments of this application, the chip packaging structure further includes a heat sink, which is thermally connected to the side of the die facing away from the packaging substrate, and the heat sink is fixedly connected to the packaging substrate. In this way, the thickness of the chip packaging structure can be reduced, making it suitable for devices with high thickness requirements.

[0010] In some embodiments of this application, a portion of the reinforcing rings is located between the protective ring and the packaging substrate; the protective ring has a groove on its side facing the packaging substrate; a portion of the reinforcing rings is located within the groove and fixedly connected to the inner wall of the groove; or, all the reinforcing rings are located between the protective ring and the packaging substrate; the side of all the reinforcing rings facing the packaging substrate is fixedly connected to the side of the protective ring facing away from the packaging substrate. In this way, the stability of the protective ring and reinforcing ring structure can be ensured.

[0011] In some embodiments of this application, the reinforcing ring is made of nickel-plated stainless steel or nickel-plated copper. In this way, the warpage suppression effect of the chip package structure can be improved by using a reinforcing ring whose material rigidity is much greater than that of the packaging substrate material.

[0012] In some embodiments of this application, the width of the reinforcing ring ranges from 2mm to 6mm; the thickness of the reinforcing ring ranges from 0.3mm to 3mm. In this way, the reinforcing ring can occupy as little area of ​​the packaging substrate as possible while suppressing warping.

[0013] Secondly, this application discloses an electronic device including the chip packaging structure described in any of the preceding claims. In this way, the probability of soldering failures and other risks in the electronic device can be reduced, and the yield and stability of the electronic device can be improved. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0015] Figure 1 This is a cross-sectional schematic diagram of a chip packaging structure disclosed in this application.

[0016] Figure 2 This is a top view schematic diagram of a chip packaging structure disclosed in an embodiment of this application.

[0017] Figure 3 for Figure 2 The diagram shows a cross-sectional view of the chip packaging structure along the AA cutting line.

[0018] Figure 4 for Figure 2 The diagram shows a cross-sectional view of the chip packaging structure along the BB cut line.

[0019] Figure 5 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0020] Figure 6 for Figure 5 The diagram shows a cross-sectional view of the chip packaging structure along the AA cutting line.

[0021] Figure 7 for Figure 5 The diagram shows a cross-sectional view of the chip packaging structure along the BB cut line.

[0022] Figure 8 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in this application.

[0023] Figure 9 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] like Figure 1 As shown, Figure 1 This is a cross-sectional schematic diagram of a chip packaging structure disclosed in this application. The chip packaging structure includes a die 10, a packaging substrate 11, and a protective ring 12. The die 10 is soldered to the packaging substrate 11 and electrically connected to the packaging substrate 11. The protective ring 12 is fixed to the packaging substrate 11 and surrounds the die 10.

[0026] During the fabrication of the chip package structure, a reflow soldering process is used to melt the solder balls 100 between the die 10 and the package substrate 11 to achieve electrical connection between the die 10 and the package substrate 11. However, because there is a significant difference in the coefficients of thermal expansion between the die 10 and the package substrate 11, the package substrate 11 warps after the reflow soldering process. This can cause the solder balls 100 at the edge of the die 10 to fail to bridge or cause the internal film layer of the die 10 to fail due to warping and delamination.

[0027] Furthermore, the applicant's research found that as the chip's integration level increases, the number of bare dies 10 soldered on the packaging substrate 11 increases, resulting in greater warpage of the packaging substrate 11 after the reflow soldering process, which in turn leads to greater warpage of the chip packaging structure.

[0028] Based on this, this application discloses a chip packaging structure that reduces warpage by providing a reinforcing ring around the die on the packaging substrate, and improves the integration of the chip packaging structure by placing at least a portion of the reinforcing ring between the protective ring and the packaging substrate.

[0029] As an optional implementation of the disclosure in this application, an embodiment of this application discloses a chip packaging structure, such as... Figures 2 to 4 As shown, Figure 2 This is a top view schematic diagram of a chip packaging structure disclosed in an embodiment of this application. Figure 3 for Figure 2 The diagram shows a cross-sectional view of the chip package structure along the AA cutting line. Figure 4 for Figure 2 The schematic diagram shown is a cross-sectional view of the chip packaging structure along the BB cutting line. The chip packaging structure includes a die 10, a packaging substrate 11, a protective ring 12, and a reinforcing ring 13.

[0030] The die 10 is fixed to and electrically connected to the packaging substrate 11. The protective ring 12 is fixed to the packaging substrate 11 and surrounds the die 10. The reinforcing ring 13 is fixed to the packaging substrate 11, surrounds the die 10, and at least a portion of the reinforcing ring 13 is located between the protective ring 12 and the packaging substrate 11.

[0031] It should be noted that in this embodiment, the chip package structure includes only one bare die 10 as an example. However, this application is not limited to this. In other embodiments, the chip package structure may include multiple bare dies 10, and the protective ring 12 and the reinforcing ring 13 are arranged around the multiple bare dies 10.

[0032] It should also be noted that the reinforcing ring 13 is fixed on the packaging substrate 11 before the bare die 10 is soldered. Therefore, when the solder balls between the bare die 10 and the packaging substrate 11 are melted using the reflow soldering process, the reinforcing ring 13 will suppress the warping of the packaging substrate 11, thereby reducing the warping of the chip packaging structure.

[0033] In this embodiment, not only can the warpage of the chip packaging structure be reduced by the reinforcing ring 13, but also the area of ​​the packaging substrate 11 occupied by the reinforcing ring 13 can be reduced by placing at least a portion of the reinforcing ring 13 between the protective ring 12 and the packaging substrate 11, thereby improving the integration of the chip packaging structure.

[0034] In some embodiments of this application, a portion of the reinforcing ring 13 is located between the protective ring 12 and the packaging substrate 11. For example... Figures 2 to 4 As shown, the reinforcing ring 13 includes a first sub-reinforcing ring 131 and a second sub-reinforcing ring 132, and the protective ring 12 includes a first sub-protective ring 121 and a second sub-protective ring 122. The first sub-protective ring 121 is located between the first sub-reinforcing ring 131 and the packaging substrate 11, and the second sub-reinforcing ring 132 is located between the bare die 10 and the second sub-protective ring 122. In this way, the warpage of the chip packaging structure can be suppressed to the greatest extent while improving the integration density of the chip packaging structure.

[0035] In some embodiments of this application, such as Figure 2 As shown, the extension directions of the first sub-protective ring 121 and the first sub-reinforcing ring 131 are the same as the extension direction of the short side of the die 10, and the extension directions of the second sub-protective ring 122 and the second sub-reinforcing ring 132 are the same as the extension direction of the long side of the die 10. Because the warpage in the extension direction of the long side of the die 10 is greater than the warpage in the extension direction of the short side of the die 10, this method can suppress the warpage of the chip package structure to the greatest extent while improving the integration density of the chip package structure.

[0036] In some embodiments of this application, such as Figure 3 As shown, the distance D1 between the second sub-reinforcing ring 132 and the bare sheet 10, and the distance D2 between the second sub-reinforcing ring 132 and the second sub-protective ring 122, are both greater than 0.5 mm. In this way, by reasonably setting the positional relationship between the second sub-reinforcing ring 132 and the bare sheet 10 and the second sub-protective ring 122, the reinforcing ring 13 can achieve the best effect in suppressing warping.

[0037] In some embodiments of this application, such as Figure 4 As shown, a portion of the reinforcing ring 13 is located between the protective ring 12 and the packaging substrate 11. The protective ring 12 has a groove 120 on the side facing the packaging substrate 11, and the portion of the reinforcing ring 13 is located within the groove 120 and fixedly connected to the inner wall of the groove 120. In this way, the stability of the structure of the protective ring 12 and the reinforcing ring 13 can be ensured.

[0038] Of course, this application is not limited to this; in other embodiments, such as Figures 5 to 7 As shown, Figure 5 This is a top view schematic diagram of another chip packaging structure disclosed in an embodiment of this application. Figure 6 for Figure 5 The diagram shows a cross-sectional view of the chip package structure along the AA cutting line. Figure 7 for Figure 5 The schematic diagram of the chip package structure along the BB cutting line shows that all reinforcing rings 13 can also be located between the protective ring 12 and the package substrate 11, and the side of all reinforcing rings 13 facing the package substrate 11 is fixedly connected to the side of the protective ring 12 facing away from the package substrate 11. In this way, the integration density of the chip package structure can be maximized while reducing the warpage of the chip package structure.

[0039] It should be noted that the protective ring 12 and the reinforcing ring 13 can be fixed to the packaging substrate 11 by baking and curing adhesive or the like, and the protective ring 12 can also be fixedly connected to the reinforcing ring 13 by baking and curing adhesive or the like.

[0040] In some embodiments of this application, the material of the packaging substrate 11 includes organic materials. The rigidity of the material of the reinforcing ring 13 is much greater than that of the material of the packaging substrate 11. For example, the material of the reinforcing ring 13 includes nickel-plated stainless steel or nickel-plated copper. In this way, the warpage suppression effect of the chip packaging structure can be improved by using the reinforcing ring 13, whose material rigidity is much greater than that of the packaging substrate 11. Of course, this application is not limited to this. In other embodiments, the material of the reinforcing ring 13 may also include other metallic materials, etc., which will not be elaborated here.

[0041] In some embodiments of this application, the width of the reinforcing ring 13 ranges from 2mm to 6mm; the thickness of the reinforcing ring 13 ranges from 0.3mm to 3mm. In this way, the reinforcing ring 13 can occupy as little area as possible on the packaging substrate 11 while suppressing warping.

[0042] It should be noted that the thickness of the protective ring 12, the thickness of the reinforcing ring 13, and the total thickness of the stacked protective ring 12 and reinforcing ring 13 are all less than the thickness of the bare PCB 10, so as to avoid the protective ring 12 and reinforcing ring 13 affecting the subsequent installation of heat sinks, etc.

[0043] In some embodiments of this application, such as Figure 2 and Figure 5As shown, the projections of the protective ring 12 and the reinforcing ring 13 onto the packaging substrate 11 are square in shape. However, this application is not limited to this. In some embodiments, the projections of the protective ring 12 and the reinforcing ring 13 onto the packaging substrate 11 can also be regular shapes such as circles. In other embodiments, the projections of the protective ring 12 and the reinforcing ring 13 onto the packaging substrate 11 can also be irregular shapes such as serrated edges. The projections of the protective ring 12 and the reinforcing ring 13 onto the packaging substrate 11 can be the same or different.

[0044] In some embodiments of this application, such as Figure 2 and Figure 5 As shown, the protective ring 12 and the reinforcing ring 13 have the same width L. This not only ensures the stability of the stacked protective ring 12 and reinforcing ring 13 structure, but also allows the reinforcing ring 13 to occupy less area of ​​the packaging substrate 11, maximizing the integration density of the chip packaging structure. However, this application is not limited to this; in other embodiments, the width of the reinforcing ring 13 may be slightly larger than the width of the protective ring 12, which will not be elaborated here.

[0045] Understandable, Figure 2 and Figure 5 The slight difference in width between the protective ring 12 and the reinforcing ring 13 shown is only to distinguish between the two structures and does not indicate that the protective ring 12 and the reinforcing ring 13 have different widths.

[0046] In some embodiments of this application, such as Figure 8 As shown, Figure 8 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in this application. The chip packaging structure also includes a packaging cover plate 14, which is thermally connected to the side of the bare die 10 facing away from the packaging substrate 11. The packaging cover plate 14 is also fixedly connected to the side of the protective ring 12 facing away from the packaging substrate 11. In this way, the packaging cover plate 14 and the protective ring 12 can form a packaging shell, making the chip packaging structure suitable for devices with low thickness requirements.

[0047] The encapsulation cover 14 can be made of metal. The encapsulation cover 14 can be thermally connected to the bare die 10 via a thermally conductive sheet, such as an indium foil. Heat generated by the bare die 10 can be transferred to the encapsulation cover 14 via the thermally conductive sheet, and then to the heat sink or air via the encapsulation cover 14. The encapsulation cover 14 can be fixedly connected to the protective ring 12 using a baked-cured adhesive or similar material.

[0048] Of course, this application is not limited to this; in other embodiments, such as Figure 9 As shown, Figure 9This is a cross-sectional schematic diagram of another chip packaging structure disclosed in this application. The chip packaging structure also includes a heat sink 15, which is thermally connected to the side of the bare die 10 away from the packaging substrate 11, and the heat sink 15 is fixedly connected to the packaging substrate 11. In this way, the thickness of the chip packaging structure can be reduced, making the chip packaging structure suitable for devices with high thickness requirements.

[0049] The heat sink 15 can be fixedly connected to the packaging substrate 11 by screws or the like. Of course, this application is not limited to this. In other embodiments, the heat sink 15 can be fixedly connected to the printed circuit board by screws or the like, which will not be described in detail here.

[0050] In some embodiments of this application, the chip packaging structure may also include passive components, such as capacitors or resistors, which are soldered onto the packaging substrate 11 to filter interference signals on the packaging substrate 11.

[0051] It should be noted that in traditional chip packaging structures, the warpage of the packaging substrate 11 is approximately -390.29 μm, and the warpage of the die 10 is approximately -185.952 μm. In the chip packaging structure of this embodiment, the warpage of the packaging substrate 11 is approximately -263.21 μm, a reduction of 32.5%, and the warpage of the die 10 is approximately -140.07 μm, a reduction of 24.8%. Therefore, the reinforcement ring 13 in this embodiment significantly improves the warpage of the chip packaging structure.

[0052] As an optional implementation of the disclosure in this application, an embodiment of this application discloses an electronic device that includes the chip packaging structure disclosed in any of the above embodiments. In this way, the probability of soldering failures and other risks in the electronic device can be reduced, and the yield and stability of the electronic device can be improved.

[0053] In some embodiments of this application, the electronic device further includes a printed circuit board or the like that electrically connected to the chip package structure. This electronic device may be, for example, a computer server, a cloud server, or a distributed server.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above embodiments are merely illustrative of several implementation methods described in detail, but they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A chip packaging structure, characterized in that, include: Packaging substrate; A bare die, which is fixed to the packaging substrate and electrically connected to the packaging substrate; A protective ring is fixed on the packaging substrate and surrounds the bare die. A reinforcing ring is fixed to the packaging substrate, the reinforcing ring is disposed around the bare die, and at least a portion of the reinforcing ring is located between the protective ring and the packaging substrate.

2. The chip packaging structure according to claim 1, characterized in that, The reinforcing ring includes a first sub-reinforcing ring and a second sub-reinforcing ring; The protection ring includes a first sub-protection ring and a second sub-protection ring; the first sub-protection ring is located between the first sub-reinforcing ring and the packaging substrate, and the second sub-reinforcing ring is located between the bare die and the second sub-protection ring.

3. The chip packaging structure according to claim 2, characterized in that, The first sub-protective ring and the first sub-reinforcing ring extend in the same direction as the short side of the bare die, and the second sub-protective ring and the second sub-reinforcing ring extend in the same direction as the long side of the bare die.

4. The chip packaging structure according to claim 2, characterized in that, The distance between the second sub-reinforcing ring and the bare sheet, as well as the distance between the second sub-reinforcing ring and the second sub-protective ring, are both greater than 0.5 mm.

5. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes a packaging cover plate, which is thermally connected to the side of the bare die away from the packaging substrate, and the packaging cover plate is fixedly connected to the side of the protective ring away from the packaging substrate.

6. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes a heat sink, which is thermally connected to the side of the die away from the packaging substrate, and the heat sink is fixedly connected to the packaging substrate.

7. The chip packaging structure according to claim 1, characterized in that, Part of the reinforcing ring is located between the protective ring and the packaging substrate; the protective ring has a groove on the side facing the packaging substrate; part of the reinforcing ring is located within the groove and is fixedly connected to the inner wall of the groove; or, All of the reinforcing rings are located between the protective ring and the packaging substrate; the side of all the reinforcing rings facing the packaging substrate is fixedly connected to the side of the protective ring facing away from the packaging substrate.

8. The chip packaging structure according to claim 1, characterized in that, The reinforcing ring is made of stainless steel with a nickel-plated surface or copper with a nickel-plated surface.

9. The chip packaging structure according to claim 1, characterized in that, The width of the reinforcing ring ranges from 2mm to 6mm; the thickness of the reinforcing ring ranges from 0.3mm to 3mm.

10. An electronic device, characterized in that, Includes the chip packaging structure described in any one of claims 1-9.

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