Surge protection devices and electrical equipment

Abstract

This application relates to surge protection devices and electrical equipment. The surge protection device includes: at least two electrode structures arranged sequentially, with a gap between adjacent electrode structures; at least one housing structure, which is respectively sealed to the two adjacent electrode structures, and the housing structure defines an internal space; and at least one pair of wafers, each pair of wafers disposed within the housing structure, each wafer in each pair being electrically connected to a corresponding electrode structure in the two adjacent electrode structures, and each pair of wafers partially overlapping and spaced apart. This surge protection device has a small overall size, ensuring a large current carrying capacity, and also possesses high withstand voltage capability.

Description

Technical Field

[0001] This application relates to the field of electrical components technology, and in particular to surge protection devices and electrical equipment. Background Technology

[0002] With the rapid development of the new energy sector, photovoltaic and charging pile equipment are constantly being updated. One trend in these devices is the development towards high-voltage DC charging to improve charging speed and efficiency. In pursuing the goals of fast charging and efficient energy conversion, high-power energy conversion inevitably leads to high-voltage and high-current flows at the ports. This renders conventional protection solutions inapplicable, necessitating adjustments to the voltage and current withstand levels of protective devices.

[0003] Conventional charging piles operate at AC220V / AC380V, while high-voltage DC charging types use DC voltages of 200V, 400V, 500V, and even up to thousands of volts. Conventional metal oxide varistors and transient voltage suppressors (TVS) have low voltage withstand capabilities, typically below 100V, which is clearly insufficient for the voltage withstand requirements of actual charging piles and DC charging stations. Directly using these protective devices would result in their failure to provide surge protection. For high-power products such as new energy equipment, the failure mode of these protective devices may be a short circuit, and given the external connection of high-power equipment, the safety issues caused by short circuits are extremely serious.

[0004] Currently, the protective structures for such equipment are generally large-volume designs that enhance insulation by increasing distance, thus providing protection against high-voltage surges. This protective method does not meet actual production requirements because it affects the product's size and introduces unnecessary structural designs, severely limiting its application scenarios. Utility Model Content

[0005] Therefore, it is necessary to provide surge protection devices to address at least one of the above-mentioned problems.

[0006] On one hand, this application provides a surge protection device, which includes: at least two electrode structures arranged sequentially, with a gap between adjacent electrode structures; at least one housing structure, which is respectively sealed to two adjacent electrode structures and defines an internal space; and at least one pair of wafers, each pair of wafers being disposed within the housing structure, each wafer in each pair being electrically connected to a corresponding electrode structure in the two adjacent electrode structures, and each pair of wafers partially overlapping and having a gap.

[0007] By incorporating a pair of electrodes, the overall size of the surge protection device is reduced while ensuring a large current-carrying capacity and high voltage withstand capability. Combined with the housing structure, this ensures structural stability and insulation between the two electrode structures. The surge protection device can be used in high-voltage external equipment to achieve equipment protection, adapting to production needs and operating environments.

[0008] In some embodiments, the spacing ranges from 50 μm to 200 μm; the surface of the overlapping region of the wafer includes a photolithographic surface.

[0009] This configuration ensures an appropriate operating voltage, helping to avoid problems such as abnormal power outages that could affect the product's lifespan.

[0010] In some embodiments, the thickness of the wafer ranges from 600 μm to 800 μm; the depth to which the photolithographic surface is recessed into the wafer ranges from 100 μm to 200 μm.

[0011] This design ensures structural strength, enabling the manufacture of high-quality photolithographic surfaces; it also allows for control of the spacing after assembly, achieving optimal performance.

[0012] In some implementations, the overlap area of ​​each pair of wafers is less than half the area of ​​any single wafer.

[0013] This setup helps ensure reliable assembly.

[0014] In some implementations, the diameter of the wafer ranges from 1 mm to 3 mm. Exemplarily, the wafer is a single-crystal silicon wafer.

[0015] This design results in a small chip size, which in turn leads to a small overall size of the surge protection device.

[0016] In some embodiments, the outer periphery of the electrode structure is provided with a groove, and the electrode structure and the housing structure are sealed by adhesive bonding.

[0017] This configuration allows the electrode structure to be fixed to the housing structure. The surge protection device has a simple and compact structure, and achieves sealing of the wafer.

[0018] In some embodiments, the electrode structure includes an electrode and an insulating heat dissipation structure, the electrode being electrically connected to a corresponding wafer and used for external connection, and the insulating heat dissipation structure covering a portion of the electrode.

[0019] This configuration ensures the flow capacity of the surge path during a surge by utilizing the electrodes, while the insulating and heat dissipation structure disperses the energy generated by the surge, reducing heat accumulation on the electrodes.

[0020] In some embodiments, the electrode is an aluminum electrode, and the insulating and heat dissipation structure is an aluminum oxide layer.

[0021] With this configuration, the electrode structure has stable performance, and the insulating heat dissipation structure has good thermal conductivity.

[0022] For example, the gas contained in the interior space is an inert gas.

[0023] This design protects the chip and prevents it from oxidizing.

[0024] In some embodiments, the housing structure includes a silicon frame and a silicon carbide frame fitted over the silicon frame.

[0025] With this design, the shell structure is stable and provides effective protection.

[0026] On the other hand, this application provides an electrical device comprising: a first wire; a second wire for transmitting current with the first wire and having a voltage difference with the first wire; and at least one of the aforementioned surge protection devices connected between the first wire and the second wire.

[0027] The electrical equipment described in this application has a high voltage and is protected against surge damage.

[0028] On the other hand, this application provides a method for manufacturing a surge protection device, the method comprising: electrically connecting each of a pair of wafers to a corresponding electrode structure in two adjacent electrode structures, each pair of wafers partially overlapping and having a gap; sealingly connecting the two electrode structures to a housing structure and disposing of the pair of wafers within the housing structure, the two electrode structures having a gap between them, and defining an internal space within the housing structure.

[0029] The method for manufacturing surge protection devices disclosed in this application can produce surge protection devices with high current capacity and high voltage resistance. Attached Figure Description

[0030] Figure 1 This is a schematic structural diagram of a surge protection device according to one or more embodiments;

[0031] Figure 2 This is a schematic structural diagram of a surge protection device according to one or more embodiments;

[0032] Figure 3 This is a schematic diagram of the structure of two wafers according to one or more embodiments;

[0033] Figure 4 This is a schematic cross-sectional view of an electrode structure according to one or more embodiments;

[0034] Figure 5 A schematic cross-sectional view of a surge protection device according to one or more embodiments;

[0035] Figure 6A schematic cross-sectional view of a surge protection device according to one or more embodiments;

[0036] Figure 7 This is a schematic structural diagram of an electrical device according to one or more embodiments;

[0037] Figure 8 A surge protection curve of an electrical device according to one embodiment;

[0038] Figure 9 This is a schematic structural diagram of an electrical device according to one or more embodiments;

[0039] Figure 10 This is a schematic structural diagram of an electrical device according to one or more embodiments;

[0040] Figure 11 This is a schematic structural diagram of an electrical device according to one or more embodiments;

[0041] Figure 12 This is a schematic flowchart of a method for manufacturing a surge protection device according to one or more embodiments.

[0042] Explanation of reference numerals in the attached drawings: 1. Electrode structure; 101. Groove; 11. Electrode; 12. Insulation and heat dissipation structure; 2. Shell structure; 201. Internal space; 202. Protrusion; 21. Silicon frame; 22. Silicon carbide frame; 3. Wafer; 301. Photolithography surface; 4. Lead wire;

[0043] 10. Surge protection devices; 100. Electrical equipment; 110. First wire; 120. Second wire; 130. Third wire; 140. Fourth wire; 150. Fifth wire. Detailed Implementation

[0044] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0045] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0046] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0047] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. For example, a first electrode structure may also be referred to as a second electrode structure, and a second electrode structure may also be referred to as a first electrode structure. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0048] In this application, unless otherwise expressly specified and limited, the terms "connected," "linked," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a flexible connection or a rigid connection along at least one direction; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium, or a direct connection with an intermediate medium present; and they can also refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. The terms "installed," "set," "fixed," etc., can be broadly understood as connection. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0049] As used in this application, the terms "layer" and "region" refer to a material portion comprising a defined area and having a defined thickness. A layer can extend horizontally, vertically, and / or along a conical surface. A layer can be a region of uniform or non-uniform continuous structure, and its thickness perpendicular to the direction of extension may not exceed the thickness of the continuous structure. A layer can comprise multiple layers, which can be stacked layers or discretely extending layers. The shapes of the various regions and layers in the accompanying drawings, as well as their relative sizes and positional relationships, are merely illustrative and may deviate from actual dimensions due to manufacturing tolerances or technical limitations, and the design can be adjusted according to actual needs.

[0050] refer to Figure 1 , Figure 1 This application illustrates a surge protection device. In an exemplary embodiment, the surge protection device 10 includes two electrode structures 1, a housing structure 2, and two wafers 3. Figures 2 to 5 As shown, for ease of description, a spatial rectangular coordinate system XYZ is established.

[0051] The two electrode structures 1 can be arranged along the Z-axis and have a gap, which can... Figure 1 The electrode structure 1 on the right side is called the first electrode structure, and the electrode structure 1 on the left side is called the second electrode structure.

[0052] The housing structure 2 is sealed and connected to two adjacent electrode structures 1 respectively. The housing structure 2 can be sleeved on the outer periphery of the electrode structure 1. The housing structure 2 defines an internal space 201, which is sealed and can be isolated from the external space.

[0053] Two wafers 3 are disposed within the housing structure 2. Figure 1 Of the two wafers 3, the right wafer 3 can be referred to as the first wafer, and the left wafer 3 can be referred to as the second wafer. The right wafer 3 corresponds to the right electrode structure 1, and the two are electrically connected; the left wafer 3 corresponds to the left electrode structure 1, and the two are electrically connected. Figure 2 As shown, both wafers 3 extend approximately along the YZ plane, and their dimension along the X-axis can be referred to as their thickness. The two wafers 3 partially overlap; for example, they are stacked along the X-axis and staggered along the Z-axis. There is a gap between the two wafers 3. Specifically, the wafers 3 do not directly contact the housing structure 2, ensuring insulation.

[0054] Both electrode structures 1 can be used for external circuits. The surge protection device 10 can maintain an open circuit under high voltage conditions of not less than 1500V DC. When a large surge occurs, it can achieve a short circuit to prevent the protected electrical components or electrical interfaces from being impacted by the surge. The operating withstand voltage of the surge protection device 10 is not less than 850V DC.

[0055] By setting a pair of spaced-apart wafers 3, the two electrode structures 1 are insulated against high voltage. The small distance between the two electrode structures 1 reduces the overall size of the surge protection device 10. The electrode structure 1, together with the housing structure 2, ensures the structural stability of the surge protection device 10. The surge protection device 10 can be used in high-voltage external equipment, ensuring both high current carrying capacity and high voltage withstand capability, thus achieving equipment protection. The surge protection device 10 is small in size and compact in structure, thereby adapting to production needs and operating environments.

[0056] Combination Figure 2 As shown, in some embodiments, the overlapping area of ​​the two wafers 3 is less than half the area of ​​either wafer 3, which helps to ensure reliable assembly. The wafers 3 can be generally circular, and the overlapping area of ​​the two wafers 3 can be generally spindle-shaped. Exemplarily, the diameter of the wafers 3 ranges from 1 mm to 3 mm, for example, 1.5 mm, 2 mm, or 2.5 mm. The small size of the wafers 3, consequently, results in a small overall size of the surge protection device 10.

[0057] Wafer 3 can be a single-crystal semiconductor wafer; for example, wafer 3 is a single-crystal silicon wafer. Wafer 3 can withstand high voltage and maintain performance when current is applied.

[0058] refer to Figure 3 The spacing h between the two wafers 3 ranges from 50 μm to 200 μm, for example, 70 μm, 100 μm, 130 μm, and 170 μm. The surface of the overlapping region of the wafers 3 includes a photolithographic surface 301. The photolithographic surface 301 is recessed into the wafers 3. When the spacing between the two wafers 3 is less than 50 μm, there is a problem of insufficient insulation and failure of the surge protection device 10. When the spacing between the two wafers 3 is greater than 200 μm, it can be used in circuits with particularly lenient voltage requirements; furthermore, configuring the spacing between the two wafers 3 to be less than or equal to 200 μm allows it to be used in circuits with more stringent voltage requirements. For example, a spacing of 150 μm between the two wafers 3 can ensure an appropriate operating voltage and also helps to avoid problems such as abnormal power outages that affect lifespan.

[0059] The thickness 'a' of wafer 3 can range from 600 μm to 800 μm, for example, 700 μm. Wafer 3 has sufficient structural strength, including at the recesses, to produce a high-quality photolithographic surface. The depth 'b' of the photolithographic surface 301 recessed into wafer 3 can range from 100 μm to 200 μm, for example, 150 μm. The two photolithographic surfaces 301 are positioned opposite each other, allowing control over the post-assembly spacing and ensuring conductivity during large surges, thus maintaining operational performance.

[0060] For example, the depth of the photolithography surface 301 recessed into the wafer 3 is 200 μm, and the spacing between the two photolithography surfaces 301 can be controlled to be 100 μm. The distance c between the edge of the wafer 3 and the sidewall of the groove of the other wafer 3 is larger than the spacing h, so as to avoid the edge tip affecting the working performance.

[0061] In other embodiments, the photolithographic surface 301 is recessed into the wafer 3 to a depth of 100 μm, and the distance between the two photolithographic surfaces 301 is 200 μm. The lower surface of the upper wafer 3 and the upper surface of the lower wafer 3 can be flush. The distance c between the edge of the wafer 3 and the sidewall of the groove of the other wafer 3 can still be controlled to be greater than the distance h.

[0062] The wafer 3 can be electrically connected to the corresponding electrode structure 1 via the lead 4. The position of the wafer 3 relative to the electrode structure 1 can be fixed.

[0063] Electrode structure 1 may have a groove 101. An adhesive, such as epoxy resin, can be applied between electrode structure 1 and housing structure 2 for connection and sealing. The outer periphery of electrode structure 1 fits into housing structure 2 and is sealed by adhesive bonding. Electrode structure 1 can be fixed to housing structure 2. Surge protection device 10 has a simple and compact structure and achieves sealing of wafer 3.

[0064] refer to Figure 1 The electrode structure 1 may include an electrode 11 and an insulating and heat-dissipating structure 12. The electrode 11 is electrically connected to the corresponding chip 3 and used for external connection, while the insulating and heat-dissipating structure 12 covers a portion of the electrode 11. The electrode 11 ensures the current-carrying capacity during surges, while the insulating and heat-dissipating structure 12 disperses the energy generated by the surge, reducing heat accumulation on the electrode 11. The insulating and heat-dissipating structure 12 also protects the electrode 11, preventing performance degradation due to oxidation. The insulating and heat-dissipating structure 12 may surround the outer periphery of the electrode 11. (Reference) Figure 4 The insulating and heat-dissipating structure 12 encloses the electrode 11.

[0065] Electrode 11 can be an aluminum electrode, and insulating heat dissipation structure 12 can be an aluminum oxide layer. Electrode structure 1 has stable performance, and insulating heat dissipation structure 12 has good thermal conductivity. For example, the thickness of a single layer of insulating heat dissipation structure 12 is 3 to 5 times the thickness of electrode 11 along the Z-axis. If insulating heat dissipation structure 12 is too thick, the surge protection device 10 will be too large; if insulating heat dissipation structure 12 is too thin, its protection capability for electrode 11 will be low, and its anti-oxidation effect will be poor. The thickness of insulating heat dissipation structure 12 can be 3 to 4 times the thickness of electrode 11, for example, 4 times. Insulating heat dissipation structure 12 can be well fixedly connected to electrode 11 and can also be well fixed to housing structure 2, achieving a good sealing effect.

[0066] The housing structure 2 may include a silicon frame 21 and a silicon carbide frame 22. The silicon carbide frame 22 is fitted onto the silicon frame 21. The housing structure 2 has stable performance and can effectively protect the wafer 3. The electrode structure 1 can be fixed to the silicon frame 21. Exemplarily, the housing structure 2 may be designed with protrusions 202. (Reference) Figure 5 and Figure 6 The silicon frame 21 or the silicon carbide frame 22 can be either a one-piece structure or a spliced ​​structure.

[0067] The gas contained in the internal space 201 can be an inert gas, such as argon. The inert gas can protect the wafer 3 and prevent it from oxidizing. An inert gas can also be present between the two photolithographic surfaces 301.

[0068] refer to Figure 7 This application provides an electrical device 100, which may be a single-phase power supply device or an electrical appliance. The electrical device 100 may include a first wire 110 and a second wire 120, the second wire 120 being used to transmit current with the first wire 110, and the second wire 120 having a voltage difference with the first wire 110.

[0069] The electrical equipment 100 also includes a surge protection device 10. The surge protection device 10 is connected between the first wire 110 and the second wire 120. Under normal operation, it maintains an open circuit; however, in the event of a large surge, the surge protection device 10 can short-circuit. The electrical equipment 100 of this application operates at high voltage. By incorporating the surge protection device 10, the insulation withstand voltage problem under high power and high current conditions can be solved, the high-voltage breakdown problem can be resolved, the surge protection capability of the electrical equipment 100 can be enhanced, and its service life can be extended. Furthermore, it helps to address the impact of current and high temperature on the electrical equipment 100 under high-voltage conditions, preventing irreversible damage to the electrical equipment 100 caused by these environmental conditions.

[0070] refer to Figure 8 A surge of 6KV voltage and waveform of 1.2 / 50μs was applied to the surge protection device 10. According to the curve displayed on the oscilloscope, the operating voltage of the surge protection device 10 is 960V. It pulls the 6KV voltage down to 960V and clamps the 960V voltage to 0V within about 100μs, thus protecting the circuit.

[0071] refer to Figure 9The electrical equipment 100 may include a first wire 110, a second wire 120, and a third wire 130. The electrical equipment 100 may use or output three-phase power, and may be a three-phase three-wire configuration. The electrical equipment 100 may include two surge protection devices 10, used in combination. Both surge protection devices 10 can be connected to the third wire 130, for example, as a ground wire (PE); simultaneously, the other electrode structure 1 of one surge protection device 10 is electrically connected to the first wire 110, for example, as a neutral wire (N), and the other electrode structure 1 of the other surge protection device 10 is electrically connected to the second wire 120, for example, as a first phase wire (L1). This electrical equipment 100 is easy to install, adaptable to actual usage environments, and has good safety performance.

[0072] In other embodiments, it can be a single surge protection device 10, including three electrode structures 1 arranged in sequence, two housing structures 2 respectively sealed and connected to two adjacent electrode structures 1, and each pair of two pairs of wafers 3 disposed in a housing structure 2 and electrically connected between the two electrode structures 1.

[0073] refer to Figure 10 The electrical equipment 100 may include a first wire 110, a second wire 120, a fourth wire 140, and a fifth wire 150. The electrical equipment 100 may also include three surge protection devices 10 arranged consecutively. The right electrode structure 1 of the right surge protection device 10 may be electrically connected to the first wire 110, for example, as a neutral wire; the left electrode structure 1 of the left surge protection device 10 may be electrically connected to the second wire 120, for example, as a first phase wire; the two electrode structures 1 of the middle surge protection device 10 may be electrically connected to the fourth wire 140 and the fifth wire 150, respectively, as the second and third phase wires. This electrical equipment 100 can be designed based on a three-phase four-wire configuration.

[0074] refer to Figure 11 The electrical equipment 100 can be designed based on a three-phase five-wire configuration. The electrical equipment 100 includes a first wire 110, a second wire 120, a third wire 130, a fourth wire 140, and a fifth wire 150, and may also include, for example, four surge protection devices 10. The five external contacts formed by the four surge protection devices 10 are electrically connected to the third wire 130, the fourth wire 140, the fifth wire 150, the second wire 120, and the first wire 110. The surge protection devices 10 provide surge protection for downstream circuits.

[0075] refer to Figure 12 This application provides a method 2000 for manufacturing a surge protection device. The method 2000 for manufacturing a surge protection device includes steps S210 and S220.

[0076] Combination Figure 1In step S210, the wafer 3 is electrically connected to the corresponding electrode structure 1. Specifically, each of the pair of wafers 3 is electrically connected to one of the two adjacent electrode structures 1.

[0077] In step S220, two electrode structures 1 are sealed and connected to the housing structure 2. An internal space is defined within the housing structure 2. A gap exists between the two electrode structures 1, allowing a pair of wafers 3 to be disposed within the housing structure 2. Each pair of wafers 3 partially overlaps and has a gap.

[0078] The method 2000 for manufacturing surge protection devices of this application is capable of producing surge protection devices 10 with high current capacity and high voltage resistance.

[0079] A method 2000 for manufacturing a surge protection device may include: step S230, forming a wafer 3; step S240, forming an electrode structure 1; and step S250, forming a housing structure. Steps S230 and S240 may be performed before step S210, and step S250 may be performed before step S220. The steps of forming each structure may be performed separately or simultaneously.

[0080] The steps for forming wafer 3 include: slicing the single crystal and chemical mechanical polishing. In this application, each step can be performed based on a precursor structure, and the structure obtained in each step can be referred to as the precursor structure for the next step. Exemplarily, the steps for forming wafer 3 include: forming a photolithographic surface 301 using a photolithography process. The photolithographic surface 301 differs from other surfaces of wafer 3 and can effectively achieve insulation and short circuit protection during large surges. Step S230 may further include: after the photolithography process, annealing wafer 3 in an argon atmosphere at 500°C for 1 hour. Wafer 3 can maintain a good morphology and effectively provide surge protection during surges.

[0081] The step of forming electrode structure 1 may include depositing an insulating and heat-dissipating structure 12 on the surface of electrode 11.

[0082] The wafer 3 can be electrically connected to the electrode structure 1 using wire bonding processes, etc.

[0083] The steps of forming the housing structure 2 may include forming a silicon frame 21, forming a silicon carbide frame 22, and fitting the silicon carbide frame 22 onto the silicon frame 21. The step of forming the silicon frame 21 may include treating the silicon frame 21 at 700°C to 900°C for 0.5 to 1 hour. For example, annealing the silicon frame 21 at 800°C for 0.5 hours. The step of forming the silicon carbide frame 22 may include treating the silicon carbide frame 22 at 1700°C to 2100°C for 0.5 to 1 hour. For example, annealing the silicon carbide frame 22 at 1900°C for 0.5 hours. The step of fitting the silicon carbide frame 22 onto the silicon frame 21 may include heating to soften at least one surface of the silicon frame 21 and the silicon carbide frame 22, and then fitting the frames together based on the softened surfaces. The silicon frame 21 and the silicon carbide frame 22 provide composite protection, making the housing structure 2 structurally stable and preventing stress damage.

[0084] In other embodiments, the material of the housing structure 2 includes aluminum nitride.

[0085] The housing structure 2 can be sealed and connected to the electrode structure 1 by adhesive bonding. Encapsulation can be performed in an inert gas environment, filling the internal space 201 of the housing structure 2 with inert gas.

[0086] The technical features of the above-disclosed embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] In the embodiments disclosed above, unless otherwise explicitly specified and limited, the execution order of each step is not restricted. For example, they can be executed in parallel or sequentially in different orders. The sub-steps of each step can also be executed alternately. Various forms of processes described above can be used, and steps can be reordered, added, or deleted, as long as the desired result of the technical solution provided in this application can be achieved, and this application does not impose any restrictions here.

[0088] The embodiments disclosed above merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of patent protection claimed by this application. Therefore, the scope of patent protection of this application should be determined by the appended claims.

Claims

1. A surge protection device, characterized by include: At least two electrode structures are arranged sequentially, with a gap between adjacent two electrode structures; At least one housing structure, each housing structure being respectively sealed to two adjacent electrode structures, the housing structure defining an internal space; and At least one pair of wafers, each pair of wafers being disposed within the housing structure, each wafer in each pair being electrically connected to one of the corresponding electrode structures in two adjacent electrode structures, and each pair of wafers partially overlapping and having a gap.

2. The surge protection device of claim 1, wherein, The spacing ranges from 50 μm to 200 μm; the surface of the overlapping area of ​​the wafer includes a photolithographic surface.

3. The surge protection device of claim 2, wherein, The thickness of the wafer ranges from 600 μm to 800 μm; the depth of the photolithographic surface recessed into the wafer ranges from 100 μm to 200 μm.

4. The surge protection device of claim 1, wherein, The overlapping area of ​​each pair of wafers is less than half the area of ​​any one of the wafers.

5. The surge protection device according to claim 4, characterized in that, The diameter of the wafer ranges from 1 mm to 3 mm; The wafer is a single-crystal silicon wafer.

6. The surge protection device according to claim 1, characterized in that, The electrode structure has a groove on its outer periphery, and the electrode structure is sealed to the housing structure by adhesive bonding.

7. The surge protection device according to claim 1, characterized in that, The electrode structure includes an electrode and an insulating heat dissipation structure. The electrode is electrically connected to the corresponding wafer and is used for external connection. The insulating heat dissipation structure covers a portion of the electrode.

8. The surge protection device according to claim 7, characterized in that, The electrode is an aluminum electrode, and the insulating and heat dissipation structure is an aluminum oxide layer; The gas contained within the shell is an inert gas.

9. The surge protection device according to any one of claims 1 to 8, characterized in that, The housing structure includes a silicon frame and a silicon carbide frame fitted onto the silicon frame.

10. Electrical equipment, characterized in that, include: First wire; The second wire is used to transmit current with the first wire and has a voltage difference with the first wire; as well as At least one surge protection device as described in any one of claims 1 to 9 is connected between the first wire and the second wire.

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