A high-power transient tube integrated structure
By integrating high-power transient transistors into a single structure and using interleaved packaging of chip A, chip B, and CLIP chips, the problems of insufficient protection capability and large space occupation of a single transient transistor are solved, achieving high reliability, low cost overvoltage protection, and synchronous fast response.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHINA ZHENHUA GRP YONGGUANG ELECTRONICS CO LTD STATE OWNED NO 873 FACTORY
- Filing Date
- 2025-06-17
- Publication Date
- 2026-06-26
AI Technical Summary
Existing single transient transistors have limited protection capabilities and are unable to cope with complex and high-intensity transient overvoltage impacts. Multiple transient transistors occupy a lot of space in electronic devices and increase production costs and failure probability, and cannot achieve synchronous and rapid response.
It adopts a high-power transient transistor integrated structure, and forms multiple U-shaped circuits through the interleaved packaging of chip A, chip B and CLIP chip to achieve electrical isolation and protection of the chip. It has high integration, small size and light weight. It uses conductive glue and CLIP chip to connect and form a high reliability protection structure.
It improves the overvoltage protection performance of electronic equipment, reduces space occupation, lowers production costs, increases production efficiency, and achieves a synchronous and rapid overall protection effect.
Smart Images
Figure CN224419172U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power diode array integration technology, further to the field of power transient transistor array integration technology, and particularly to a high-power transient transistor integrated structure. Background Technology
[0002] In today's rapidly developing electronic information age, various electronic devices such as smartphones, laptops, automotive electronic systems, and industrial control equipment are playing an increasingly important role in people's lives and production. These electronic devices have highly precise and complex internal circuits, and at the same time, they face various threats from external electromagnetic interference and transient overvoltages.
[0003] Transient transistors, as a key overvoltage protection device, can clamp excessively high voltages within a safe range for a very short time, thereby protecting electronic equipment from damage caused by transient overvoltages. However, existing single transient transistor suppression solutions have many limitations.
[0004] From a performance perspective, the protection capability of a single transient transistor is limited, making it difficult to cope with some complex and high-intensity transient overvoltage surges. For example, during thunderstorms, the surge voltage generated by induced lightning may exceed the withstand range of a single transient transistor. If multiple independently used transient transistors have different response speeds, they cannot achieve synchronized and rapid response, resulting in poor overall protection.
[0005] In terms of space utilization, as electronic devices continue to become smaller and thinner, strict requirements are placed on the space occupied by internal components. Multiple discrete transient transistors occupy a large amount of circuit board space, hindering the further miniaturization of electronic devices.
[0006] From the perspective of cost and production efficiency, using multiple independent transient transistors will increase the assembly process, increase labor and time costs, and also increase the probability of failure due to improper assembly.
[0007] In view of the above situation, in order to meet the urgent needs of electronic devices for high-performance, high-reliability overvoltage protection as well as miniaturization and low cost, this application is committed to achieving the synergistic operation between transient transistors through innovative circuit layout design and advanced plastic packaging technology, thereby improving the overall overvoltage protection performance, while effectively reducing space occupation, lowering production costs, and improving production efficiency, thus providing a better solution for overvoltage protection of electronic devices. Summary of the Invention
[0008] The purpose of this application is to provide an integrated structure for high-power transient transistors to address the shortcomings of existing technologies, thereby improving the overall overvoltage protection performance of electronic devices, while effectively reducing space occupation, lowering production costs, and increasing production efficiency.
[0009] Therefore, this application proposes an integrated structure for high-power transient transistors, such as... Figure 1-10 As shown. Includes:
[0010] Includes sheet material A, sheet material B, and CLIP sheet.
[0011] The sheet A includes connecting ribs, pins, and a bonding area; the connecting ribs connect multiple pins, and the left pin between two opposite pins is fixedly connected to the bonding area.
[0012] The chip B includes connecting ribs, leads, and a chip bonding area. The connecting ribs connect multiple leads, and the right lead between two leads is fixedly connected to the chip bonding area.
[0013] The CLIP end of the CLIP chip is fixedly connected to the chip connection area.
[0014] Each pin of the aforementioned material A is bent twice to form a bending platform, forming a U-shaped loop structure between two pins, and a through hole is provided on the bending platform.
[0015] The aforementioned material piece B extends perpendicularly to the left and right pins of the two pins in opposite directions, forming a U-shaped loop structure, and has a through hole in the horizontal section between the two right-angle turns.
[0016] A through hole is provided at the fixed connection point between the left pin of the aforementioned die A pin and the bonding area, and a through groove is provided between the bonding area and the right pin to keep them spaced apart and not directly connected; this enables the front side of the chip to be connected to the connection end after bonding, thus electrically isolating the bonding area from the connection end.
[0017] A through hole is provided at the fixed connection point between the right pin of the B pin of the aforementioned die and the bonding area, and a through groove is provided between the bonding area and the left pin to keep them spaced apart and not directly connected; this enables the front side of the chip to be connected to the connection end after the die is bonded, thereby electrically isolating the bonding area from the connection end.
[0018] The aforementioned bonding areas all have raised steps, which are used to ensure that the conductive adhesive only covers the central area of the back of the chip during chip bonding, while the surrounding edges are kept at a distance from the conductive adhesive to protect the glass passivation layer on the back of the chip; the raised steps are bonded to the chip by conductive adhesive.
[0019] The aforementioned CLIP chip includes a clip end and a chip connection area, characterized in that there is a through hole between the clip end and the chip connection area, and the chip is connected to the connection end via the CLIP chip.
[0020] The chip connection area has a recessed step, which is used so that after the CLIP chip is attached, the conductive adhesive is only bonded to the center of the front of the chip, while the spacing around the perimeter is increased and the conductive adhesive is not bonded, in order to protect the glass passivation layer on the front edge of the chip.
[0021] The aforementioned connecting ribs all have multiple round or waist-shaped holes.
[0022] The encapsulation structure includes controlling the positions of sheet A and sheet B through limiting grooves and positioning pins in the molding die, so that sheet A and sheet B form an interleaved encapsulation structure. The sheet A and sheet B are encapsulated in an interleaved manner, and there is a gap between sheet A and sheet B after encapsulation.
[0023] In use, apply conductive adhesive to each bonding area of sheet A and sheet B, and then glue the chip to the raised step of the bonding area. After fixing, apply conductive adhesive to the upper surface of each chip and the connection end of sheet A and sheet B, and then fix multiple clips to the chip clips and attach them to the connection end.
[0024] After being glued and fixed, sheet A and sheet B are placed symmetrically on the molding die, with sheet B on the lower layer and sheet A on the upper layer. After being placed in the molding die, the bonding areas of sheet A and sheet B are perpendicular to each other. The molding die limits the bonding to achieve staggered molding with gaps between sheet A and sheet B.
[0025] The beneficial effects of this application are as follows: the chip is glued at the bonding position, and the two pins are connected together by the CLIP chip to form a U-shaped circuit. The chip A and chip B are encapsulated in an interleaved plastic structure to form multiple U-shaped circuits. This structure has high integration, small size, light weight, strong instantaneous overload capacity, high reliability, and plays a protective role in electronic circuits. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the product's circuit structure.
[0027] Figure 2 This is a schematic diagram of the shape of the product's packaging shell.
[0028] Figure 3 This is a schematic diagram of the structure of material A.
[0029] Figure 4 This is a schematic diagram of the structure of material sheet B.
[0030] Figure 5 This is a schematic diagram of the CLIP chip structure.
[0031] Figure 6 This is a schematic diagram of the assembly of component A, chip, and CLIP chip.
[0032] Figure 7 This is a schematic diagram of sheet A after assembly.
[0033] Figure 8 This is a schematic diagram of the assembly of component B, chip, and CLIP.
[0034] Figure 9 This is a schematic diagram of sheet B after assembly.
[0035] Figure 10 This is a schematic diagram of the overall structure of the staggered plastic sealing system.
[0036] In the diagram: 1 is sheet A, 10 is the connecting rib of sheet A, 11 is the positioning hole of the connecting rib of sheet A, 12 is the lead of sheet A, 13 is the through hole of the bending platform of sheet A, 14 is the through hole of the connecting end of sheet A, 15 is the bonding area of sheet A, 16 is the through groove of sheet A, 17 is the connecting end of sheet A, 18 is the bending platform of sheet A, 19 is the raised step of the bonding area of sheet A, 2 is sheet B, 20 is the connecting rib of sheet B, 21 is the positioning hole of the connecting rib of sheet B, and 22 is the lead of sheet B. 23 is the through hole of the bending platform of sheet B, 24 is the through hole of the connecting end of sheet B, 25 is the bonding area of sheet B, 26 is the through groove of sheet B, 27 is the connecting end of sheet B, 28 is the raised step of the bonding area of sheet B, 3 is the CLIP sheet, 31 is the chip connection area, 32 is the clip end, 33 is the through hole of the CLIP sheet, 34 is the recessed step of the chip connection area of the CLIP sheet, 4 is the molding compound, 40 is the sheet gap, 5 is chip A, and 6 is chip B. Detailed Implementation
[0037] The following embodiments are proposed for this high-power transient transistor integrated structure:
[0038] like Figures 3 to 10 As shown, this application provides an integrated structure for a high-power transient transistor, comprising:
[0039] The chip includes a substrate A, a substrate B, and a CLIP chip. Substrate A includes a connecting rib 10, pins 12, and a bonding area 15. The connecting rib 10 connects multiple pins 12, and the left pin between two opposite pins 12 is fixedly connected to the bonding area 15. Substrate B includes a connecting rib 20, pins 22, and a bonding area 25. The connecting rib 20 connects multiple pins 22, and the right pin between two opposite pins 22 is fixedly connected to the chip bonding area 25. The CLIP chip has a CLIP terminal 32 fixedly connected to a chip connection area 31.
[0040] In the above-mentioned material A, a circuit is formed between every two pins 12. The left pin 12 is connected to the bonding area 15 for bonding the chip, and the right pin 12 is connected to the end 17 for connecting to the clip end 32 after soldering. After production, every two pins between products form an independent U-shaped circuit, which can independently protect a channel or a line, or protect a channel or a line together with other U-shaped circuits of this structure, achieving synchronous and fast response and better overall protection effect.
[0041] The aforementioned component B forms a circuit between every two pins 22. The right pin 22 connects to the die bonding area 25 for chip bonding, and the left pin 22 connects to the clip terminal 32 after soldering. After production, every two pins form an independent U-shaped loop, which can independently protect a channel or a line, or protect a channel or a line together with other U-shaped loops of the same structure, achieving synchronous and rapid response and better overall protection.
[0042] Furthermore, to accommodate installation needs of different sizes, the aforementioned fixing connections can be integrally molded or welded.
[0043] Each pin 12 of material A is bent twice to form a bending platform 18, forming a U-shaped loop structure between two pins 12, and a through hole 13 is provided on the bending platform 18. The function of the through hole 13 is to enhance the longitudinal strength of the molded body after molding.
[0044] During the molding process, sheet A and sheet B are packaged in staggered layers with a gap in between; there is a through hole 13 at the center of each bend 18 to enhance the longitudinal structural strength of the molded body after molding.
[0045] Furthermore, to accommodate installation requirements of different sizes, the angle α formed by the bending platform and pin 12 is 30°≤α≤120°, preferably 80°≤α≤100°.
[0046] Material B extends perpendicularly to the left and right pins 22 in opposite directions to form a U-shaped loop structure. A through hole 23 is provided on the horizontal section between the two right-angle turns to enhance the vertical strength of the encapsulated body after encapsulation.
[0047] A through hole 14 is provided at the fixed connection point between the left pin of the aforementioned pin 12 and the bonding area 15 to enhance the vertical strength of the molded body after molding. A through groove 16 is provided between the bonding area 15 and the right pin to ensure conductivity between the front side of the chip and the connection terminal 17 after bonding, preventing short circuit between the back side of the chip and the connection terminal 17. The through groove 16 does not exceed 1 mm.
[0048] A through-hole 24 is provided at the fixed connection point between the right pin of pin 22 and the bonding area 25 to enhance the vertical strength of the molded body after molding. A through-slot 26 is provided between the bonding area 25 and the left pin to ensure conductivity between the front side of the chip and the connection terminal 27 after bonding, preventing short circuit between the back side of the chip and the connection terminal 27. The distance between the through-slots 26 does not exceed 1 mm.
[0049] The aforementioned bonding areas 15 / 25 all have raised steps 19 / 28. The area of the raised platform is adapted to the bonding area of chip A / 2. This is to ensure that the conductive adhesive is only bonded to the center of the back of the chip after bonding, and the spacing around the perimeter is increased so that the conductive adhesive is not bonded, thus protecting the glass passivation layer on the back edge of the chip.
[0050] The aforementioned bonding areas 15 / 25 all use conductive adhesive to bond chip A / 2.
[0051] The aforementioned chip A / 2 is connected to the connector 17 / 27 via a CLIP chip. Preferably, chip A / 2 is bonded to the CLIP chip connection area 31 using conductive adhesive. Each chip connection area 31 has a recessed step 34, which allows the conductive adhesive to adhere only to the center of the chip's front side after the CLIP chip is attached, with the surrounding area spaced further apart to protect the glass passivation layer at the chip's front edge. The CLIP terminal 32 is bonded to the connector 17 / 27 using conductive adhesive, achieving the chip-on connection.
[0052] The aforementioned connecting ribs 10 / 20 each have multiple round holes or oblong holes 11 / 21. During installation, material pieces A and B are fixed by inserting the positioning pins of the operating platform into the round holes or oblong holes 11 / 21.
[0053] like Figure 10 As shown, sheet A and sheet B are encapsulated in an alternating manner, with a gap of 40 between them after encapsulation. Preferably, sheet A and sheet B are integrally injection molded after their partial structures are interlocked, with the gap of 40 providing insulation between the interlocked partial structures.
[0054] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This application includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all implementation methods. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this application fall within the protection scope of this application.
Claims
1. A high-power transient transistor integrated structure, characterized in that: The device includes a chip A, a chip B, and a CLIP chip. The chip A includes a chip A connecting rib (10), a chip A pin (12), and a chip A bonding area (15). The chip A connecting rib (10) connects multiple chip A pins (12), and the left pin between two chip A pins (12) is fixedly connected to the chip A bonding area (15). The chip B includes a chip B connecting rib (20), a chip B pin (22), and a chip B bonding area (25). The chip B connecting rib (20) connects multiple chip B pins (22), and the right pin between two chip B pins (22) is fixedly connected to the chip B bonding area (25). The CLIP chip has a CLIP end (32) fixedly connected to a chip connection area (31).
2. The high-power transient transistor integrated structure as described in claim 1, characterized in that, Each of the material sheet A pins (12) is bent twice to form a material sheet A bending platform (18), and a U-shaped loop structure is formed between the two material sheet A pins (12), and a material sheet A bending platform through hole (13) is provided on the material sheet A bending platform (18).
3. The high-power transient transistor integrated structure as described in claim 1, characterized in that, The material piece B extends perpendicularly in opposite directions to the left material piece B pin (22) and the right material piece B pin (22) respectively, forming a U-shaped loop structure, and a material piece B bending platform through hole (23) is provided on the horizontal section between the two right-angle turns.
4. The high-power transient transistor integrated structure as described in claim 1, characterized in that, A through hole (14) for connecting the left pin of the chip A pin (12) and the chip A bonding area (15) is provided. A through groove (16) for chip A is provided between the chip A bonding area (15) and the right pin, so that the front of the chip is connected to the chip A bonding end (17) after bonding, and the chip A bonding area (15) and the chip A bonding end (17) are electrically isolated.
5. The high-power transient transistor integrated structure as described in claim 1, characterized in that, A through hole (24) for the connecting end of the chip B is provided at the fixed connection point between the right pin of the chip B pin (22) and the bonding area (25) of the chip B. A through groove (26) for the chip B is provided between the bonding area (25) of the chip B and the left pin, so that the front side of the chip is connected to the connecting end (27) of the chip B after bonding, and the bonding area (25) of the chip B and the connecting end (27) of the chip B are electrically isolated.
6. The high-power transient transistor integrated structure as described in claim 1, characterized in that, The bonding areas (15 / 25) all have raised steps (19 / 28) to ensure that the conductive adhesive only covers the central area of the back of the chip during chip bonding, while the surrounding edges are kept at a distance from the conductive adhesive to protect the glass passivation layer on the back of the chip. The raised steps (19 / 28) are bonded to the chip (5 / 6) by conductive adhesive.
7. The high-power transient transistor integrated structure as described in claim 1, wherein the CLIP chip includes a clip terminal (32) and a chip connection area (31), characterized in that, There is a CLIP through hole (33) between the clip end (32) and the chip connection area (31), and the chip (5 / 6) is connected to the connection end (17 / 27) through the CLIP.
8. The high-power transient transistor integrated structure as described in claim 7, characterized in that, The chip connection area (31) has a recessed step (34) so that after the CLIP chip is attached, the conductive adhesive is only bonded to the center of the front of the chip, while the spacing around the perimeter is increased and the conductive adhesive is not bonded, in order to protect the glass passivation layer on the front edge of the chip.
9. The high-power transient transistor integrated structure as described in claim 1, characterized in that, There are multiple through holes (11 / 21) on each of the connecting bars (10 / 20).
10. The high-power transient transistor integrated structure as described in claim 1, characterized in that, Material A and material B are encapsulated in an alternating manner, with a gap (40) between them after encapsulation.