A control motherboard fault detection device

Abstract

This invention provides a control board fault detection device, belonging to the field of control board testing technology. It solves the problems of existing detection methods, such as difficulty in comprehensively and synchronously detecting and analyzing multi-dimensional parameters, complex and cumbersome fault location processes, and extreme difficulty in diagnosing some hidden faults. This control board fault detection device includes a host computer, a main control chip U5 for acquiring the lithium battery voltage of the control board, a charge / discharge test circuit for controlling the power supply status of the charging port of the control board, a connector module for connecting to corresponding detection points on the control board, and a logic level detection circuit connected to the connector module for acquiring the level data of the corresponding detection points on the control board. Both the logic level detection circuit and the main control chip U5 are connected to the host computer, the charge / discharge test circuit is connected to the main control chip U5, and the main control chip U5 is connected to the connector module. This invention enables accurate detection of the control board.

Description

Technical Field

[0001] This utility model belongs to the field of control board testing technology and relates to a control motherboard fault detection device. Background Technology

[0002] With the continuous development of smart devices, the functions of their core control motherboards are becoming increasingly powerful and their integration is becoming higher and higher. This has led to the miniaturization and precision of the control motherboards and the components they contain. Against this backdrop, the fault detection and repair of control motherboards face many challenges.

[0003] Currently, the testing of control motherboards largely relies on manual operation of traditional equipment such as oscilloscopes. However, due to the small and densely distributed test points on the control motherboard, manual testing is not only inefficient but also prone to misjudgment due to operational errors, and may even cause secondary damage to components. Furthermore, traditional testing methods struggle to comprehensively and simultaneously detect and analyze multiple parameters of the control motherboard, such as its charging and discharging performance, logic level signals, and real-time heat dissipation status, making fault location complex and cumbersome, especially for diagnosing some hidden faults. Summary of the Invention

[0004] The purpose of this invention is to address the aforementioned problems in the existing technology by proposing a control motherboard fault detection device. The technical problem it aims to solve is: how to achieve accurate detection of the control motherboard.

[0005] The objective of this utility model can be achieved through the following technical solution: A control motherboard fault detection device, including a host computer, the control motherboard fault detection device further includes a main control chip U5 for acquiring the lithium battery voltage of the control motherboard, a charge and discharge test circuit for controlling the power supply status of the charging port of the control motherboard, a connector module for connecting to the corresponding detection point of the control motherboard, and a logic level detection circuit connected to the connector module for acquiring the level data of the corresponding detection point of the control motherboard. The logic level detection circuit and the main control chip U5 are both connected to the host computer, the charge and discharge test circuit is connected to the main control chip U5, and the main control chip U5 is connected to the connector module.

[0006] When performing fault detection on the control motherboard, the connector module is connected to the corresponding detection point on the control motherboard. The logic level detection circuit, main control chip U1, and charge / discharge test circuit are all connected to the connector module. The host computer is connected to both the logic level detection circuit and the main control chip U1. During testing, the host computer sends test commands to the logic level detection circuit and the main control chip U1. The logic level detection circuit collects the level data of the corresponding position on the control motherboard through the connector module and sends it to the host computer, which then determines whether there is a fault in each line of the control motherboard. The main control chip U1 controls the charge / discharge test circuit, thereby testing the charging line of the control motherboard through the connector module. The voltage detection interface of the main control chip U1 collects the voltage of the control motherboard through the connector module and sends it to the host computer, realizing voltage detection of the control motherboard. This device connects to various points on the control motherboard through the connector module to collect data, enabling comprehensive and multi-dimensional synchronous detection and analysis of the control motherboard's parameters. This allows maintenance personnel to locate the fault point more quickly and accurately, improving detection accuracy.

[0007] In the aforementioned control motherboard fault detection device, the device further includes an infrared thermal imaging camera for collecting temperature information of the control motherboard, and the infrared thermal imaging camera is connected to the host computer. The combination of the infrared thermal imaging camera and the host computer enables the identification of hot spots on the control motherboard.

[0008] In the aforementioned control motherboard fault detection device, the charging and discharging test circuit includes a transistor AQ1, a relay AK1, a light-emitting diode ALED1, and a diode AD1. The base of transistor AQ1 is connected to the main control chip U5 through resistor AR2, and the base of transistor AQ1 is connected to ground through resistor AR3. The emitter of transistor AQ1 is also connected to ground. Pin 1 of relay AK1 is connected to voltage VCC. The cathode of diode AD1 is connected to pin 1 of relay AK1, and the anode of diode AD1 is connected to pin 4 of relay AK1. The cathode of light-emitting diode ALED1 is connected to the anode of diode AD1, and the anode of light-emitting diode ALED1 is connected to the cathode of diode AD1 through resistor AR2. Pin 2 of relay AK1 is connected to the connector module, and pin 5 of relay AK1 is connected to the VBUS terminal of the main control chip U5. The main control chip U1 controls the switching of relay AK1 by controlling the on / off state of transistor AQ1, thereby detecting the power supply to the charging port of the control motherboard.

[0009] In the aforementioned control motherboard fault detection device, the logic level detection circuit includes a control chip U1, an isolation chip U4, a memory chip U3, resistor arrays RN1, RN2, RN3, and RN4. Both the isolation chip U4 and the memory chip U3 are connected to the control chip U1. Pins B1, B2, B3, and B4 of the isolation chip U4 are connected to pins at one end of resistor array RN1 and one end of resistor array RN3, respectively. Pins B5, B6, B7, and B8 of the isolation chip U4 are connected to pins at one end of resistor array RN2 and one end of resistor array RN4, respectively. The pins at the other end of resistor array RN3 are connected to voltage VCC, and the pins at the other end of resistor array RN4 are also connected to voltage VCC. The pins at the other ends of both resistor array RN3 and resistor array RN4 are connected to a connector module. Electrical isolation between the control chip U1 and the external interface is achieved through the isolation chip U4 and the connector module, effectively suppressing surges, EMI interference, and noise, improving the system's anti-interference capability, and protecting the core control chip from damage caused by abnormal external voltage. The memory chip U3 is mainly used for buffering level data.

[0010] In the aforementioned control motherboard fault detection device, the logic level detection circuit further includes a status indication module. This module comprises LED1, LED2, and LED3. The positive terminal of LED1 is connected to voltage VCC via resistor R5. The positive terminal of LED2 is connected to control chip U1 via resistor R6. The positive terminal of LED3 is connected to control chip U1 via resistor R9. The negative terminals of LED1, LED2, and LED3 are interconnected and grounded. The configuration of LEDs LED1, LED2, and LED3 allows for a direct visual indication of the connection and operating status of the logic level detection circuit.

[0011] In the aforementioned control motherboard fault detection device, the logic level detection circuit further includes a step-down chip U2 and a communication interface USB1. The control chip U1 is connected to the host computer via the communication interface USB1. The communication interface USB1 is connected to the VIN pin of the step-down chip U2 via a resistor F1. The VOUT pin of the step-down chip U2 outputs the stepped-down voltage VCC. The step-down chip U2 reduces the voltage at the communication interface USB1 to a suitable operating voltage for each chip, i.e., voltage VCC.

[0012] In the aforementioned control motherboard fault detection device, the connector module includes several probes connected to corresponding detection points on the control motherboard. The use of these probes enables repair personnel to detect minute points on the control motherboard, achieving precise fault detection.

[0013] Compared with existing technologies, this control motherboard fault detection device has the following advantages:

[0014] 1. This utility model integrates a logic level detection circuit, a charge / discharge test circuit, a host computer, a main control chip, and an infrared thermal imaging camera. It can simultaneously detect the signal integrity, power stability, charge / discharge function, and temperature distribution of the control motherboard, thereby achieving accurate detection and precise location of hardware faults in the control motherboard.

[0015] 2. The design of the isolation chip and probe connector module in this utility model not only ensures the safety of the test, but also supports the precise access of high-density test points, which significantly improves the efficiency and accuracy of the test. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the control structure of this utility model.

[0017] Figure 2 This is a schematic diagram of the detection circuit of this utility model.

[0018] In the diagram, 1 is the host computer; 2 is the charge / discharge test circuit; 3 is the connector module; 31 is the probe; 4 is the logic level detection circuit; 41 is the status indicator module; and 5 is the infrared thermal imaging camera. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be further described in detail below with reference to the accompanying drawings. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this utility model or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without inventive effort are within the scope of protection of this utility model.

[0020] like Figure 1 As shown, this control motherboard fault detection device includes a host computer 1, a main control chip U5 for acquiring the lithium battery voltage of the control motherboard, a charge / discharge test circuit 2 for controlling the power supply status of the charging port of the control motherboard, an infrared thermal imaging camera 5 for acquiring the temperature information of the control motherboard, a connector module 3 for connecting to the corresponding detection point of the control motherboard, and a logic level detection circuit 4 connected to the connector module 3 for acquiring the level data of the corresponding detection point of the control motherboard. The logic level detection circuit 4, the infrared thermal imaging camera 5, and the main control chip U5 are all connected to the host computer 1, the charge / discharge test circuit 2 is connected to the main control chip U5, and the main control chip U5 is connected to the connector module 3.

[0021] Among them, such as Figure 2As shown, the charge / discharge test circuit 2 includes transistor AQ1, relay AK1, LED ALED1, and diode AD1. The base of transistor AQ1 is connected to the main control chip U5 through resistor AR2, and the base of transistor AQ1 is connected to ground through resistor AR3. The emitter of transistor AQ1 is connected to ground. Pin 1 of relay AK1 is connected to voltage VCC. The cathode of diode AD1 is connected to pin 1 of relay AK1, and the anode of diode AD1 is connected to pin 4 of relay AK1. The cathode of LED ALED1 is connected to the anode of diode AD1, and the anode of LED ALED1 is connected to the cathode of diode AD1 through resistor AR2. Pin 2 of relay AK1 is connected to connector module 3, and pin 5 of relay AK1 is connected to the VBUS terminal of main control chip U5.

[0022] The logic level detection circuit 4 includes a control chip U1, an isolation chip U4, a storage chip U3, a status indicator module 41, resistor arrays RN1, RN2, RN3, and RN4, a step-down chip U2, and a communication interface USB1. The control chip U1 is connected to the host computer 1 via the communication interface USB1. The communication interface USB1 is connected to the VIN pin of the step-down chip U2 via a resistor F1. The VOUT pin of the step-down chip U2 outputs the stepped-down voltage VCC. The VIN pin of the step-down chip U2 is also connected to ground via a capacitor C3. The isolation chip U4, the status indicator module 41, the isolation chip U4, the isolation chip U4, the storage chip U3, the status indicator module 41, the isolation chip U4, the isolation chip U4, the storage ... Block 41 and memory chip U3 are both connected to control chip U1. Pins B1, B2, B3 and B4 of isolation chip U4 are connected to the pins of one end of resistor array RN1 and the pins of one end of resistor array RN3. Pins B5, B6, B7 and B8 of isolation chip U4 are connected to the pins of one end of resistor array RN2 and the pins of one end of resistor array RN4. The pins of the other end of resistor array RN3 are connected to voltage VCC. The pins of the other end of resistor array RN4 are connected to voltage VCC. The pins of the other end of resistor array RN3 and the other end of resistor array RN4 are both connected to connector module 3. The status indication module 41 includes LED1, LED2 and LED3. The positive terminal of LED1 is connected to the voltage VCC through resistor R5. The positive terminal of LED2 is connected to the control chip U1 through resistor R6. The positive terminal of LED3 is connected to the control chip U1 through resistor R9. The negative terminals of LED1, LED2 and LED3 are connected to each other and then grounded.

[0023] The connector module 3 includes several probes 31 that are connected to the corresponding detection points on the control motherboard.

[0024] The logic level detection circuit 4, the main control chip U1, and the charge / discharge test circuit 2 in this control motherboard fault detection device constitute a fault detection circuit. The logic level detection circuit 4 is connected to the host computer 1 through the communication interface USB1, and the main control chip U1 is connected to the host computer 1 through its own USB interface. The logic level detection circuit 4, the main control chip U1, and the charge / discharge test circuit 2 are all connected to the connector module 3. The infrared thermal imaging camera 5 is placed on top of the control motherboard and is connected to the host computer 1. When performing fault detection on the control motherboard, each probe 31 in the connector module 3 is connected to the corresponding detection point on the control motherboard. During the detection, the host computer 1 sends detection commands to the logic level detection circuit 4 and the main control chip U1 respectively. The logic level detection circuit 4 collects the level data of the corresponding position on the control motherboard through the connector module 3 and sends it to the host computer 1, which then determines whether there is a fault in each line of the control motherboard. The main control chip U1 controls the charge and discharge test circuit 2, thereby testing the charging line of the control motherboard through the connector module 3. The voltage detection interface of the main control chip U1 collects the voltage of the control motherboard through the connector module 3 and sends it to the host computer 1, realizing the voltage detection of the control motherboard. The infrared thermal imaging camera 5 collects the temperature of the control motherboard and sends it to the host computer 1, thereby locating the abnormal heat point of the control motherboard. This device collects data from each point on the control motherboard through the probes 31, realizing the synchronous detection and analysis of comprehensive multi-dimensional parameters of the control motherboard, enabling maintenance personnel to locate the fault point more quickly and accurately, with high detection accuracy.

[0025] The specific embodiments described herein are merely illustrative examples illustrating the spirit of this utility model. Those skilled in the art to which this utility model pertains may make various modifications or additions to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of this utility model or exceeding the scope defined by the appended claims.

Claims

1. A control mainboard fault detection device, comprising a host computer (1), characterized in that, The control motherboard fault detection device also includes a main control chip U5 for collecting the lithium battery voltage of the control motherboard, a charge and discharge test circuit (2) for controlling the power supply status of the charging port of the control motherboard, a connector module (3) for connecting to the corresponding detection point of the control motherboard, and a logic level detection circuit (4) connected to the connector module (3) for collecting the level data of the corresponding detection point of the control motherboard. The logic level detection circuit (4) and the main control chip U5 are both connected to the host computer (1). The charge and discharge test circuit (2) is connected to the main control chip U5, and the main control chip U5 is connected to the connector module (3). The control motherboard fault detection device also includes an infrared thermal imaging camera (5) for collecting the temperature information of the control motherboard. The infrared thermal imaging camera (5) is connected to the host computer (1).

2. The control main board failure detection apparatus according to claim 1, characterized by, The charge / discharge test circuit (2) includes a transistor AQ1, a relay AK1, a light-emitting diode ALED1, and a diode AD1. The base of the transistor AQ1 is connected to the main control chip U5 through a resistor AR2. The base of the transistor AQ1 is connected to ground through a resistor AR3. The emitter of the transistor AQ1 is connected to ground. Pin 1 of the relay AK1 is connected to the voltage VCC. The cathode of the diode AD1 is connected to pin 1 of the relay AK1. The anode of the diode AD1 is connected to pin 4 of the relay AK1. The cathode of the light-emitting diode ALED1 is connected to the anode of the diode AD1. The anode of the light-emitting diode ALED1 is connected to the cathode of the diode AD1 through a resistor AR2. Pin 2 of the relay AK1 is connected to the connector module (3). Pin 5 of the relay AK1 is connected to the VBUS terminal of the main control chip U5.

3. The control mainboard failure detection apparatus according to claim 2, characterized by, The logic level detection circuit (4) includes a control chip U1, an isolation chip U4, a storage chip U3, a resistor array RN1, a resistor array RN2, a resistor array RN3, and a resistor array RN4. The isolation chip U4 and the storage chip U3 are both connected to the control chip U1. Pins B1, B2, B3, and B4 of the isolation chip U4 are connected to pins at one end of the resistor array RN1 and pins at one end of the resistor array RN3. Pins B5, B6, B7, and B8 of the isolation chip U4 are connected to pins at one end of the resistor array RN2 and pins at one end of the resistor array RN4. The pins at the other end of the resistor array RN3 are connected to the voltage VCC. The pins at the other end of the resistor array RN4 are connected to the voltage VCC. The pins at the other end of the resistor array RN3 and the other end of the resistor array RN4 are both connected to the connector module (3).

4. The control main board failure detection apparatus according to claim 2 or 3, characterized by, The logic level detection circuit (4) further includes a status indication module (41), which includes LED1, LED2 and LED3. The positive terminal of LED1 is connected to voltage VCC through resistor R5. The positive terminal of LED2 is connected to control chip U1 through resistor R6. The positive terminal of LED3 is connected to control chip U1 through resistor R9. The negative terminals of LED1, LED2 and LED3 are connected to each other and then grounded.

5. The control mainboard failure detection apparatus according to claim 3, wherein The logic level detection circuit (4) also includes a step-down chip U2 and a communication interface USB1. The control chip U1 is connected to the host computer (1) through the communication interface USB1. The communication interface USB1 is connected to the VIN pin of the step-down chip U2 through the resistor wire F1. The step-down chip U2 outputs the stepped-down voltage VCC through its VOUT pin.

6. The control mainboard failure detection apparatus according to claim 1, wherein The connector module (3) includes several probes (31) that are connected to the corresponding detection points of the control motherboard.

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