HYBRID DOUBLE STRUCTURING METHOD FOR SEMICONDUCER MANUFACTURING

Abstract

Method (200) for manufacturing an integrated circuit IC with a first lithography technique having a first resolution, and a second lithography technique different from the first lithography technique having a second resolution which is lower than the first resolution; the method (200) comprising the following steps: providing (202) a layout of the IC, wherein the layout comprises a set of IC structures;Deriving (204) a graph from the layout, wherein the graph has nodes and edges connecting some of the nodes, wherein the nodes represent the IC structures, wherein the edges are classified into at least two types, wherein a first type of edge connects two nodes that are to be structured separately using the first and second lithography techniques and represents distances that are smaller than the first resolution, wherein a second type of edge connects two nodes that are to be structured in the same process using the first lithography technique or are to be structured separately using the first and second lithography techniques and represents distances that are greater than or equal to the first resolution but smaller than the second resolution;Assigning (212) colors X and Y to all nodes connected by edges of the first type, assigning different colors to any two nodes connected by a common edge of the first type; identifying (214) a network of nodes connected by edges of the first type; checking (214) whether there are two such pairs of nodes in the network, such that a first pair is assigned the same color X and is directly connected by an edge of the second type, and a second pair is assigned the same color Y and is directly connected by another edge of the second type; if two such pairs are found, modifying (210) the layout to prevent two such pairs;and dissecting, using a computer-aided IC tool, the nodes into a first subset and a second subset, wherein the IC structures corresponding to the first subset are to be structured on a wafer using the first lithography technique, and the IC structures corresponding to the second subset are to be structured on the wafer using the second lithography technique.;

Description

PRIOR ARTThe semiconductor integrated circuit (IC) industry has experienced very rapid growth. The functional density (i.e., the number of interconnected devices per chip area) has fundamentally increased during IC development, while the geometric size (i.e., the smallest component (or trace) that can be generated using a fabrication process) has become smaller. This miniaturization process (scaling) provides advantages in principle by increasing production efficiency and lowering the costs associated therewith. Such miniaturization also has caused an increase in the complexity of processing and manufacturing ICs, and similar advances in IC manufacturing are required to implement these developments. For example, as the geometric sizes are reduced, it becomes fundamentally difficult for conventional photolithography processes to form semiconductor features having these small sizes. One approach to this problem uses a double structure (DP) method. A typical DP method splits an IC layout into two subsets and fabricates a photomask for each subset. A wafer is patterned with the two photomasks in two lithographic processes. Images of the two lithographic processes are overlaid on each other to collectively form a denser image on the wafer. In conventional DP methods, the two lithographic processes have the same resolution, which in some cases limits the minimum critical dimension (CD) that can be generated by the DP methods. Improvements in these fields are desired.U.S. Pat. No. 6,894,762 B1, U.S. Pat. No. 2012 / 0 137 261 A1, U.S. Pat. No. 2016 / 0 292 345 A1 and U.S. Pat. No. 2013 / 0 074 018 A1 describe conventional layout methods.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to the standard industry method, various features are not drawn to scale and are used for illustrative purposes only. Rather, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a simplified block diagram of an embodiment of an integrated circuit (IC) fabrication system and associated IC fabrication flow that may benefit from aspects of the present disclosure. FIGS. 2A, 2B, 2C, and 2D show a flow diagram of a method of manufacturing an IC according to various aspects of the present disclosure. FIG. 3A shows an example of an IC layout in accordance with aspects of the present disclosure. FIG. 3B shows a graph representing the IC layout of FIG. 3A, according to an embodiment. FIG. 3C illustrates a process for ranking edges in a graph, in accordance with aspects of the present disclosure FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, 4L, 4M, 4N, 4O, and 4P schematically illustrate some operations of the method of FIGS. 2A to 2D, in accordance with some embodiments. FIG. 5 shows a block diagram of a computerized IC tool for performing operations of the method of FIGS. 2A-2D, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments, or examples, for implementing different features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or embodiments discussed.Moreover, terms relating to spatial relativeity, such as "below," "below," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature (to other elements or features) as depicted in the figures. The terms relating to spatial relativeness are intended to encompass different orientations of the device being used or operated in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or otherwise oriented) and the spatially relative terms used herein may likewise be construed accordingly.The present disclosure generally relates to an IC design and fabrication in various embodiments. More particularly, the present disclosure relates to using hybrid dual structure (DP) processes for IC fabrication. In hybrid double patterning, an IC layout is decomposed into two subsets, and each of the two subsets appears in a photomask layer (or a masking layer) in a data file. The data file is then used to make photomasks or converted to direct write data structures for maskless lithography. Two photomasks (or a photomask and a direct write data structure) corresponding to the two subsets are then used in two different lithographic techniques to pattern a wafer together. As used herein, a photomask (or mask or reticle) is an apparatus used in photolithography (or lithography), such as a deep ultraviolet (DUV) lithography plate, having a fused silica substrate with a patterned chromium layer, while a photomask layer is a data file (such as GDS file) used to fabricate a photomask.Using two photomasks in two different lithography techniques to pattern a same wafer layer distinguishes hybrid double patterning from conventional double patterning using the same lithography technique to accomplish the task. For example, hybrid double structuring may use EUV (extreme ultraviolet radiation) lithography to generate a first subset of structures and use 193 nm immersion lithography to generate a second subset of structures. In various embodiments, the two lithographic techniques in hybrid double structuring may be any two of: EUV lithography, high numerical aperture EUV lithography (high NA); ultraviolet lithography using a wavelength of 436 nm, 405 nm or 365 nm; DUV lithography using a wavelength of 248 nm, 193 nm or 157 nm; immersion lithography; E-beam; and other available lithography techniques. Rather, in the case of electron beam lithography (which represents maskless lithography), the "photomask" is in the form of a direct write data structure rather than a physical device.Of the two lithography techniques, for convenience of discussion, one having a higher resolution is referred to as L1 lithography or simply "L1", and the other is referred to as L2 lithography or simply "L2". In addition, it is generally understood that a higher (lower) resolution means a lower (larger) resolution. In other words, L1 may generate (or resolve) smaller feature sizes than L2. For example, L1may have a resolution of 13.5 nm, while L2may have a resolution of 45 nm.Hybrid double-patterning lithography offers some advantages over conventional double-patterning lithography. In an example where L1 has a higher resolution than the lithographic techniques of conventional double-patterning lithography, the overall resolution of the hybrid double-patterning may be higher (better) than the conventional double-patterning lithography. In another example, where L2 is lower in resolution but lower in cost than the lithographic techniques of conventional dual-patterning lithography, the overall cost of hybrid dual-patterning may be lower (better) than the conventional dual-patterning lithography.However, there are also challenges associated with hybrid double-patterning lithography. One challenge is that breaking down an IC layout into two subsets suitable for two different lithography techniques may be difficult because it is no longer a simple 2-colorability problem. In the discussion below, the present disclosure provides some innovative 2-colorability methods to effectively address this challenge. The provided methods may be performed at a design stage by designers and / or layout engineers. Alternatively or additionally, they may be performed at a later stage after the design stage, for example, by a foundry at a manufacturing stage.FIG. 1 is a simplified block diagram of an embodiment of an integrated circuit (IC) fabrication system 100 and an associated IC fabrication flow that may benefit from various aspects of the provided subject matter. The IC fabrication system 100 includes multiple units, such as a design house 120, a mask house 130, and an IC manufacturer 150 (i.e., a microchip factory), that cooperate with one another in design, development, and manufacturing cycles and / or services related to the fabrication of an IC device 160. The plurality of entities are connected using a communication network, which may be a single network or a plurality of different networks, such as an intranet and the Internet, and which may include wired and / or wireless communication channels. Each entity may interact with other entities and may provide services to and / or receive services from the other entities. One or more of the design house 120, the mask house 130, and the IC manufacturer 150 may be owned by separate companies or a single company, and may even coexist in a common facility and use common resources.The design house (or design team) 120 creates an IC design layout (or IC layout) 122. The IC design layout 122 includes various geometric structures (e.g., polygons) designed for the IC device 160. The geometric structures correspond to IC features in one or more semiconductor layers forming the IC device 160. Examples of IC features include active regions, gate electrodes, source and drain features, isolation features, metal lines, contact plugs, vias, and so forth. The design house 120 implements suitable design methods to form the IC design layout 122. The design methods may include logical design, physical design, placement and routing, and / or various design verification operations. The IC design layout 122 is represented in one or more data files that have information about the geometric structures. The IC design layout 122 may be represented in a GDSII file format or DFII file format, for example.The mask house 130 uses the IC design layout 122 to fabricate a set of masks to be used to fabricate the various layers of the IC device 160 according to the IC design layout 122. The mask house 130 performs data preparation 132 and mask fabrication 144. At data preparation 132, IC design layout 122 is translated into a form that can be physically written by a mask writer. The mask fabrication 144 produces the set of masks (photomask or reticle).In the present embodiment, data preparation 132 includes a hybrid double-pattern decomposition 134 that is configured to decompose IC design layout 122 into two subsets suitable for two different lithography techniques (L1 and L2) employed by microchip factory 150. The data preparation 132, particularly the hybrid double-pattern decomposition 134, may generate feedback to the design house 120, which may be used to modify (or adapt) the IC design layout 122 to be made compatible with the fabrication processes in the microchip factory 150. As discussed above, in some embodiments, the hybrid double-patterning decomposition 134 may be implemented by the design house 120 instead of the mask house 130. The data preparation 132 may further include other manufacturing processes, such as optical proximity correction (OPC), off-axis illumination, sub-resolution assist features, other suitable techniques, or combinations thereof. The details of the hybrid double-pattern decomposition 134 are discussed in a later section of the present disclosure.After the data preparation 132 prepares the data for the mask layers, the mask preparation 144 produces a set of masks that include the two masks for hybrid double patterning. For example, one electron beam (E-beam) or a mechanism of multiple E-beams is used to form a pattern on a mask based on data files derived from the IC design layout 122. The mask may be formed in various technologies such as binary masks, phase shift masks, and EUV masks. For example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the substrate. The opaque material is patterned according to the mask data, thereby forming opaque regions and transparent regions on the binary mask. An irradiation beam, such as an ultraviolet (UV) beam, is blocked by the opaque regions and transmitted through the transparent regions, thereby transferring an image of the mask to a sensitive material layer (e.g., photoresist) coated on a wafer 152. As another example, an EUV mask includes a low thermal expansion substrate, a reflective multilayer (ML) over the substrate, and an absorption layer over the ML. The absorption layer is patterned according to the mask data. An EUV beam is either absorbed by the patterned absorption layer or reflected by the ML, thereby transferring an image of the mask to a sensitive material layer (e.g., photoresist) coated on the wafer 152. In some embodiments, microchip factory 150 may employ some type of maskless lithography, such as e-beam lithography. For example, one of L1 and L2 may be an E-beam lithography. In such a case, the data handler 132 may process the direct write data file for maskless lithography and the mask fabrication 144 does not fabricate a photomask for those particular layers to be generated using maskless lithography.The IC manufacturer (microchip factory) 150, such as a semiconductor casting mill, uses the masks to fabricate the IC device 160 using, for example, lithography processes. The microchip factory 150 may include a front-end-of-line manufacturing facility (FEOL) and / or a back-end-of-line manufacturing facility (BEOL). In particular, microchip fab 150 implements two different lithography techniques to accomplish the hybrid dual patterning on semiconductor wafer 152. For example, one lithography technique is EUV and the other is 193 nm immersion lithography, or one lithography technique is 193 nm immersion lithography and the other is conventional (or dry) 193 nm lithography. The two lithography techniques may be performed in any order. The first lithography technique is used to produce a first pattern on the wafer 152 and the second lithography technique is used to produce a second pattern on the wafer 152. The first and second patterns together form (by addition or subtraction) a pattern on the wafer 152. The structure can be used in a variety of processes. For example, the structure may be used in an ion implantation process to form different doped regions in wafer 152, or may be used in an etching process to form different etch regions in wafer 152.Wafer 152 includes a silicon substrate or other suitable substrate having layers of material formed thereon. Other suitable substrate materials include another suitable elementary semiconductor such as diamond or germanium; a suitable compound semiconductor such as silicon carbide, indium arsenide or indium phosphide; or a suitable alloy semiconductor such as silicon germanium carbide, gallium arsenic phosphide or gallium indium phosphide. Wafer 152 may further include various doped regions, dielectric features, and multilevel interconnects (formed in subsequent fabrication steps).FIGS. 2A through 2D show a flow diagram of a method 200 configured in accordance with various aspects of the present disclosure. Embodiments of the method 200 may be implemented by the hybrid double-structure decomposition 134. The method 200 is an example and is not intended to limit the present disclosure beyond what is expressly recited in the claims. Additional operations may be provided for additional embodiments of the method before, during, and after method 200, and some operations described may be replaced, eliminated, or moved. The method 200 is described below in connection with FIGS. 3A-4P, which graphically illustrate some principles of the method 200. In the discussion below, it is assumed that hybrid double-patterning lithography uses a first lithography technique L1 and a second lithography technique L2, where L1 has a higher (better) resolution than L2. In other words, the finest or smallest resolution (smallest distance) that can be achieved with L1 is smaller than that that that can be achieved with L2. During wafer fabrication, L1 may be performed before or after L2 in hybrid double patterning lithography.Referring to FIG. 2A, at operation 202, the method 200 is provided with a layout of an IC. Referring to FIG. 3A, an example layout 300 includes geometric structures (polygons in this embodiment) P 1, P 2, P 3 and P 4. Each of the structures represents an IC feature, such as an active region, a gate electrode, a source or drain feature, an isolation feature, a metal line, a contact plug, a via, or another suitable IC feature. The structures are spaced apart from each other. In particular, structures P 1 and P 2 are spaced apart by a distance (or pitch) S 12 structures P 2 and P 3 are spaced apart by a distance S 23 structures P 2 and P 4 are spaced apart by a distance S 24 and structures P 3 and P4 are spaced apart by a distance S34. Also, in this embodiment, the distances S 12 and S 24 are smaller than a predetermined distance X, while the distances S 23 and S 34 are equal to or larger than the predetermined distance X. X represents the finest or smallest resolution (smallest distance) that can be achieved by the lithography technique L2 in hybrid double-patterning lithography. In other words, X is the smallest distance between adjacent IC features that can be formed by L2 without these adjacent IC features being short-circuited to each other.At operation 204, the method 200 (FIG. 2A ) derives a graph representing the IC design layout. Continuing with the example of IC design layout 300, a graph 350 is derived as shown in FIG. 3B. Graph 350 includes nodes connected by edges. The nodes represent structures P 1 through P 4. For ease of discussion, the nodes are labeled with the same alphanumeric values as the corresponding structures. The edges represent those distances less than X. In this embodiment, edge E 12 represents distance S 12 and edge E 24 represents distance S 24. Note that node P 3 is not connected to edges because structure P 3 is sufficiently spaced from other structures.At operation 206, the method 200 (FIG. 2A ) arranges the edges in the graph to be either an L1 edge or an L2 edge. Referring to FIG. 3C, in the present embodiment, an edge is an L 1- edge when the distance represented by the edge is less than the resolution of L 1, and an edge is an L 2 edge when the distance represented by the edge is equal to or greater than the resolution of L 1 but less than the resolution of L 2. As discussed above, if the distance between two structures is greater than or equal to the resolution of L2, there is no edge connecting the two nodes representing the two structures. From the perspective of a double patterning, if an edge between two nodes is an L1 edge, the two corresponding patterns are separately patterned by two lithographic processes L1 and L2, since neither L1 nor L2 alone is able to resolve the distance therebetween. Similarly, if an edge between two nodes is an L2 edge, the two corresponding structures are patterned by one lithographic process using L1 alone or by two lithographic processes using L1 and L2 separately. Likewise, if there is no edge between two nodes, the two corresponding structures may be patterned by one lithographic process using L1 or L2 alone or by two lithographic processes using L1 and L2 separately. By applying the above principles, operation 206 arranges edges E 12 and E 24 of graph 350 (FIG. 3B ).IC layout 300 and associated graph 350 are simple examples that may be processed using method 200. To provide a better understanding of the principles of the present disclosure, a more complex graph 400 is illustrated in FIG. 4A. Referring to FIG. 4A, the graph 400 includes multiple nodes 402. Each of the nodes 402 represents an IC layout structure that generally represents a polygon. FIG. 4B shows edges 404 connecting some of the nodes 402. FIG. 4B further illustrates edges 404 being classified into two types: L1 edge (solid line) and L2 edge (dashed line), as discussed with reference to FIG. 3C. Graph 400 shown in FIG. 4B is a result of operations 204 and 206 performed on an IC layout (not shown) obtained at operation 202. Remaining operations of method 200 are discussed using graph 400 as an example. Note that the graph 400 is merely an example, and does not limit the present disclosure. Embodiments of the method 200 may be applied to any IC layouts.Referring to FIG. 2A, at operation 208, the method 200 checks whether there is a loop formed by an odd number of nodes connected to L1 edges. Such a loop is referred to as an odd loop. FIG. 4A illustrates such an odd loop 406. Referring to FIG. 4C, loop 406 has three (an odd number of) nodes and all edges in loop 406 are L1 edges. In comparison, another loop 408 is not an odd loop because the loop has four nodes. After an odd loop is found, the method 200 continues to operation 210 to modify the IC layout to interrupt the loop, as the hybrid double pattern may not properly resolve the IC structures corresponding to the odd loop. This is because two IC structures connected by an L1 edge must be patterned by separate L1 and L2 processes (as defined by an L1 edge). The presence of an odd number of nodes in the loop means that some adjacent IC structures in the loop violate the above rule. In such a case, operation 210 may lay the corresponding layout patterns and correct such a violation. The operation 210 may be implemented by the mask house 130 or by the design house 120 (FIG. 1 ). After the IC layout is modified by operation 210, it is sent back to operation 202 and the above operations 204, 206, 208 are repeated until the graph 400 does not include an odd loop. From there, operation 200 continues with breaking down the nodes into two subsets, one for L1 and a second for L2. The decomposition includes a step of finding nodes to be structured by L1 (initial mapping), followed by steps of spreading colors from the nodes firmly mapped to L1 to the remainder of the graph. operations 212, 214, and 216 (Fig. 2B) and operations 226, 228, 230, and 231 (Fig. 2C) are two alternative embodiments of finding which nodes (corresponding to IC structures) are structured by lithography process L1 (the initial mapping). Operations 218, 220, and 222 (FIG. 2D ) then propagate colors from that initial mapping to the remainder of the graph.In the first embodiment, the method 200 performs operations 212, 214, and 216 to find out which IC structures are patterned by the lithography process L 1. Referring to FIG. 2B, at operation 212, the method 200 performs a 2-color (e.g., using a color "X" and a color "Y") on all nodes connected by L1 edges. This includes several steps, as discussed below.Referring to FIG. 4D, operation 212 identifies "networks.". A network includes nodes and only L1 edges connecting the nodes. In other words, when identifying nets, operation 212 ignores the L2 edges. Note that IC layout 122 has been modified to interrupt odd loop 406 (FIG. 4C ) in graph 400. Referring to FIG. 4E, operation 212 colors the nodes within each mesh using colors X and Y, assigning different colors to two nodes connected to a common L1 edge.At operation 214, the method 200 (FIG. 2B ) checks whether there is a network having both an X-X pair and a Y-Y pair. As used herein, an "X-X pair" refers to two nodes within a mesh that are colored with X and are connected by an L2 edge, and a "Y-Y pair" refers to two nodes within a mesh that are colored with Y and are connected by an L2 edge. FIG. 4F shows an example network 450 satisfying the above condition, where nodes 453 and 454 form a Y-Y pair and nodes 455 and 456 form an X-X pair. Having such X-X and Y-Y pairs in the same network indicates that the IC layout corresponding to the network may not have been properly patterned by the hybrid double-patterning lithography. Taking the network 450 as an example, then nodes 453 and 454 must be assigned L2 when node 452 is assigned L1 (i.e., the IC structure corresponding to node 452 is patterned by L1 lithography), which represents a violation of the manufacturing rule because a distance between the two cannot be properly resolved by L2 lithography (according to the definition of the L2 edge). On the other hand, if node 452 is assigned L2 and nodes 453 and 454 are assigned L1, then nodes 455 and 456 must be assigned L2, which renews a violation against the manufacturing rule.After the act 214 finds such a violation, the method 200 (FIG. 2B ) continues to act 210 to modify the IC layout 122 to prevent such X-X and Y-Y pairs in the same network. For example, operation 210 may lay the corresponding layout patterns and correct such a violation. If no such violation is found, the method 200 (FIG. 2B ) continues with operation 216 to assign color "A" to any X-X pair(s) and Y-Y pair(s) in the network. A node with color A indicates that the corresponding IC structure is to be created by L1 lithography in the microchip factory 150. In the graph 400 illustrated in FIG. 4G, nodes 402A and 402B form a Y-Y pair, nodes 402C and 402D form an X-X pair. Thus, nodes 402A, 402B, 402C, and 402D are assigned color A. The results are shown in Fig. 4K. Nodes 402A, 402B, 402C, and 402D serve as the starting point (or starting point) of coloring graph 400 with color A and color B. A node with color B indicates that the corresponding IC structure is to be created by L2 lithography in microchip factory 150.Figure 2C illustrates an alternative embodiment of initially coloring nodes with color A. Referring to Figure 2C, method 200 proceeds from operation 208 to operation 226. At operation 226, method 200 finds a pair of nodes directly connected by an L2 edge. There may be many such pairs in graph 400. The method 200 may process one pair or more pairs simultaneously at a time. For a given pair of nodes connected by an L2 edge, the method 200 (operation 228) checks whether there is a path between the two nodes formed by an even number of L1 edges. If the answer is yes, method 200 assigns node color A at operation 230 and continues to operation 232. If the answer is no, method 200 proceeds to operation 232. If there are multiple pairs to be processed (operation 232), the method 200 returns to operation 226 and the above operations are refused. FIGS. 4H, 4I and 4J show the above operations.Referring to FIG. 4H, at operation 226, method 200 finds a pair of nodes 402E and 402F. Nodes 402E and 402F are directly connected to an L2 edge 404A. At operation 228, the method 200 determines that the nodes 402E and 402F are also connected by a path that includes only L1 edges, namely 404B, 404C, 404D, and 404E. In addition, the number of L1 edges in the path is an even number, namely 4. Therefore, the pair of nodes 402E and 402F satisfy the condition of operation 228. Method 200 then assigns color A to nodes 402E and 402F at operation 230. In another example shown in FIG. 4I, even though nodes 402J and 402K are directly connected by an L2 edge, there is no path between the two nodes that includes only L1 edges. Therefore, nodes 402J and 402K are not colored with color A at operation 230. In yet another example shown in FIG. 4J, nodes 402L and 402M are directly connected by an L2 edge, and there is also a path between the two nodes that includes only L1 edges. But the number of L1 edges in the path is not an even number. Therefore, nodes 402L and 402M are not colored with color A at operation 230. In fact, nodes 402L and 402M may be colored with colors A and B, respectively, or colors B and A, respectively.From either operation 216 or operation 232, the method 200 proceeds to operation 218 (FIG. 2D ) to color the remainder of nodes in the graph based on the initial color of color A, as discussed above. Note that method 200 may employ other embodiments (alternative to acts 212 / 214 / 216 and acts 226 / 228 / 230 / 232) to find out which node to assign color A.In the present embodiment, operation 218 colors the nodes in graph 400 based on the following rules (1) through (4) as shown in FIG. 4L: (1) if a node is colored with color A, then its immediate neighbor is colored with color B if the node and immediate neighbor are connected by an L1 edge; (2) if a node is colored with color B, then its immediate neighbor is colored with color A if the node and its immediate neighbor are connected by an L1 edge; (3) if a node is colored with color B, then its immediate neighbor is colored with color A if the node and its immediate neighbor are connected by an L2 edge; (4) If a node is colored with color A, then its immediate neighbor is temporarily not colored if the node and immediate neighbor are connected by an L2 edge. Nodes that are not colored due to rule (4) may be assigned either color A or color B (in a later coloring step), which may be used by method 200 to provide process friendliness, such as balancing a pattern stress of the two subsets for mask fabrication, balancing a pattern stress on the wafer during the L1 and L2 lithography processes, and avoiding an undesirable configuration on the same mask.Based on the above rules and the vertices that are initially colored with color A (e.g., by operations 212 / 214 / 216 or operations 226 / 228 / 230 / 232), operation 218 increasingly assigns colors to the vertices in graph 400, as shown in FIGS. 4M and 4N. After operation 218 is completed, method 200 checks (operation 220 in FIG. 2D ) whether there is a pair of nodes colored with color B and directly connected to an L2 edge. Such a pair indicates violation of the manufacturing rules, since the corresponding IC structures are to be patterned by L2 lithography (indicated by color B), but cannot be properly triggered by L2 lithography (indicated by L2 edge). If the act 220 finds such a pair, the method 200 continues with the act 210 to modify the IC layout 122 to prevent the violation, for example, by laying the corresponding IC structures in the layout 122. If the act 220 does not find such a pair, the method 200 continues to act 222 to complete the coloring process.As shown in FIG. 4N, some nodes in graph 400 are not colored after operation 218 is completed. This may be for a few reasons. For example, some nodes may not be connected to a network in which some nodes are initially colored with color A, so that the coloring process of operation 218 does not propagate to these nodes. As another example, due to rule (4) discussed in operation 218, some nodes are intentionally not colored by operation 218, so process friendliness may be provided by method 200. At operation 222, the method 200 (FIG. 2D ) assigns colors to these nodes in consideration of process friendliness. Nodes that are isolated (not edge-connected to other nodes) may randomly assign the method 200 to color A or color B, considering process friendliness. For nodes located in a network, the method 200 may randomly select a starting point by assigning color A or color B to any of the nodes and then propagating the colors to the rest of the nodes in the network. FIG. 4O illustrates the full color assignment to the graph 400 according to an embodiment.At operation 224, the method 200 outputs the results (color assignment) of the decomposition. The first subset of IC structures corresponding to nodes colored with color A is output for L1 lithography, and the second subset of IC structures corresponding to nodes colored with color B is output for L2 lithography. The first and second subsets may be stored in a tangible computer readable medium for mask fabrication 144 or other IC processing devices. The tangible computer-readable medium may include a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a solid-state storage device, or any other suitable storage medium. The data preparation 132 may perform further processes on the first and second subsets of IC structures based on the requirement of an L1 and L2 lithography process. For example, the data preparation 132 may perform optical proximity correction (OPC), off-axis illumination, sub-resolution assist features, other suitable techniques, or combinations thereof, separately on the first and second subsets of IC structures.In the discussion above, the method 200 classifies edges into two types: L1 edge and L2 edge (operation 206). In another embodiment, the method 200 may use more than two types of edges. For example, in addition to L1 edge and L2 edge, method 200 may use a third edge type: Link3, as indicated in FIG. 4P. For example, there may be two IC structures that can be resolved (patterned) in resolution by either L1 lithography or L2 lithography. However, it is preferred that they are patterned by L2 lithography in order to achieve better process performance such as higher contrast during photoexposure. To further develop this embodiment, the rules discussed in operation 218 may be extended to accommodate this third type of edge by, for example, adding the two rules (5) and (6) below: (5) if a node is colored with color A, then its immediate neighbor is colored with color B if the node and immediate neighbor are connected by a link3 edge; (6) if a node is colored with color B, then its immediate neighbor is not colored temporarily if the node and immediate neighbor are connected by a link3 edge. All operations of method 200 may remain the same, except that operation 218 in this embodiment follows rules (1) through (6).Referring to FIG. 5, an example of a computerized IC tool 500 for implementing embodiments of the method 200 described above is shown. The computerized IC tool 500 may be a design tool used by the design house 120, or a mask data rendering tool used by the mask house 130 (FIG. 1 ). The computerized IC tool 500 includes a microprocessor 502, an input device 504, a storage device 506, a video controller 508, a system memory 510, a display 514, and a communication device 516, all interconnected using one or more buses 512. The storage device 506 could be a floppy disk drive, a hard disk drive, a CD-ROM, an optical drive, or any other form of storage device. Additionally, the storage device 506 may be capable of accommodating a floppy disk, a CD-ROM, a DVD-ROM, or any other form of computer readable medium. In an example, the input device 504 and the memory device 506 collectively receive a design layout (e.g., the design layout 122). In one embodiment, the storage device 506 may include computer-executable instructions that, when read by the microprocessor 502, cause the microprocessor 502 to perform the method 200 discussed above. Additionally, the communication device 516 could be a modem, network card, or any other device to enable the IC tool 500 to communicate with other tools.The computerized IC tool 500 may implement the method 200 using hardware, software, or a combination thereof. An example of hardware includes processor-enabled platforms, such as personal computers or servers, and portable processing devices, such as smart phones, tablets, and personal digital assistants. In addition, the hardware may include other physical devices capable of executing computer readable instructions, such as field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs). Software includes any machine code stored in any storage medium such as RAM or ROM and machine code stored on other devices (such as floppy disks, flash memories, or CD-ROM). Software may include, for example, source or object code. The software also includes any set of commands that may be executed on a client machine or server.Combinations of software and hardware could also be used to provide improved functionality and performance for certain embodiments of the present disclosure. An example is to fabricate software functions directly into a silicon chip, such as an FPGA or an ASIC. Accordingly, it should be appreciated that combinations of hardware and software are also included within the definition of the computerized IC tool 500 and are therefore considered by the present disclosure to be possible equivalent structures and equivalent methods.Computer readable media in the present disclosure include passive data storage such as random access memory (RAM), as well as semi-permanent data storage such as compact disk read only memory (CD-ROM). In addition, an embodiment of the present disclosure may be executed in the RAM of a computer to convert a standard computer to the computerized IC tool 500.The computerized IC tool 500 may be configured to operate on any specific architecture. For example, the computerized IC tool 500 may be configured to operate on a single computer, in local area networks, client-server networks, wide area networks, Internets, portable and other portable and wireless devices and networks.Although not intended to be limiting, the present disclosure provides many advantages for semiconductor fabrication processes. For example, embodiments of the present disclosure provide methods for hybrid double patterning that may take advantage of a higher resolution of one lithographic process and a lower cost of another lithographic process. Embodiments of the present disclosure provide efficient ways to disassemble an IC layout for hybrid double patterning, including checking potential violations of manufacturing rules at an early stage of fabrication. Embodiments of the provided methods may be easily integrated into an existing design and manufacturing process.In an example aspect, the present disclosure is directed to a method of manufacturing an integrated circuit (IC) having a first lithography technique and a second lithography technique different than the first lithography technique. The method comprises: providing a layout of the IC, the layout having a set of IC structures; deriving a graph from the layout, the graph having nodes and edges connecting some of the nodes, the nodes representing the IC structures, the edges being classified into at least two types, a first type of edges connecting two nodes to be separately patterned with the first and second lithography techniques, a second type of edges connecting two nodes to be patterned in a same process using the first lithography technique or to be separately patterned with the first and second lithography techniques. The method further includes decomposing, using a computerized IC tool, the nodes into a first subset and a second subset, wherein the IC structures corresponding to the first subset are to be patterned on a wafer using the first lithography technique, and the IC structures corresponding to the second subset are to be patterned on the wafer using the second lithography technique.In one embodiment, after the step of deriving, the method further comprises: checking whether there is a loop formed by an odd number of nodes connected by edges of the first type; and under the condition that there is such a loop, modifying the layout to interrupt the loop.In one embodiment, after the deriving step, the method further comprises assigning colors X and Y to all nodes connected by edges of the first type, two nodes connected by a common edge of the first type being assigned different colors. In another embodiment, after the step of assigning colors X and Y, the method further comprises: identifying a mesh of nodes connected together by edges of the first type; checking if two such pairs of nodes are present in the mesh, that a first pair is assigned the same color X and is directly connected by an edge of the second type, and a second pair is assigned the same color Y and is directly connected by another edge of the second type; and under the condition that two such pairs are present, modifying the layout to prevent two such pairs. In another further embodiment, after the step of assigning colors X and Y, the method further comprises: initially assigning Fabre A to all pairs of nodes assigned the same color X or the same color Y and directly connected by an edge of the second type; and arranging nodes with color A in the first subset. After the step of initially assigning color A, the method may further comprise: assigning color B to all nodes that are not colored with colors A or B and that are directly connected to nodes with color A by an edge of the first type; after the step of assigning color B, then assigning color A to all nodes that are not colored with colors A or B and that are directly connected to nodes with color B by an edge of the first or second type; repeating the steps of assigning color B and then assigning fabric A to the remainder of the nodes in the graph; and arranging nodes with color A in the first subset and nodes with color B in the second subset.In another embodiment, the method may include, after the repeating step: checking whether there is a pair of nodes colored with color B and connected by an edge of the second type; and modifying the layout on condition that there is such a pair. Alternatively, after the repeating step, the method may include: under the condition that there are nodes neither colored with color A nor colored with color B, assigning color A or color B to the node to balance a mask load between the first and second subsets.In another alternative embodiment, after the repeating step, the method further comprises: forming a first photomask having the IC structures corresponding to the first subset of nodes; and forming a second photomask having the IC structures corresponding to the second subset of nodes. The method may also include: performing a first lithography process on a wafer using the first lithography technique to generate a first subset of etch mask structures corresponding to the first subset of nodes; performing a second lithography process on the wafer using the second lithography technique to generate a second subset of etch mask structures corresponding to the second subset of nodes; and etching the wafer using both the first and second subsets of etch mask structures.In one embodiment, after the deriving step, the method further comprises: locating a pair of nodes connected by a second type edge; checking whether a path exists between the pair of nodes across only first type edges; on condition that such a path exists and the number of first type edges on the path is even, initially assigning color A to the pair of nodes; and arranging nodes with Fabre A in the first subset. In another embodiment, after the step of initially assigning color A, the method comprises assigning color B to all nodes that are not colored with colors A or B and that are directly connected to nodes with color A by an edge of the first type. After the step of assigning color B, the method further comprises: subsequently assigning color A to all nodes that are not colored with colors A or B and that are directly connected to nodes with color B by an edge of the first or second type; repeating the steps of assigning color B and then assigning color A to the rest of the nodes in the graph; and arranging nodes with color A in the first subset and nodes with color B in the second subset.In another example aspect, the present disclosure is directed to a method of manufacturing an integrated circuit (IC) having a first lithography technique and a second lithography technique that has a lower resolution than the first lithography technique. The method comprises: providing a layout of the IC, the layout having a set of IC structures; deriving a graph from the layout by representing the IC structures by nodes and representing a distance between the IC structures by edges connecting the corresponding nodes; and ranking the edges into two types, wherein a first type of edges connects two nodes to be separately patterned with the first and second lithography techniques, wherein a second type of edges connects two nodes to be patterned in a same process using the first lithography technique or to be separately patterned with the first and second lithography techniques. The method further comprises: decomposing the nodes into a first subset and a second subset, wherein the IC structures corresponding to the first subset are to be patterned on a wafer using the first lithography technique to form a first etch mask, and the IC structures corresponding to the second subset are to be patterned on the wafer using the second lithography technique to form a second etch mask, wherein the first and second etch masks collectively transfer the IC structures to the wafer.In one embodiment, after the ranking step, the method further comprises: checking whether there is a loop formed by an odd number of nodes connected by edges of the first type. In another embodiment, after the ranking step, the method further comprises: assigning colors X and Y to all nodes connected by first type edges, wherein two nodes connected by a common first type edge are assigned different colors.In one embodiment, after the step of assigning colors X and Y, the method further comprises: initially assigning color A to all pairs of nodes assigned the same color X or the same color Y and directly connected by an edge of the second type; and arranging nodes with color A in the first subset. In another embodiment, after the step of initially assigning color A, the method further comprises: assigning color B to all nodes that are not colored with colors A or B and that are directly connected to nodes with color A by an edge of the first type. After the step of assigning color B, the method further comprises subsequently assigning color A to all nodes that are not colored with colors A or B and that are directly connected to nodes with color B by an edge of the first or second type. The method further comprises: repeating the steps of assigning color B and then assigning color A to the rest of the nodes in the graph; placing nodes with color A in the first subset; and placing nodes with color B in the second subset.In yet another example aspect, the present disclosure is directed to a method of manufacturing an integrated circuit (IC) having a first lithography technique having a first resolution and a second lithography technique having a second resolution greater than the first resolution. The method comprises: providing a layout of the IC, the layout having a set of IC structures; and deriving a graph from the layout, the graph having nodes and cats connecting some of the nodes, the nodes representing the IC structures, the edges representing a distance between the IC structures that is less than the second resolution. The method further comprises: ranking the edges into at least two types, wherein a first type represents a distance that is less than the first resolution, a second type represents a distance that is greater than or equal to the first resolution but less than the second resolution. The method further includes decomposing the nodes into a first subset and a second subset, wherein the IC structures corresponding to the first subset are to be patterned on a wafer using the first lithography technique, and the IC structures corresponding to the second subset are to be patterned on the wafer using the second lithography technique, wherein at least one of the deriving, ranking, and decomposing is performed using a computerized IC tool.In one embodiment, after the ranking step, the method further comprises: assigning colors X and Y to all nodes connected by first type edges, wherein two nodes connected by a common first type edge are assigned different colors. In another embodiment, after the step of assigning colors X and Y, the method comprises: assigning color A to all pairs of nodes assigned the same color X or the same color Y and directly connected by an edge of the second type; and progressively coloring the remainder of nodes with colors A and B by performing: assigning different colors to two nodes directly connected by an edge of the first type; assigning color A to a node directly connected to a node with color B by an edge of the second type; and assigning either color A or color B to a node directly connected to a node of color A by an edge of the second type. The method further comprises arranging nodes with color A in the first subset and nodes with color B in the second subset.In an example aspect, the present disclosure is directed to a method of manufacturing an integrated circuit (IC) having a first lithography technique having a first resolution and a second lithography technique having a second resolution greater than the first resolution. The method comprises: providing a layout of the IC, the layout having a set of IC structures; and deriving a graph from the layout, the graph having nodes and cats connecting some of the nodes, the nodes representing the IC structures, the edges representing a distance between the IC structures that is less than the second resolution. The method further comprises: ranking the edges into two types, a first type representing a distance less than the first resolution, a second type representing a distance greater than or equal to the first resolution but less than the second resolution; and using a computerized IC tool that splits the nodes into a first subset and a second subset. The decomposing comprises: locating a pair of nodes connected by a second type edge; on condition that a path exists between the pair of nodes via only first type edges and the number of first type edges on the path is even, assigning color A to the pair of nodes; and increasingly coloring the rest of nodes having colors A and B by: assigning different colors to two nodes directly connected by a first type edge; assigning color A to a node directly connected to a node having color B by a second type edge; and assigning either color A or color B to a node directly connected to a node of color A by an edge of the second type. The method further comprises arranging nodes with color A in the first subset and nodes with color B in the second subset.In one embodiment, after the ranking step, the method further comprises: checking whether there is a loop formed by an odd number of nodes connected by first type edges; and under the condition that there is such a loop, modifying the layout to interrupt the loop. In another embodiment, after increasingly coloring the Fabre B-colored waste of nodes, the method further comprises: checking whether there is a pair of nodes colored with Fabre B and connected by an edge of the second type; and under the condition that there is such a pair, modifying the layout.In another example aspect, the present disclosure is directed to a method of manufacturing an integrated circuit (IC) having a first lithography technique having a first resolution and a second lithography technique having a second resolution greater than the first resolution. The method comprises: providing a layout of the IC, the layout having a set of IC structures; and deriving a graph from the layout, the graph having nodes and cats connecting some of the nodes, the nodes representing the IC structures, the edges representing a distance between the IC structures that is less than the second resolution. The method further comprises: ranking the edges into two types, a first type representing a distance less than the first resolution, a second type representing a distance greater than or equal to the first resolution but less than the second resolution; and using a computerized IC tool that splits the nodes into a first subset and a second subset. The decomposing comprises: assigning colors X and Y to all nodes connected by edges of the first type, wherein two nodes connected by a common edge of the first type are assigned different colors; assigning color A to all pairs of nodes assigned the same color X or the same color Y and directly connected by an edge of the second type; and coloring the rest of nodes increasingly with colors A and B by: assigning different colors to two nodes directly connected by an edge of the first type; assigning color A to a node directly connected to a node with color B by an edge of the second type; and assigning either color A or color B to a node directly connected to a node of color A by an edge of the second type. The method further comprises arranging nodes with color A in the first subset and nodes with color B in the second subset.In one embodiment, after the ranking step, the method further comprises: checking whether there is a loop formed by an odd number of nodes connected by first type edges; and under the condition that there is such a loop, modifying the layout to interrupt the loop.In another embodiment, the method further comprises, after assigning colors X and Y: identifying a mesh of nodes that are connected together using edges of the first type; and on condition that a first pair of nodes in the mesh is assigned the same color X and is directly connected by an edge of the second type, and a second pair of nodes in the mesh is assigned the same color Y and is directly connected by another edge of the second type, modifying the layout to share the mesh.In yet another embodiment, after increasingly coloring the ret of nodes with colors A and B, the method further comprises: under the condition that there is a pair of nodes colored with Fabre B and connected by a second type edge, modifying the layout to remove the second type edge between the pair.In yet another example aspect, the present disclosure is directed to a method of manufacturing an integrated circuit (IC) having a first lithography technique and a second lithography technique different than the first lithography technique. The method comprises: providing a layout of the IC, the layout having a set of IC structures; deriving a graph from the layout, the graph having nodes and edges connecting some of the nodes, the nodes representing the IC structures, the edges being classified into at least two types, a first type of edges connecting two nodes to be separately patterned with the first and second lithography techniques, a second type of edges connecting two nodes to be patterned in a same process using the first lithography technique or to be separately patterned with the first and second lithography techniques. The method further comprises, under the condition that a loop comprising an odd number of nodes connected by edges of the first type is present, modifying the layout to break the loop. The method further includes decomposing, using a computerized IC tool, the nodes into a first subset and a second subset, wherein the IC structures corresponding to the first subset are to be patterned on a wafer using the first lithography technique, and the IC structures corresponding to the second subset are to be patterned on the wafer using the second lithography technique. The decomposing comprises: assigning colors X and Y to all nodes connected by edges of the first type, wherein two nodes connected by a common edge of the first type are assigned different colors; assigning color A to all pairs of nodes assigned the same color X or the same color Y and directly connected by an edge of the second type; assigning color B to all nodes that are not colored with colors A or B and directly connected to nodes with color A by an edge of the first type; and arranging nodes with color A in the first subset and nodes with color B in the second subset.In one embodiment, the method further comprises, after the step of assigning color B, subsequently assigning color A to all nodes that are not colored with colors A or B and are directly connected to nodes having color B through an edge of the first or second type; and retrieving the steps of assigning color B and then assigning color A to the rest of the nodes in the graph. In another embodiment, the method further comprises, after assigning colors X and Y: identifying a mesh of nodes that are connected together using edges of the first type; and on condition that a first pair of nodes in the mesh is assigned the same color X and is directly connected by an edge of the second type, and a second pair of nodes in the mesh is assigned the same color Y and is directly connected by another edge of the second type, modifying the layout to share the mesh.

Claims

Method (200) for producing an integrated circuit IC having a first lithography technique which has a first resolution and a second lithography technique which is different from the first lithography technique and has a second resolution which is lower than the first resolution; the method (200) comprising the following steps: providing (202) a layout of the IC, wherein the layout has a set of IC structures; deriving (204) a graph from the layout, the graph having nodes and edges connecting some of the nodes, the nodes representing the IC structures, the edges being classified into at least two types, a first type of edges connecting two nodes to be separately patterned with the first and second lithography techniques and representing distances less than the first resolution, a second type of edges connecting two nodes to be patterned in a same process using the first lithography technique or separately patterned with the first and second lithography techniques and representing distances greater than or equal to the first resolution but less than the second resolution; assigning (212) colors X and Y to all nodes connected by edges of the first type, two nodes connected by a common edge of the first type being assigned different colors; identifying (214) a network of nodes connected to each other via edges of the first type; checking (214) whether two such pairs of nodes are present in the network, that a first pair is assigned the same color X and it is directly connected by an edge of the second type, and a second pair is assigned the same color Y and it is directly connected by another edge of the second type; modifying (210) the layout to prevent two such pairs, on condition that two such pairs are present; and dicing, using a computerized IC tool, the nodes into a first subset and a second subset, wherein the IC structures corresponding to the first subset are to be patterned on a wafer using the first lithography technique and the IC structures corresponding to the second subset are to be patterned on the wafer using the second lithography technique.The method (200) of claim 1, further comprising, after the deriving step (204), the steps of: checking (208) whether there is a loop formed by an odd number of nodes connected by first type edges; and under the condition that there is such a loop, modifying (210) the layout to break the loop.The method (200) of claim 1 or 2, further comprising, after the step of assigning (212) colors X and Y, the steps of: initially assigning (216) color A to all pairs of nodes assigned the same color X or the same color Y and directly connected by an edge of the second type; and arranging nodes with color A in the first subset.The method (200) of claim 3, further comprising, after the step of initially assigning color A (216), the steps of: assigning color B to all nodes that are not colored with colors A or B and that are directly connected to nodes with color A by an edge of the first type; after the step of assigning color B, subsequently assigning color A to all nodes that are not colored with colors A or B and that are directly connected to nodes with color B by an edge of the first or second type; repeating the steps of assigning color B and then assigning color A to the remainder of the nodes in the graph; and arranging nodes with color A in the first subset and nodes with color B in the second subset.The method (200) according to claim 4, further comprising, after the repeating step, the steps of: checking (220) whether there is a pair of nodes colored with color B and connected by an edge of the second type; and on condition that there is such a pair, modifying (210) the layout.The method (200) of claim 4 or 5, further comprising, after the repeating step, the step of: under the condition that there are nodes that are neither colored with color A nor color B, assigning (222) color A or color B to the node to balance a mask load between the first and second subsets.The method (200) of any of the preceding claims 4 to 6, further comprising, after the repeating step, the steps of: forming a first photomask having the IC structures corresponding to the first subset of nodes; and forming a second photomask having the IC structures corresponding to the second subset of nodes.The method (200) of any of the preceding claims 4 to 7, further comprising the steps of: performing a first lithography process on a wafer using the first lithography technique to generate a first subset of etch mask structures corresponding to the first subset of nodes; performing a second lithography process on the wafer using the second lithography technique to generate a second subset of etch mask structures corresponding to the second subset of nodes; and etching the wafer using both the first and second subsets of etch mask structures.The method (200) of any preceding claim, further comprising, after the deriving step (204), the steps of: locating (226) a pair of nodes connected by a second type edge; checking (228) whether a path exists between the pair of nodes across only first type edges; on condition that such a path exists and the number of first type edges on the path is even, initially assigning (230) color A to the pair of nodes; and arranging nodes with color A in the first subset.The method (200) of claim 9, further comprising, after the step of initially assigning color A (230), the steps of: assigning color B to all nodes that are not colored with colors A or B and that are directly connected to nodes with color A by an edge of the first type; after the step of assigning color B, subsequently assigning color A to all nodes that are not colored with colors A or B and that are directly connected to nodes with color B by an edge of the first or second type; repeating the steps of assigning color B and then assigning color A to the remainder of the nodes in the graph; and arranging nodes with color A in the first subset and nodes with color B in the second subset.A method (200) of manufacturing an integrated circuit IC having a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution; the method (200) comprising the steps of: providing (202) a layout of the IC, the layout having a set of IC structures; deriving (204) a graph from the layout by representing the IC structures by nodes and representing a distance between IC structures by edges connecting the corresponding nodes; arranging (206) the edges into two types, a first type of edges connecting two nodes to be separately patterned with the first and second lithography techniques and representing distances less than the first resolution, a second type of edges connecting two nodes to be patterned in a same process using the first lithography technique or separately patterned with the first and second lithography techniques and representing distances greater than or equal to the first resolution but less than the second resolution; assigning (212) colors X and Y to all nodes connected by edges of the first type, two nodes connected by a common edge of the first type being assigned different colors; initially assigning (216) color A to all pairs of nodes assigned the same color X or the same color Y and directly connected by an edge of the second type; arranging nodes with color A in the first subset; and decomposing the nodes into a first subset and a second subset, wherein the IC structures corresponding to the first subset are to be patterned on a wafer using the first lithography technique to form a first etching mask and the IC structures corresponding to the second subset are to be patterned on the wafer using the second lithography technique to form a second etching mask, wherein the first and second etching masks jointly transfer the IC structures to the wafer.The method (200) of claim 11, further comprising, after the ranking step (206), the step of: checking (208) whether a loop is present formed by an odd number of nodes connected by edges of the first type.The method (20) of claim 11 or 12, further comprising, after the step of initially assigning color A, the steps of: assigning color B to all nodes that are not colored with colors A or B and that are directly connected to nodes with color A by an edge of the first type; after the step of assigning color B, subsequently assigning color A to all nodes that are not colored with colors A or B and that are directly connected to nodes with color B by an edge of the first or second type; repeating the steps of assigning color B and then assigning color A to the remainder of the nodes in the graph; arranging nodes with color A in the first subset; and placing nodes of color B in the second subset.A method (200) of manufacturing an integrated circuit IC having a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution, comprising the steps of: providing (202) a layout of the IC, the layout having a set of IC structures; deriving (204) a graph from the layout, the graph having nodes and edges connecting some of the nodes, the nodes representing the IC structures, the edges representing a distance between the IC structures that is less than the second resolution; ranking (206) the edges into at least two types, a first type representing a distance less than the first resolution, a second type representing a distance greater than or equal to the first resolution but less than the second resolution; assigning (212) colors X and Y to all nodes connected by edges of the first type, two nodes connected by a common edge of the first type being assigned different colors; assigning (216) color A to all pairs of nodes assigned the same color X or the same color Y and directly connected by an edge of the second type; Increasingly coloring the remainder of nodes having colors A and B by performing: assigning different colors to two nodes directly connected by an edge of the first type; assigning color A to a node directly connected to a node having color B by an edge of the second type; and assigning either color A or color B to a node directly connected to a node having color A by an edge of the second type; arranging nodes having color A in the first subset and nodes having color B in the second subset; and decomposing the nodes into a first subset and a second subset, wherein the IC structures corresponding to the first subset are to be patterned on a wafer using the first lithography technique, and the IC structures corresponding to the second subset are to be patterned on the wafer using the second lithography technique, wherein at least one of the deriving, ranking, and decomposing is performed by a computer-aided IC tool.

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