Semiconductor component and method for its manufacture

Abstract

Method for fabricating a semiconductor device comprising the following steps: Depositing a spacer material (107) over a top and side walls of a mandrel (105); Placing a layer (111) over the spacer material (107); Structuring the layer (111) to create an opening (121) and expose the spacer material (107); and Applying an etchant such that it comes into physical contact with the layer (111) and the spacer material (107) on the side wall of the mandrel, the etchant comprising an inhibitor that inhibits an etch rate of the spacer material (107).

Description

BackgroundSemiconductor devices are used in various electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by depositing insulating or dielectric layers, conductive layers, and layers of semiconductor materials over a semiconductor substrate in sequence, and patterning the various material layers with lithographic and etching processes to produce circuit components and elements thereon.The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously decreasing the smallest feature width so that more components can be integrated on a given area. However, if the smallest pattern width is reduced, further problems which should be addressed arise in each of the processes used.US 2005 / 0 261 151 A1 discloses a corrosion-inhibiting cleaning composition for semiconductor wafer processing comprising hydrogen peroxide in a concentration in the range from about 0.01 wt % to about 0.01 wt %, sulfuric acid in a concentration in the range from about 0.01 wt % to about 0.01 wt %, hydrogen fluoride in a concentration in the range from about 0.01 wt % to about 0.01 wt %, an azole in a concentration in the range from about 0.01 wt % to about 0.01 wt %, and deionized water. The azole has a corrosion-inhibiting effect on a metal layer to be cleaned by forming a chelate with a surface of the metal layer during a cleaning process.US 2013 / 0 217 234 A1 discloses a cleaning solution. The cleaning solution contains an aliphatic polycarboxylic acid, a chain sulfonic acid (substantially less than 4 wt %) and an amine-containing buffering agent.US 2009 / 0 184 092 A1 discloses an iodine-based etching solution for etching a material in which palladium and gold coexist. This etching solution contains at least one additive selected from the group consisting of five-membered nitrogen-containing compounds, alcohol compounds, amide compounds, ketone compounds, thiocyanic acid compounds, amine compounds and imide compounds. The etching rate ratio between palladium and gold (etching rate of palladium / etching rate of gold) is not less than 1.US 2015 / 0 318 172 A1 discloses a method for structuring a semiconductor component. A three layer photoresist is formed over a plurality of patterned features. The three-layer photoresist comprises a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, wherein the top layer contains a photosensitive material. The top layer is patterned by a photolithography method, wherein the patterned top layer includes an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.Brief Description of the DrawingsAspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased. FIG. 1 illustrates forming an opening through a middle layer, in accordance with some embodiments. FIG. 2 illustrates the removal of the middle layer, in accordance with some embodiments. FIG. 3 illustrates the deposition of a masking layer, in accordance with some embodiments. FIG. 4 illustrates the fabrication of spacers in accordance with some embodiments. FIG. 5 illustrates removing a mandrel material from a space between the spacers, in accordance with some embodiments. FIG. 6 illustrates the patterning of a layer to be patterned, in accordance with some embodiments.Detailed DescriptionEmbodiments for semiconductor manufacturing processes with process nodes comprising a 20 nm process node, a 16 nm process node, a 10 nm process node, a 7 nm process node, a 5 nm process node or the like are described below. However, the described embodiments may be used in different application fields and are not limited to these embodiments.Referring now to FIG. 1, an embodiment is shown that includes a layer 101 to be patterned, a hard mask 103, a mandrel layer 105, a spacer material 107, a bottom layer 109, a middle layer 111, and a second photoresist 117. The layer 101 to be patterned may be: a layer of a semiconductor material; a top layer of a metallization layer; a dielectric layer (such as a passivation layer) formed over a semiconductor substrate (not individually shown); or another masking layer used to pattern a still further underlying layer. In an embodiment where the layer to be patterned 101 is a semiconductor material, the layer to be patterned 101 may be a semiconductor substrate with or without interposed active devices, metallization layers, and dielectric materials.In another embodiment, where the layer to be patterned 101 is a metallization layer, the layer to be patterned 101 may be formed of a conductive material by methods such as single damascene process, dual damascene process, deposition, patterning, etc. In a specific embodiment, the conductive material for the layer 101 to be patterned comprises at least one metal, a metal alloy, a metal nitride, a metal sulfide, a metal selenide, a metal oxide or a metal silicide. Specific examples are copper, titanium, aluminum, cobalt, ruthenium, titanium nitride, tungsten nitride (WN 2) and tantalum nitride, but alternatively another suitable material may be used.In yet another embodiment, the layer to be patterned 101 is a dielectric layer having a dielectric constant of about 1 to about 40. In particular examples, the dielectric layer for the layer to be patterned 101 may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, lanthanum oxide, other suitable low-k dielectric layers, combinations thereof, or the like, formed by such methods as deposition, oxidation, or the like.However, as one of ordinary skill in the art would recognize, materials, methods, and other details are described in the embodiments, but these details are intended to illustrate the embodiments only and are not intended to be limiting in any way. Rather, any suitable layer may alternatively be used, which is made of a suitable material and is manufactured with a suitable method and thickness. All of these layers are intended to be entirely within the scope of the embodiments.The first hard mask 103 is formed to function as an etch stop layer during the etching of the overlying mandrel layer 105 (discussed below).In some embodiments, the first hard mask 103 also functions as an anti-reflective coating. In an embodiment, the first hard mask 103 may be made of a material such as silicon oxide, such as borophosphosilicate tetraethyl orthosilicate (BPTEOS) or tetraethyl orthosilicate (TEOS) oxide, by CVD, ALD, spin coating, or the like. However, any suitable material and method for the preparation may be used.The mandrel layer 105 may be a dummy material, such as amorphous dummy silicon or dummy polysilicon (DPO), or another material that may be patterned. The mandrel layer 105 may be deposited by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), combinations thereof, or the like, to a thickness of about 10 nm to about 500 nm (about 100 Å to about 5000 Å), for example about 100 nm (1000 Å). However, any suitable material or deposition process or thickness may be used.After the mandrel layer 105 is formed, it may be patterned by placing a first photoresist (not individually shown in FIG. 1 ) over the mandrel layer 105. In one embodiment, the first photoresist is a tri-layer photoresist having a bottom anti-reflective coating (BARC) layer, a middle mask layer, and a top photoresist layer. However, any suitable type of light-sensitive material or combination of materials may be used.After the first photoresist is placed over the mandrel layer 105, the first photoresist is patterned. In one embodiment, the first photoresist may be patterned by exposing a photosensitive material in the first photoresist (e.g., the top photoresist layer in the three-layer photoresist) to a patterned energy source (e.g., light), e.g., through a reticle. The application of the energy results in a chemical reaction in the parts of the photosensitive material that the patterned energy source has acted upon, such that the physical properties of the exposed parts of the first photoresist are modified such that the physical properties of the exposed parts of the first photoresist are different from the physical properties of the unexposed parts of the first photoresist. Then, the first photoresist may be developed with, for example, a developer (not individually shown) to separate the exposed portion of the first photoresist from the unexposed portion of the first photoresist.After the mandrel layer 105 has been patterned, the spacer material 107 is conformally formed over the mandrel layer 105. After fabrication, the spacer material 107 runs along top and sidewalls of the mandrel layer 105 and along top surfaces of the first hard mask 103. The spacer material 107 may be made of titanium oxide (TiO x), AlO, AlN, AlON, TaN, TiN, Si, SiO, SiN, metals, metal alloys, and the like, and may be deposited by a suitable method such as ALD, CVD, or the like. The spacer material 107 may be deposited to a thickness of about 0.1 nm to about 30 nm, e.g., about 15 nm. However, any suitable materials, methods of manufacture, or thicknesses may be used.When the spacer material 107 is in place, first portions of the spacer material 107 are covered with a dielectric material 301 (not shown in FIG. 1 but shown in FIG. 3 and described with reference thereto) in a first region 113 over the layer 101 to be patterned, while second portions of the spacer material 107 are not covered with a dielectric material 301 in a second region 115 over the layer 101 to be patterned. The bottom layer 109 and the middle layer 111 are deposited on the spacer material 107 for protection. In an embodiment, the bottom layer 109 may be a BARC layer having different optical properties than the second photoresist 117 and acting to prevent uncontrolled and unwanted reflection of energy (e.g., light) into the second photoresist 117 during exposure of the second photoresist 117 such that the reflected light cannot initiate reactions in an unwanted region of the second photoresist 117. For example, the bottom layer 109 may have a different refractive index n, a different extinction coefficient k or a different thickness T than the second photoresist 117. In addition, the lower layer 109 may be used to provide a planar surface that helps reduce the negative effects of the angular incident energy.In one embodiment, the bottom layer 109 comprises a polymer resin, a catalyst, and a cross-linking agent, all of which are introduced into a BARC solvent for distribution. The polymer resin may comprise a polymer in which various monomers are linked together with a chromophore. The material for the bottom layer 109 may be applied to the spacer material 107 such that the material for the bottom layer 109 covers an exposed top surface of the spacer material 107, and may be applied by a method such as spin coating, dip coating, air knife coating, curtain casting, wire bar coating, gravure coating, laminating, extruder coating, combinations thereof, or the like. In an embodiment, the material for the bottom layer 109 may be deposited first to a thickness of about 10 nm to about 1000 nm, e.g., about 100 nm.The middle layer 111 may be disposed over the bottom layer 109. In an embodiment, the middle layer 111 may be an organic layer or an inorganic layer having a different etch resistance than the second photoresist 117. In a particular embodiment, the middle layer 111 is a hard mask material such as silicon, silicon nitride, an oxide, an oxynitride, or silicon carbide, combinations thereof, or the like. The hard mask material for the middle layer 111 may be deposited by a method such as chemical vapor deposition (CVD), but alternatively, other methods may be used, such as plasma enhanced chemical vapor deposition (PECVD), gravure chemical vapor deposition (LPCVD), spin coating, or silicon oxide deposition followed by nitriding. Any suitable method or combination of methods for depositing or otherwise placing the hard mask material may be used, and all of these methods or combinations are intended to be fully within the scope of the embodiments. The middle layer 111 may be formed to a thickness of about 10 nm to about 80 nm (about 100 Å to about 800 Å), e.g., about 30 nm (300 Å).The second photoresist 117 is disposed over the middle layer 111 to provide a patterned mask so that the middle layer 111 can be patterned into the desired pattern. In one embodiment, the second photoresist 117 is a photosensitive material that is spread over the middle layer 111 and then exposed to a patterned energy source (e.g., light) to initiate a chemical reaction in the portions of the photosensitive material that are exposed. This chemical reaction causes a change in physical properties which can be used in a development process to separate the exposed portions of the photosensitive material from the unexposed portion of the photosensitive material to produce a patterned photoresist.After the second photoresist 117 has been patterned to the desired pattern, it may be used as a mask for patterning the hard mask material of the middle layer 111. For example, the pattern of the second photoresist 117 may be transferred to the middle layer 111 with an anisotropic etch process, such as reactive ion etch (RIE), wherein ions of a suitable etchant, such as CF 4- O 2, may be used in a dry etch to remove portions of the middle layer 111 exposed by the patterned second photoresist 117. However, other suitable etchants such as CH 3 / O 2, CH 2 F 2, CH 3 F, or the like may be used, and other suitable removal methods such as wet stripping may be used.After the pattern of the second photoresist 117 is transferred to the middle layer 111, the middle layer 111 may be used to transfer the pattern of the second photoresist 117 to the bottom layer 109 to form openings 121 exposing a top surface of the spacer material 107. In an embodiment, the bottom layer 109 may be etched with an etching process using the second photoresist 117 and the middle layer 111 (now patterned) as a masking layer. The etching process may be a dry etching process using an etchant such as oxygen, nitrogen, hydrogen, ammonia, sulfur hexafluoride, difluoromethane, nitrogen trifluoride, chloro trifluoride, chlorine, carbon monoxide, carbon dioxide, helium, boron dichloride, argon, fluorine, trifluoromethane, tetrafluoromethane, perfluorocyclobutane, or perfluoropropane, or combinations thereof, or the like. However, any other suitable etching method may be used, such as wet etching, or wet etching performed simultaneously with the etching of the middle layer 111, and other suitable etchants may be used.In a particular embodiment, the openings 121 are formed to help place and position the subsequently deposited dielectric material 301 (discussed in more detail below with reference to FIG. 3 ). The openings 121 may be formed with a first width W 1 of about 10 nm to about 100 nm, e.g., about 64 nm. However, any suitable width may be used.FIG. 2 shows that after patterning either the middle layer 111 or the bottom layer 109, the second photoresist 117 may be removed from the middle layer 111. In an embodiment, a stripping process for removing the second photoresist 117 may be used, in which the temperature of the second photoresist 117 is increased to cause thermal decomposition of the second photoresist 117, which may then be removed with a cleaning process such as rinsing. Alternatively, the second photoresist 117 may be removed using a wet etching process, for example. Any suitable method of removing the second photoresist 117 may be used, and all of these methods are intended to be fully within the scope of the embodiments.After the second photoresist 117 has been removed, an etching process (represented by the symbols X denoted by 201 in FIG. 2 ) is also used to remove the middle layer 111. By removing the middle layer 111 prior to the deposition of the dielectric material 301, the height of the openings 121 is reduced. By removing the middle layer 111, the openings 121 may have a first height H 1 of about 30 nm to about 150 nm, e.g., about 100 nm, for example. However, any suitable height may be used.By decreasing the height of the openings 121, an aspect ratio of the openings 121, such as a ratio of the first height H 1 to the first width W 1, is also decreased. For example, in one embodiment, removing the middle layer 111 modifies the aspect ratio of the openings 121 from a range of about 0.4 to about 21 to a range of about 0.3 to about 15. With this reduction in aspect ratio, in a subsequent deposition process (described later with reference to FIG. 3 ), it becomes easier to fill the openings 121 without generation of voids. By reducing the number of cavities, the manufacturing process becomes simpler and fewer defects are produced.In an embodiment, the etching process 201 may be a wet etching process used to remove the middle layer 111. In a particular embodiment, the wet etching process uses a liquid etching solution that is brought into physical contact with the exposed portions of the middle layer 111, and components in the etching solution react with the material of the middle layer 111 such that the middle layer 111 is removed from the bottom layer 109. In some embodiments, the liquid etching solution includes an etchant, a spacer inhibitor, and a solvent.The etchant in the liquid etching solution is chosen to have a high etch selectivity for the material of the middle layer 111 without substantially removing the remaining exposed materials (e.g., the spacer material 107 and the material of the bottom layer 109). Therefore, the particular etchant to be selected will depend, at least in part, on the materials selected for the middle layer 111, the bottom layer 109, and the spacer material 107. However, in a particular embodiment where the middle layer 111 comprises an oxide, the bottom layer 109 comprises an organic material, and the spacer material 107 comprises titanium oxide (TiO 2) the etchant to be selected may comprise hydrofluoric acid (HF), tetramethylammonium hydroxide, tetramethylammonium fluoride, combinations thereof, or the like. However, any suitable etchant may be used.While the use of an etchant such as hydrofluoric acid is suitable for removing the material of the middle layer 111, the use of hydrofluoric acid also leads to considerable problems. For example, the liquid etching solution comes into physical contact not only with the exposed portions of the middle layer 111 but also with each surface of the walls of the openings 121, such as the lower layer 109 and the spacer material 107. If the hydrofluoric acid is used unchanged, it undesirably reacts with the spacer material 107, so that the spacer material 107 is removed and either undesired topographical changes occur or so large a portion of the spacer material 107 is removed that a cutting failure defect occurs. Such topographical variation affects subsequent processing (limiting the process window to accommodate this variation) or lowers the quality and yield of devices made by this process due to the cutting failure defects.To help avoid the undesired removal of the spacer material 107, the inhibitor is added, which is to inhibit the removal of the spacer material 107 during the etching process 201. In one embodiment, the inhibitor is a chelator that can be added to the liquid etching solution and serves to increase the etching selectivity of the etching solution, such that the spacer material 107 is removed at a lower rate. Thus, the inhibitor is at least partially dependent on the spacer material 107, the material of the middle layer 111 and the remaining components of the liquid etching solution. In an embodiment where the spacer material 107 is titanium oxide, the middle layer 111 comprises an oxide, and the etchant is hydrofluoric acid, the inhibitor may comprise an N-ethanolamide derivative ligand. In a particular embodiment, the inhibitor may have the structure: wherein R1is an organic group such as an alkyl group, an ester group, an aromatic group, a ketone group, an amide group, or a carbocyclic acid group, and R2is an organic group such as an alkyl group, an ester group, an aromatic group, a ketone group, an amide group, or a carbocyclic acid group, and R 1 and R 2 may combine to form a cycloalkane in some embodiments.In particular embodiments, the inhibitor may be 1-(2-hydroxyethyl)-2-pyrrolidinone, N,N-diethanolamide, N-hydroxyethyl phthalimide, 1-(2-hydroxyethyl)pyrrolidine-2,5-dione, or N-(2-hydroxyethyl)-1,2,3,6-tetrahydrophthalimide, each of which may have the following structures: The solvent of the liquid etching solution serves to buffer and dilute the etchant so that the etching rate of the etchant is in a controllable range. In addition, the solvent also enables a method of distributing the etchant and contracting the etchant to the middle layer 111. Thus, the solvent may be any suitable liquid which allows for the dispersion and control of the etchant and inhibitor. In a particular embodiment, the solvent may be water, but any other suitable liquid may also be used, such as glycol or alcohol.To prepare the liquid etching solution, the etchant and the inhibitor are added to the solvent either individually or simultaneously and mixed. In another embodiment, the etchant and solvent may be obtained together (e.g., as dilute hydrofluoric acid) and the inhibitor may be added to the solution. Any suitable method of mixing the individual components may be used to obtain the liquid etching solution.In one embodiment, the etchant is added to the solvent at a concentration of about 0.01 mass % to about 50 mass %, e.g., about 5 mass %. In addition, the inhibitor may be added to the solvent at a concentration of about 0.001% by mass to about 5% by mass, e.g., about 0.01% by mass. However, any suitable concentration may be used.In a particular embodiment, the etching solution may comprise a combination of tetramethylammonium hydroxide (about 0.5 mass %) and tetramethylammonium fluoride (about 1.5 mass %). These may be added to ethylene glycol at about 10 mass % to about 15 mass %. Finally, the inhibitor, e.g., N-ethanolamide derivative, is added at a concentration of about 1 mass % or less.After the etching solution is prepared, it may be brought into physical contact with the middle layer 111. In an embodiment, the etching process 201 may be performed by dipping the structure comprising the middle layer 111 and the spacer material 107 in a basin with the etching solution in a dipping method. However, any other suitable method of contacting the etching solution with the middle layer 111 may be used, such as stirring, spraying, combinations thereof, or the like.In an embodiment, the etching process 201 may be performed at a temperature of about 20° C. to about 80° C., e.g., about 40° C. Moreover, for removing the middle layer 111, the etching process 201 may be performed for less than about 15 min, e.g. about 4 min. However, any suitable temperature and duration may be used.By using the inhibitor, the middle layer 111 can be removed without excessive damage to the spacer material 107. For example, in an embodiment where the inhibitor has a concentration of 10 mass % and the ratio of hydrofluoric acid to water is 1:100, the etch rate of the spacer material 107 (if titanium oxide) may be reduced from greater than 1.375 nm (13.75 Å) / min to about 0.42 nm (4.2 Å) / min. Thus, at an etch time of 4 min at room temperature, the loss of the spacer material 107 can be decreased from more than 5.5 nm (55 Å) (or even 11 nm (110 Å)) to about 1.681 nm (16.81 Å).As another example, the concentration of inhibitor may be raised to about 40%. In this example, the etch rate of the spacer material 107 may be lowered still further to 0.229 nm (2.29 Å) / min. In this example, the thickness loss of the spacer material 107 (e.g., titanium oxide) is decreased to about 0.913 nm (9.13 Å).In another embodiment, the ratio of hydrofluoric acid to water may be about 1:500. Without the presence of the inhibitor, the etching process may have an etch rate of the spacer material 107 of about 0.228 nm (2.28 Å) / min. At room temperature, the amount of spacer material 107 lost may be about 0.912 nm (9.12 Å) with a 4 minute etch and about 4.043 nm (40.43 Å) with a 15 minute etch. However, when the inhibitor is added at a concentration of about 10%, the etching rate of the titanium oxide can be reduced to 0.14 nm (1.4 Å) / min. This results in a reduction in the loss of spacer material 107 to about 0.516 nm (5.61 Å).As another example, the concentration of inhibitor may be raised to about 40%. In this example, the etch rate of the spacer material 107 may be lowered still further to 0.039 nm (0.39 Å) / min. In this example, the thickness loss of the spacer material 107 (e.g., titanium oxide) is decreased to about 0.154 nm (1.54 Å) with an etch for about 4 minutes.Without being limited by any particular theory, it is believed that the inhibitor reacts with and bonds to free atoms of the spacer material 107, thereby preventing the free atoms from being available for reaction with the etchant. It is believed that in an embodiment where the spacer material 107 is titanium oxide and the inhibitor is one of the aforementioned inhibitors, the free oxygen pair in the inhibitor as an electron acceptor reacts with the titanium atoms, either with a single titanium atom or with multiple titanium atoms, to form a cyclic titanium intermediate as follows: For example, in a theory of a particular embodiment, the titanium can react with the free oxygen pair as an electron acceptor to form a cyclic titanium intermediate. By this intermediate, the N-ethanolamide derivative can serve as a titanium protection.It is believed that in a particular embodiment where the spacer material 107 is titanium oxide and the inhibitor is 1-(2-hydroxyethyl)-2-pyrrolidinone, the inhibitor will chelate the titanium, either with only one titanium atom or with multiple titanium atoms, as follows: FIG. 3 shows that after removing the middle layer 111 and reducing the aspect ratio of the openings 121, the spacer material 107 located over the first region 113 of the layer 101 to be patterned may be protected by covering or masking the spacer material 107 in the first region 113 of the layer 101 to be patterned with the dielectric material 301. For example, in one embodiment, dielectric material 301 may be a low temperature silicon oxide, but any suitable dielectric material may be used. However, other suitable materials such as oxides and nitrides may be used.In an embodiment, the dielectric material 301 may be deposited using a deposition method such as atomic layer deposition (ALD). For example, in one embodiment, the remaining structure comprising the spacer material 107 and the bottom layer 109 may be treated with a first precursor that reacts with the exposed surfaces of the spacer material 107 and the bottom layer 109 in a self-limiting reaction. After the first precursor is removed, the surface is treated with a second precursor that reacts with the products of the first precursor in another self-limiting reaction and completes a first cycle to form a first monomolecular layer of the dielectric material 301 (individual monomolecular layers are not individually shown in FIG. 3 ). The first cycle may then be repeated (e.g., the first monomolecular layer may be treated with a first precursor and then with a second precursor) to form a second monomolecular layer over the first monomolecular layer and increase the overall thickness of the dielectric material 301. The multiple cycle atomic layer deposition process may be continuously repeated until the thickness of the dielectric material 301 is so large as to fill and overfill the openings 121, i.e., until a thickness of about 5 nm to about 200 nm (50 Å to about 2000 Å), e.g., about 50 nm (500 Å), has been reached. However, any suitable thickness may be used.In a particular embodiment, the dielectric material 301 may be an oxide, such as a low temperature oxide. In this embodiment, the first precursor may be a silane, while the second precursor may be an oxidizing precursor, such as water, oxygen, or an oxygen-containing plasma. Although these precursors are given, any suitable precursor materials may be used.By removing the middle layer 111 before depositing the dielectric material 301, the aspect ratio of the openings 121 before depositing the dielectric material 301 has also been reduced. Thus, problems arising from attempting to deposit materials in high aspect ratio openings, e.g., formation of voids in the deposited material, may be reduced or eliminated. In addition, by adding the inhibitor to the liquid etching solution, the negative effects of etching the spacer material 107 during the removal of the middle layer 111 may be reduced or eliminated.FIG. 3 also illustrates the patterning of the dielectric material 301 to expose the spacer material 107 over the second region 115 of the layer 101 to be patterned. In an embodiment, a third photoresist (not individually shown) is placed over the dielectric material 301 and patterned to expose the portion of the spacer material 107 in the second region 115. After the third photoresist has been patterned, the dielectric material 301 may be removed, e.g., with an anisotropic etch process, such as reactive ion etching, and the third photoresist may be removed, e.g., with a stripping process. However, any suitable etching process may be used to expose the spacer material 107 over the second region 115 of the layer 101 to be patterned.FIG. 4 shows the production of spacers 401 from the spacer material 107 over the second region 115 of the layer 101 to be structured. In one embodiment, the spacers 401 are made from the spacer material 107 by anisotropically etching the spacer material 107 and removing it from the horizontal surfaces of the mandrel layer 105. However, any suitable method may be used.FIG. 5 shows that after the production of the spacers 401, the mandrel layer 105 can be removed from the intermediate space between the spacers 401. In one embodiment, the mandrel layer 105 may be removed with a wet etch, but alternatively any suitable etching process, such as dry etch, may be used. For example, when silicon is used to form the mandrel layer 105, an etchant such as HF may be used to remove the mandrel layer 105 without substantially removing one of the spacers 401. By using the mandrel layer 105 to form the spacers 401 and then removing the mandrel layer 105, a mask having smaller dimensions than those of the mandrel layer 105 (which may be limited by the lithographic method used) can be obtained.FIG. 6 shows that after the production of the spacers 401 and the removal of the mandrel layer 105 between the spacers 401, the structure of the spacers 401 may be transferred to the underlying first hard mask 103 and the underlying layer 101 to be patterned. In an embodiment, the structure of the spacers 401 may be transferred with one or more anisotropic etching processes, such as reactive ion etching. However, any suitable method of transferring the structure of the spacers 401 into the underlying layers may be used.By using the inhibitor in the liquid etching solution, the middle layer 111 can be removed to reduce the aspect ratio of the openings 121. Therefore, a potentially negative effect (e.g., voids) of using an atomic layer deposition process to deposit a material such as a low temperature oxide may be better avoided. Therefore, the other benefits of other materials can be utilized in the preparation, such as reduced low temperature oxide topographical charges, selectivity of the low temperature oxide to titanium oxide (e.g., 0.78), or control of the adjustable critical dimensions of the low temperature oxide. These benefits allow for a lower cut failure rate due to RM quality problems or topographical charges.In one embodiment, a method of manufacturing a semiconductor device includes patterning a middle layer to expose a spacer material; and applying an etchant to come into physical contact with the middle layer and the spacer material, the etchant including an inhibitor that inhibits an etch rate of the spacer material. In one embodiment, the etchant comprises dilute hydrofluoric acid. In one embodiment, the spacer material is titanium oxide. In one embodiment, the inhibitor comprises an N-ethanolamide derivative ligand. In one embodiment, the inhibitor is a chelator. In an embodiment, the method further includes depositing a dielectric material over the spacer material. In an embodiment, the depositing of the dielectric material is performed at least partially using an atomic layer deposition process.In one embodiment, a method of manufacturing a semiconductor device includes the steps of: depositing a spacer material over a mandrel; placing a tri-layer photoresist over the spacer material, the tri-layer photoresist comprising a bottom layer, a middle layer, and a photoresist; patterning the middle layer and the bottom layer to form a first opening and expose the spacer material; removing the middle layer with an etching solution, the etching solution including an inhibitor to reduce an etching rate of the spacer material during the removal of the middle layer; and filling the first opening with a masking material. In one embodiment, the method includes filling the first opening at least partially using an atomic layer deposition process. In an embodiment, filling the first opening includes filling the first opening with a dielectric material. In one embodiment, the dielectric material is void-free. In an embodiment, the dielectric material is an oxide. In one embodiment, the dielectric material is a low temperature oxide. In one embodiment, the inhibitor has a concentration of about 10% to about 40%.A method of manufacturing a semiconductor device comprises the steps of: patterning a middle layer and a bottom layer to expose a layer of titanium oxide; applying an etchant to remove the middle layer; and reducing an etch rate of the layer of titanium oxide by simultaneously applying an inhibitor to the layer of titanium oxide, the inhibitor having an N-ethanolamide derivative ligand. In one embodiment, the inhibitor is 1-(2-hydroxyethyl)-2-pyrrolidinone. In one embodiment, the inhibitor is N,N-diethanolamide. In one embodiment, the inhibitor is N-hydroxyethylphthalimide. In one embodiment, the inhibitor is 1-(2-hydroxyethyl)pyrrolidine-2,5-dione. In one embodiment, the inhibitor is N-(2-hydroxyethyl)-1,2,3,6-tetrahydrophthalimide.

Claims

A method of manufacturing a semiconductor device, comprising the steps of: depositing a spacer material (107) over a top surface and sidewalls of a mandrel (105); placing a layer (111) over the spacer material (107); patterning the layer (111) to form an opening (121) and expose the spacer material (107); and applying an etchant to physically contact the layer (111) and the spacer material (107) on the sidewall of the mandrel, wherein the etchant comprises an inhibitor that inhibits an etch rate of the spacer material (107).The method of claim 1, wherein the etchant comprises dilute hydrofluoric acid.The method of claim 1 or 2, wherein the spacer material (107) is titanium oxide.The method of any preceding claim, wherein the inhibitor comprises an N-ethanolamide derivative ligand.The method of any preceding claim, wherein the inhibitor is a chelator.The method of any preceding claim, further comprising depositing a dielectric material (301) over the spacer material (107).The method of claim 6, wherein the depositing of the dielectric material (301) is performed at least partially using an atomic layer deposition process.A method of manufacturing a semiconductor device, comprising the steps of: depositing a spacer material (107) over a mandrel (105); placing a tri-layer photoresist over the spacer material (107), the tri-layer photoresist comprising: a bottom layer (109), a middle layer (111), and a photoresist (117); patterning the middle layer (111) and the bottom layer (109) to form a first opening and expose the spacer material (107); removing the middle layer (111) with an etching solution, the etching solution having an inhibitor to reduce an etching rate of the spacer material (107) during the removal of the middle layer (111); and filling the first opening with a masking material.The method of claim 8, further comprising filling the first opening at least partially using an atomic layer deposition process.The method of claim 9, wherein filling the first opening comprises filling the first opening with a dielectric material.The method of claim 10, wherein the dielectric material is void-free.The method of claim 10 or 11, wherein the dielectric material is an oxide.The method of any of claims 10 to 12, wherein the dielectric material is a low temperature oxide.The method of any one of claims 8 to 13, wherein the inhibitor has a concentration of about 10% to about 40%.A method of manufacturing a semiconductor device, comprising the steps of: patterning a middle layer (111) and a bottom layer (109) to expose a layer of titanium oxide; applying an etchant to remove the middle layer (111); and reducing an etching rate of the layer of titanium oxide by simultaneously applying an inhibitor to the layer of titanium oxide, the inhibitor having an N-ethanolamide derivative ligand.The method of claim 15, wherein the inhibitor is 1-(2-hydroxyethyl)-2-pyrrolidinone.The method of claim 15, wherein the inhibitor is N,N-diethanolamide.The method of claim 15, wherein the inhibitor is N-hydroxyethylphthalimide.The method of claim 15, wherein the inhibitor is 1-(2-hydroxyethyl)pyrrolidine-2,5-dione.The method of claim 15, wherein the inhibitor is N-(2-hydroxyethyl)-1,2,3,6-tetrahydrophthalimide.

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