Printed circuit board technology for power electronic circuits

Abstract

Method for manufacturing a circuit board (100, 220, 300, 400, 500, 600, 700) for power electronic circuits, where the circuit board (100, 220, 300, 400, 500, 600, 700) comprises at least two inlay layers, wherein each inlay layer has a metallic inlay (112, 122) whose thickness is in the millimeter range, wherein the spaces between the metallic inlay (112, 122) are filled with a non-conductive material (114, 124, 204, 714), wherein an intermediate layer (102, 718) with at least one metallization layer is arranged between at least two adjacent inlay layers, wherein the intermediate layer (102, 718) has a plurality of vias to an inlay layer covered by it, and wherein at least one recess (116, 126) is provided in at least one first inlay layer, which is designed to mount at least one electronic component (106, 502, 602, 704), namely at least one power electronic component, on a second inlay layer, wherein, in order to provide a screw point for the circuit board (100, 220, 300, 400, 500, 600, 700) in an inlay position, a part of a metallic inlay (112, 122) protrudes from the circuit board (100, 220, 300, 400, 500, 600, 700) by a distance.

Description

[0001] The present invention relates to a method and a system for producing circuit boards for power electronic circuits.

[0002] Conductor paths on circuit boards of power electronic circuits exhibit high switching inductances. If, for example, a current is switched between two conductor paths using one or more half-bridges, a magnetic field around a first conductor path must be reduced and built up around a second conductor path, or energy from the magnetic field around the first conductor path must be dissipated by a first current flow, and energy from the magnetic field around the second conductor path must be provided by a second current flow. Therefore, rapid, and in this case, small, energy transfer is only possible at locations where the magnetic fields of the old and new conductor paths overlap and are of a similar magnitude. If this is not the case, the transfer requires a time expenditure that can range from several tens of nanoseconds to several microseconds.Furthermore, the discharge / buildup currents in the half-bridges are driven by opening switches and can potentially damage electrical components in a circuit. To mitigate this, the current-switching time is extended sufficiently to prevent switches from being opened while a magnetic field is still dissipating. Additionally, relief circuits, so-called snubbers, can be used to dissipate the currents. However, both methods generate high losses because the currents flowing during the extended switching time are generally converted into heat.

[0003] While conventional power electronics were mostly implemented with discrete components, such as thyristors and IGBTs (insulated-gate bipolar transistors), with screw terminals and busbars, the latest power transistors allow the integration of high-performance circuits into typical printed circuit boards (PCBs). However, with typical metal thicknesses of 35 µm, such boards, known to those skilled in the art as printed circuit boards (PCBs), are not capable of conducting high currents or absorbing their waste heat.

[0004] In recent years, LED technology has triggered various developments in circuit board technology to enable higher currents and the associated heat dissipation. For example, the document DE 10 2012 211 143 A1 describes a printed circuit board with recesses for accommodating an electrical component, which may be an LED, with heat-conducting elements underneath. This creates a thermal feedthrough to a heat sink located on the underside of the circuit board. However, with only two connections, LEDs are simple compared to transistors or even complete power electronic circuits.

[0005] In particular, modern modular power electronics circuits such as those described in SM Goetz, T. Weyh, “Modular Multilevel Converter with Series and Parallel Module Connectivity: Topology and Control.” in IEEE Transactions on Power Electronics, vol. 30, no. 1, pp. 203-215, 2015, or in the publication US 9 496 799 B2, which decompose high powers into small, board-integrated powers and handle them with low-voltage semiconductors, require a way to conduct these powers and currents on boards.

[0006] Furthermore, modern, fast-switching power semiconductors require very compact circuit implementations to avoid any speed losses. This is primarily due to the high so-called parasitic inductances that arise in large circuit designs. The magnetic energies stored in the parasitic inductances can be unintentionally discharged during switching operations and generate switching overvoltages that can damage or destroy components.

[0007] Many power electronic circuits would allow a significant reduction in parasitic inductances if they could be constructed with multiple conductor layers, as described, for example, in document DE 10 2007 006 462 A1. Furthermore, multiple layers, as is familiar from conventional low-power circuit boards, also allow compensation of electric fields of opposing currents, as is specifically used in document DE 10 2016 106 359 A1 to reduce unwanted switching peaks.

[0008] While conventional printed circuit boards are typically manufactured with a certain number of copper layers approximately 35 µm to 70 µm thick, there are now ways to produce boards with several layers of 400 µm or more using a very similar manufacturing process. As with standard printed circuit boards, the copper layer is deposited over the entire surface electrolytically, i.e., galvanically, or laminated as a metal foil. This is followed by a coating with a photoresist, which is exposed positively or negatively with a corresponding pattern, developed, and then partially removed. Finally, the areas no longer covered by photoresist are wet-chemically etched.

[0009] However, copper etching is largely isotropic and unidirectional, and therefore also etches from the side into the copper areas still covered by the photoresist, a form of undercutting. Therefore, the resolution of the possible structures decreases with layer thickness. Furthermore, etching such thick layers requires a large amount of chemicals. Furthermore, the etching process is slow.

[0010] Furthermore, the same layer thickness must generally be used across the entire circuit board, since the copper for each layer is initially deposited evenly by electrolytic means. Otherwise, almost all established manufacturing methods can be used to locally connect different layers of the circuit board, for example, through through-hole plating, a so-called via. One example is the publication DE 10 2014 224 033 A1, which describes the pressing of the carrier and conductor layers of a circuit board, thereby accommodating an electronic component in a recess via solderless press contacts.

[0011] Since the etching of thick copper is usually limited to layer thicknesses well under one millimeter, so-called inlays are often created for greater thicknesses of just a few millimeters. Inlays are cut onto the copper according to the required shape, e.g., using waterjet cutting, milling, or punching. The parts must then be embedded into a circuit board. The inlay is usually inserted into an inner layer of the circuit board. The empty spaces created at the level of the inserted solid copper elements must be filled with material, usually with preimpregnated fibers abbreviated as prepreg, e.g., FR4 or similar. This can be done either directly, by filling the empty spaces with appropriate glass fiber composite materials, which are then cured, or indirectly, by manufacturing a negative element of the inlay elements, into which the copper parts are inserted and then impregnated with resin or pressed.

[0012] In the current state of the art, circuit boards for so-called surface-mount semiconductors, also known in technical jargon as SMD (surface-mount device), or SMT (surface-mounting technology), are offered with only one inlay layer on the surface and, if necessary, several usually etched circuit board layers above or below. This prevents overlapping current paths from being implemented.

[0013] While embedding multiple inlay layers using a state-of-the-art process would be possible in principle, the problem is that standard methods do not allow for a cost-effective conductive connection, i.e., through-plating, from the surface to all stacked inlay layers. Connecting the further-flung circuit board layers for high currents and / or heat dissipation would be difficult and costly. Furthermore, the overall thickness of the circuit board would increase by several millimeters with each inlay layer. Furthermore, the height of the components attached on one or even both sides by soldering must be taken into account in this overall height. In power electronic circuits, these components consist primarily of power semiconductors such as field-effect transistors and the like.

[0014] DE 10 2006 004 332 A1 discloses a multifunctional printed circuit board with several substrates arranged one above the other, some of the substrates having conductor track structures. A component is arranged on the substrate in a cavity of the substrates.

[0015] Against this background, it is an object of the present invention to provide a method for cost-effective circuit board technology for interconnecting power electronic components, which minimizes the buildup of magnetic fields on the line connections to the power electronic components while simultaneously enabling heat dissipation from the power electronic components. Furthermore, an object of the present invention is to provide a corresponding system for implementing such a method.

[0016] To achieve the above-mentioned object, a method for producing a circuit board for power electronic circuits is presented, in which the circuit board comprises at least two inlay layers, wherein a respective inlay layer has a metallic inlay whose thickness is in the millimeter range, wherein intermediate spaces of the metallic inlay are filled with a non-conductive material, wherein a respective intermediate layer with at least one metallization layer is arranged between at least two adjacent inlay layers, wherein the respective intermediate layer has a plurality of vias to an inlay layer covered thereby, wherein at least one recess is provided in at least one first inlay layer, which recess is designed to mount at least one electronic component, namely at least one power electronic component, on a second inlay layer,wherein, to provide a screwing point for the circuit board in an inlay layer, a part of a metallic inlay protrudes from the circuit board by a certain distance.

[0017] In addition to the obvious advantage that an electronic component embedded in a recess does not contribute to the overall thickness of the board, thus saving installation space, this solution allows the electronic components to be brought closer to the respective metallic inlay. It is advantageous to mount each electronic component directly on the inlay metal. This eliminates the need to conduct current through long, lossy vias from a board surface to the depth of the respective inlay. Furthermore, the thermal connection to the thermally conductive inlay metal and its thermal capacity are excellent, compared to conventional solutions. Copper or aluminum are particularly chosen as the material for the metallic inlay.

[0018] Embedding at least one power electronic component in a recess near an inlay significantly reduces the area covered by the current paths and thus parasitic inductances. This avoids the disadvantage of a conventional multilayer board with several layers of thicker copper, for example, with a copper layer thickness of approximately 400µm each, which would increase the board thickness and place the components, which are usually connected on the top and bottom layers, at a considerable distance from each other and from the lower metal layers.

[0019] Mounting a power electronic component in a recess can be achieved by soldering the component's housing in a similar way to a surface soldering process known from the prior art. When applying solder paste in a so-called reflow soldering process, the non-flat surface of the circuit board must be taken into account, which is why conventional flat screen-printed masks are generally inadequate. One possible embodiment involves the use of a three-dimensional mask in which a recess in the inlay layer is represented by a corresponding depression. Advantageously, solder is applied, at least within the recess, using a so-called CNC dispenser, i.e., a computer-aided, numerically controlled solder distributor. Furthermore, contacting the electronic component can be achieved by wire bonding.Alternatively, instead of the housing typically found around an electronic component, the electronic component embedded in the housing, e.g., a so-called bare die in the case of a semiconductor chip, can be mounted directly into the recess. Installing such an electronic component without a housing offers the advantages of better thermal connection, lower connection inductance and resistance, smaller space requirements, and therefore higher power density, at lower overall costs. Electrical contact, particularly for contacts located on the top side of the component, is advantageously achieved using wire bonding, as is also customary in semiconductor packaging according to the state of the art.

[0020] In one embodiment of the method according to the invention, a respective inlay layer is covered by at least one insulation layer. It is particularly advantageous to cover an inlay layer with an insulation layer near a circuit board surface. Conventionally etched copper layers can be placed on this insulation layer, as has previously been the case with circuit boards with a single inlay layer. In this way, multiple inlay layers can be embedded in a circuit board, for example, to enable overlapping current paths.

[0021] In a further embodiment of the method according to the invention, at least one insulation layer is provided with a plurality of vias to the inlay layer it covers. This can be done, for example, by drilling through the insulation layer to the inlay layer, with the respective drill hole being filled with a conductive material, which is done, for example, by electroplating. A contact surface of an electronic component, e.g. a semiconductor chip, in which the contact surface is located on an underside, can be connected to the inlay layer, for example, by these electroplated vias. The corresponding connection surfaces of the semiconductor are technically treated like an inlay. The electroplating can be carried out using two or more different materials for better adhesion, for example titanium or chromium followed by copper, aluminum, or silver.Gold as a terminal layer can limit chemical influences and corrosion. Silver, on the other hand, can improve conductivity. Electroplating automatically creates continuous electrical and thermal conductivity from the corresponding contact surface of the electronic component to the corresponding conductor track within the circuit board.

[0022] The metallization layer of the respective intermediate layer can be manufactured conventionally, i.e., for example, by electrodeposition or lamination with metal foil, etc., in thicknesses of, for example, 35 µm, 70 µm, 105 µm, etc., and then photochemically patterned with photoresist and wet-chemically etched, for example, with ferric chloride or sodium persulfate. The size of a conductor track formed in the metallization layer, for example in a semiconductor chip, is dimensioned such that sufficient control of so-called gate connections and the associated return channel to a so-called source connection is guaranteed. The metallization layer responsible for connecting the control is advantageously located on the side of the intermediate layer that is directly accessible in the corresponding recess for connection processes such as soldering and bonding.

[0023] A power electronic component is mounted on such an intermediate layer, which is located between two adjacent inlay layers. The patterning required for the so-called footprint of an electronic component is applied to the metallization layer of the intermediate layer. As mentioned in the previous paragraph, the intermediate layer is conventionally laminated or coated with metal foil and etched, thus allowing the high resolutions required, for example, for contacting the gate terminals of SMD transistors.

[0024] Alternatively, only those connections and lines requiring high resolution, such as the control lines for SMD transistors, can be provided in the intermediate layer, while the inlay metal at the locations of the components' power contacts is only locally stripped of any insulation layers to provide well-structured metal surfaces at the location of the corresponding connections of the electronic component. To make the inlay flush with the surface of the intermediate layer on which the component is to be mounted for a better soldering process or similar, metal can also be locally deposited onto the inlay to grow the exposed connections of the inlay until they are flush with the adjacent surface.

[0025] In a further embodiment of the method according to the invention, at least one recess is provided in at least one intermediate layer, wherein the at least one recess is congruent or aligned with a respective recess of an adjacent inlay layer. Particularly in the case of more than two inlay layers with a respective intermediate layer, an intermediate layer can have a corresponding recess so that access to a side of a first inlay layer facing the recesses is also possible through recesses in further inlay layers.

[0026] In one embodiment of the method according to the invention, a respective intermediate layer has a plurality of through-contacts, so-called vias, in particular micro-vias, to a respective inlay layer adjacent to the respective intermediate layer. The current and heat from power electronic components mounted on a respective intermediate layer can be conducted directly via the largest possible number of through-contacts to the adjacent inlay layer, which has a significantly lower spatial structuring resolution compared to an intermediate layer. Accordingly, an intermediate layer can be prepared as a carrier, which is provided with holes. These holes are then electrically and thermally connected by electroplating the through-contact, for example after mechanically fixing a semiconductor chip, for example using an adhesive, at the desired location.For this purpose, the semiconductor chip advantageously has a metallization on the surface to be contacted.

[0027] Additional metallization layers can be added within the intermediate layer, separated by an electrically insulating carrier material, e.g., epoxy, possibly with glass fiber reinforcement, e.g., as prepreg material with FR4. If these metallizations carry signals for one of the electronic components in one of the recesses, these signals are routed to the exposed layers on the contact surface via metallized vias.

[0028] The intermediate layer also has the advantage that elements of two adjacent inlay layers can be electrically and thermally connected very easily using conventional technologies, as each inlay layer can be connected to the corresponding intermediate layer via vias. For this purpose, the insulation layer between the corresponding inlay element and a metallization layer of the intermediate layer is drilled, cut, or milled and then metallized, for example by electroplating. This step is carried out in an intermediate layer for the at least two inlay parts that are to be electrically and thermally connected to the same metallization layer. The intermediate layer therefore serves to create the connection between the inlay layers, whereas a direct connection between inlay layers is difficult using traditional technologies, as after two inlay layers have been joined, possibly with insulation, for example.with epoxy, none of the surfaces are available for drilling and metallization deposition. The intermediate layer thus avoids the problem of not being able to create direct vias between two inlays, because with opaque carrier material neither optical nor mechanical access for drilling or even for galvanic metallization of the holes is available. In the embodiment of the method according to the invention with an intermediate layer, however, the connection to the intermediate layer can be created separately from the two opposite sides at locations where there is as vertical access as possible for drilling through the intermediate layer to the corresponding inlay element. Subsequent galvanic metallization to fill the hole is also possible.Through this via metallization, i.e. the deposition of conductor material into the drill hole, there is a direct connection between the metal of the inlay and the metal of a metallization layer of the intermediate layer.

[0029] Furthermore, the intermediate layer offers advantages during a thermal connection process, such as soldering, between an electronic component and an inlay layer. Especially during the creation of a solder connection with an inlay layer, this layer constantly dissipates heat, which is generally compensated for in the current state of the art by increasing the heat input to maintain the required temperature during the soldering process. Despite the connection to the inlay layers via the vias, the thermal dissipation of the intermediate layers is significantly lower, thus reducing the heat load on the board and, in particular, the electronic components.

[0030] At the same time, the circuit board technology presented according to the method according to the invention offers a thermally extremely conductive path for the heat development of the electronic components during operation, starting with the contacts of the electronic components, via the intermediate layer and up to the inlay metal. Despite the reduced thermal conductivity compared to direct contact between the inlay metal and an electronic component, the overall heat capacity is not reduced due to the complete presence of the inlay metal. On the other hand, regardless of whether materials with potentially higher thermal conductivities are used within the intermediate layers, the thermal conductivity of components up to the intermediate layer is still limiting. It is therefore advantageous to specifically coat the carrier material of the intermediate layer, e.g. epoxy, with highly conductive materials, e.g.Ceramic powder such as zinc oxide, aluminum oxide or titanium oxide, to achieve locally increased thermal conductivity, if necessary between several metallization and insulation layers of an intermediate layer.

[0031] In the recess, all parts of the interlayer's metallization that are not required for the direct connection process, such as soldering or bonding, can be coated with a lacquer. This lacquer, e.g., epoxy-based solder mask, is preferably applied only within a surface area of ​​a recess on the interlayer to avoid complicating the subsequent application of inlay layers or conventional multilayer PCB layers with a chemically inert coating, and to save material.

[0032] Preferably, the solder mask is applied in a recess after all circuit board layers have been completely applied, along with the solder mask on the top and bottom of the board. Common methods include screen printing, curtain coating, or spraying.

[0033] Different vertical heights of the respective layers, or the deepening of the recesses, can be achieved, in particular, by using photo-structureable resist, e.g., UV-curable resist, in combination with a uniformly wetting, flat coating process. In this case, the coating is applied to the surfaces and the recesses together. Curing and structuring can then be performed selectively by appropriate exposure only at those areas that need to be covered, for example, to cover a metal away from solder joints and a raw PCB substrate.

[0034] In one embodiment of the method according to the invention, at least one recess of an inlay layer is filled with an insulating material, which serves to improve thermal dissipation, provide touch safety, and / or shield against chemical influences. A recess can be potted using typical potting compounds. These can be, for example, two-component materials, solvent-based materials, UV-curing resins, or pressed granules. Advantageous materials can be based on epoxies or polyurethanes, for example. For increased thermal conductivity, a polymer carrier matrix can be filled with thermally conductive materials, such as zinc oxide, titanium oxide, or aluminum oxide, whereby the grain size should generally be less than half the smallest dimension of a recess.

[0035] Especially when installing unencapsulated semiconductor chips, filling the recess is indicated to provide shielding against chemical influences, such as oxidation, moisture, and light. The encapsulating material is preferably as optically opaque as possible in the spectral range critical for the semiconductor chip. Suitable materials include epoxy, pre-impregnated fiber materials such as prepreg, polyurethanes, silicones, or thermoplastics.

[0036] Furthermore, a circuit board for power electronic circuits is claimed, which has at least two inlay layers, wherein a respective inlay layer consists of a metallic inlay whose thickness is in the millimeter range and a non-conductive material which fills spaces between the metallic inlay, wherein at least a first inlay layer has at least one recess whose size is designed to enable mounting of at least one electronic component on a second inlay layer.

[0037] In a further embodiment, a circuit board is claimed in which the at least one electronic component mounted within the at least one recess is a power electronic component.

[0038] In yet another embodiment, a circuit board is claimed in which at least one inlay layer is covered by at least one insulation layer and which has a plurality of vias.

[0039] In one embodiment of the circuit board according to the invention, it comprises a respective intermediate layer with at least one metallization layer between at least two adjacent inlay layers, wherein the respective intermediate layer has a plurality of vias to an inlay layer covered by it.

[0040] Connecting fine contacts, such as the gate of an SMD transistor, requires high-resolution structuring and precise positioning, often involving considerable technical effort. In addition to the two power contacts, the drain and source, through which a load current is to flow and which are to be connected to the inlay, the gate connection, the control connection of power transistors, is also required. In commercially available SMD transistors, the distance between the gate and the adjacent source connection is often well under one millimeter, e.g., 500 µm. Furthermore, the size of the connection is often similar. This distance is significantly below the cost-effective resolution for inlays. The solution is provided by an intermediate layer of the circuit board according to the invention.

[0041] Finally, in a further embodiment, a circuit board is claimed in which at least one electronic component is installed within at least one recess of an inlay layer and the at least one recess is filled with an insulating material.

[0042] Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawings.

[0043] It is understood that the features mentioned above and those to be explained below can be used not only in the combination specified in each case, but also in other combinations or on their own, without departing from the scope of the present invention.

[0044] The figures are described coherently and comprehensively; the same components are assigned the same reference symbols. Fig. 1 shows a schematic representation of the structure of a circuit board produced according to an embodiment of the method according to the invention. Fig. 2 shows a schematic representation of a connection process from a production of a circuit board according to a further embodiment of the method according to the invention. Fig. 3 shows a schematic representation of a structure of a circuit board with vias, which is manufactured according to yet another embodiment of the method according to the invention. Fig. 4 shows a schematic representation of a structure of a circuit board with electronic components installed in recesses, manufactured according to an embodiment of the method according to the invention. Fig. 5 shows a schematic representation of a structure of a circuit board with an electronic component installed without a housing, manufactured according to an embodiment of the method according to the invention. Fig. 6 shows a schematic representation of a structure of a circuit board with an electronic component installed without a housing and connected by vias, manufactured according to an embodiment of the method according to the invention. Fig. 7 shows a schematic representation of a three-dimensional view of a circuit board produced according to an embodiment of the method according to the invention.

[0045] In Fig. 1 shows a schematic representation of the structure of a circuit board 100 produced according to an embodiment of the method according to the invention. Two inlay layers 110 and 120 with thicknesses in the millimeter range are connected to one another via an intermediate layer 102. The thickness of the intermediate layer 102 can be, for example, 35 µm. The inlay layers have a respective metallic inlay 112 or 122, the thickness of which can be, for example, 2 mm and is encased by prepreg 114 or 124. The respective metallic inlays 112 and 122 have a plurality of through-contacts, designated in two examples by reference numeral 104, so-called vias, to the intermediate layer 102. The through-contacts 104 can, for example, be drilled or laser-cut and then electrolytically filled with a metal. In recesses 116 and 126, electronic components 106 are soldered to the intermediate layer 102 by means of solder 118.An electronic component 106 can, for example, be an SMD field-effect transistor. The cutouts 116 and 126 enable the respective electronic component 106 to be connected in close proximity to the respective metallic inlay 112 and 122, respectively, thereby avoiding current losses, improving thermal dissipation of heat from an electronic component 106, and significantly reducing so-called parasitic inductances. Furthermore, the overall height of the circuit board 100 is minimized, e.g., by the cutout 116. In the lower inlay layer, the rightmost part of the metallic inlay 122 protrudes to the right by a distance 128 from the circuit board 100. This is used for a screw-on point for the circuit board 100. For example, on the underside of the lower inlay layer, another electronic component 108, e.g. an SMD capacitor, is connected to a metallization layer 132.Furthermore, an additional metallization layer 134 exemplifies how an inlay layer can contain, in addition to a metallic inlay a few millimeters thick, additional metallization layers of, for example, 35 µm, 70 µm, or 105 µm thickness. Both the metallization layer 132 and the metallization layer 134 can be connected to the metallic inlay 122 by a plurality of vias.

[0046] In Fig. Figure 2 shows a schematic representation of a connection process 212 for producing a circuit board 220 according to an embodiment of the method according to the invention. Reference numeral 210 encloses the layers required here, by way of example, for producing the circuit board 220.

[0047] Each inlay layer consists of a respective metallic inlay 112 or 122, wherein a non-conductive material 204, preferably prepreg, has been pressed into the gaps formed by the respective metallic inlay 112 or 122. An upper and a lower inlay layer are sealed at the top and bottom by insulation layers 202, for example made of prepreg. Furthermore, an intermediate layer 206 containing a metallization layer is located between the two inlay layers. The various layers are joined 208 by a bonding process 212, which may consist of an adhesive process or thermally assisted pressing. An intermediate layer can also be covered by applying a thin resin layer, similar to a solder mask.

[0048] In Fig. 3 shows a schematic representation of a circuit board 300 with through-holes according to an embodiment of the method according to the invention. Fig. 2, a plurality of vias, for example, at reference numeral 302, were applied to the circuit board 300 by drilling and metallization at recesses where a surface of the intermediate layer is accessible. Such vias not only provide a connection option for an electronic component, but also indirectly establish a connection between the metallic inlays 112 and 122 of the two inlay layers via the metallization layer of the intermediate layer. Generally, a current can be conducted across multiple metallization layers that are connected by a plurality of vias.

[0049] Fig. 4 shows a schematic representation of a structure of a circuit board 400 with electronic components installed in recesses 116 and 126 according to one embodiment of the method according to the invention. In the exemplary embodiment shown, the electronic components 106 are attached directly, i.e., without an intermediate layer, to the respective metallic inlay 112 or 122 at locations 402 or 404. By omitting an intermediate layer, the thermal connection of the installed electronic components 106 to the respective metallic inlays is excellent. Furthermore, the structure shown has the advantage that the electronic components 106 embedded in the recesses do not contribute to the overall thickness and thus save installation space.Recesses 116 and 126 are each potted with a potting compound 406 to ensure better thermal dissipation from the embedded electronic components 106 and / or to ensure touch safety for the components 106 and / or to protect the components 106 from chemical influences. Potting can be performed using typical potting compounds. These can be, for example, two-component materials, solvent-based materials, UV-curing resins, or granules for compression.

[0050] Recommended materials can be based on epoxies or polyurethanes, for example. For increased thermal conductivity, a polymer support matrix can be filled with thermally conductive materials such as zinc oxide, titanium oxide, or aluminum oxide.

[0051] In Fig. Figure 5 shows a schematic representation of a circuit board 500 structure with an electronic component 502 installed without a housing according to an embodiment of the method according to the invention. Semiconductor components without a housing, so-called bare dies, can be inserted into the recesses using connection technologies commonly used in circuit board construction, such as soldering. Installing such an electronic component 502 without a housing offers the advantage of higher thermal connection, lower connection inductance and lower connection resistance, smaller space requirements, and therefore higher power density, at overall lower costs. Electrical contacting, particularly for contacts located on the top side of the component 502, is advantageously carried out using wire bonding 504, as is also customary in semiconductor housings according to the prior art.Particularly when installing unencapsulated semiconductor chips, filling the recess is indicated to shield the component 502 from chemical influences, such as oxidation, moisture, and light. For this purpose, the encapsulating material 506 is advantageously as optically opaque as possible in the spectral range critical for the semiconductor chip. Suitable materials include, for example, epoxy, pre-impregnated fiber materials such as prepreg, polyurethanes, silicones, or thermoplastics.

[0052] In Fig. 6 shows a schematic representation of a circuit board 600 with an electronic component installed without a housing and connected by vias according to an embodiment of the method according to the invention. The electronic component 602 is connected by the Fig. 2 with reference number 202 designated insulation layer of the in Fig. 2 with reference numeral 206. If a contact surface of an electronic component 602, for example a semiconductor chip, is located on its underside, this can be connected to a metallization layer of the intermediate layer and / or a metallic inlay 112 via the galvanized vias, designated in one example by reference numeral 606. The corresponding connection surfaces of the semiconductor are technically treated like an inlay. The galvanic deposition can be carried out using two or more different materials for better adhesion, for example titanium or chromium followed by copper, aluminum, or silver. Gold as a final layer can limit chemical influences on the component 602 and corrosion of the component 602. Silver, on the other hand, can improve conductivity.The galvanic deposition automatically creates a continuous electrical and thermal conductivity from the corresponding contact surface of the electronic component to the corresponding conductor track within the circuit board.

[0053] In Fig.Figure 7 shows a schematic representation of a three-dimensional view of a circuit board 700 manufactured according to an embodiment of the method according to the invention. The metallic inlays 112 and 122, an intermediate piece 714 made of a non-conductive material, e.g., epoxy or pressed-in prepreg, located in a gap, intermediate layers 718 formed of non-conductive material and / or solder resist, or top / bottom terminations made of non-conductive material 202, and the conductor track structure 716 located thereon, finally covered with solder resist 702, are shown here in their planar extent. A connection between the metallic inlays 122 and the metallization areas 712, here for a so-called drain connection, and 722, here for a so-called source connection, is formed by vias, e.g., shown by reference numeral 710.Finally, an electronic component 704, here an SMD transistor, is shown within a recess in the upper inlay layer. Visible are the contacts between source terminal 708 and metallization area 722, as well as between gate terminal 706 and a conductor track 720.

Claims

[1] Method for producing a circuit board (100, 220, 300, 400, 500, 600, 700) for power electronic circuits, in which the circuit board (100, 220, 300, 400, 500, 600, 700) comprises at least two inlay layers, wherein a respective inlay layer has a metallic inlay (112, 122) whose thickness is in the millimeter range, wherein spaces between the metallic inlay (112, 122) are filled with a non-conductive material (114, 124, 204, 714), wherein a respective intermediate layer (102, 718) with at least one metallization layer is arranged between at least two adjacent inlay layers, wherein the respective intermediate layer (102, 718) has a plurality of vias to an inlay layer covered by it, and wherein at least one recess (116, 126) is provided in at least one first inlay layer, which recess is designed to mount at least one electronic component (106, 502, 602, 704), namely at least one power electronic component, on a second inlay layer, wherein, in order to provide a screwing point for the circuit board (100, 220, 300, 400, 500, 600, 700) in an inlay layer, a part of a metallic inlay (112, 122) protrudes a distance from the circuit board (100, 220, 300, 400, 500, 600, 700). [2] Method according to claim 1, wherein a respective inlay layer is covered by at least one insulation layer (202). [3] Method according to claim 2, wherein the at least one insulation layer (202) is provided with a plurality of vias (302, 606) to the inlay layer covered thereby. [4] Method according to one of claims 1 to 3, wherein at least one recess is provided in at least one intermediate layer, wherein the at least one recess is congruent or aligned with a respective recess of an adjacent inlay layer. [5] Method according to one of claims 1 to 4, in which a respective intermediate layer (206, 718) is provided with a plurality of vias (302, 606, 710) to a respective inlay layer adjacent to the respective intermediate layer. [6] Method according to one of the preceding claims, in which at least one recess of an inlay layer is filled with an insulating material (406, 506). [7] Board (100, 220, 300, 400, 500, 600, 700) for power electronic circuits, which has at least two inlay layers, wherein a respective inlay layer consists of a metallic inlay (112, 122) whose thickness is in the millimeter range and a non-conductive material (114, 124, 204, 714) which fills spaces between the metallic inlay (112, 122), wherein a respective intermediate layer (102, 718) with at least one metallization layer is arranged between at least two adjacent inlay layers, wherein the respective intermediate layer (102, 718) has a plurality of vias to an inlay layer covered by it, wherein at least one first inlay layer has at least one recess (116, 126) whose size is designed so that at least one electronic component (106, 502, 602, 704), namely at least one power electronic component, is mounted on a second inlay layer, wherein, in order to provide a screwing point for the circuit board (100, 220, 300, 400, 500, 600, 700) in an inlay layer, a part of a metallic inlay (112, 122) protrudes a distance from the circuit board (100, 220, 300, 400, 500, 600, 700). [8] Circuit board (100, 220, 300, 400, 500, 600, 700) according to claim 7, wherein at least one inlay layer is covered by at least one insulation layer (202) having a plurality of vias (302, 606). [9] Circuit board according to claim 7 or 8, wherein at least one electronic component (106, 502) is installed within at least one recess of an inlay layer and the at least one recess is filled with an insulating material (406, 506).

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